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* PI3USB9238: Read device type and charge registers after INTB assertionstabilize-11647.70.Bstabilize-11647.104.Brelease-R73-11647.BDaisuke Nojiri2019-01-242-42/+85
| | | | | | | | | | | | | | | | | | | | | | | PI3USB9238 can fail to detect BC 1.2 charger because the initialization timing after reset differs chip to chip. This patch checks the interrupt register in a loop to wait until device type and charger status registers are ready. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/119166282 BRANCH=nami TEST=Verify BC 1.2 chargers are reliably detected as DCP (wall-charger), CDP (type-A port on chromebook), and SDP (type-c port on chromebook) by type-c port of Vayne (via A-to-C cable). Change-Id: I970007723fcff5e2818765705d534d1a581b33e7 Reviewed-on: https://chromium-review.googlesource.com/1399202 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* arcada: remove executable flag from all filesJett Rink2019-01-245-0/+0
| | | | | | | | | | | | Files in board/arcada_ish are all marked as executable. Fixing. BRANCH=none BUG=none TEST=presubmit passes Change-Id: I65da8acb83e55b91c2fca870b0b85648aa145451 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1432315
* casta : implement ledYongBeum Ha2019-01-244-4/+132
| | | | | | | | | | | BUG=b:122489253 BRANCH=master TEST=build, flash ec and check led. Change-Id: I9eaa6f2763c08eaae10fba65fab18548f703e669 Signed-off-by: YongBeum Ha <ybha@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/1428499 Reviewed-by: Diana Z <dzigterman@chromium.org>
* scarlet: Lower the charging voltagePhilip Chen2019-01-241-2/+2
| | | | | | | | | | | | | | | | | | | The battery spec states the maximal charging voltage is 4.42V. Considering +-1% of voltage accuracy from rt9467, we should lower the charging voltage to ensure it never hits 4.42V. BUG=b:118799175 BRANCH=scarlet TEST=make BOARD=scarlet Change-Id: I8a2f01d64ccb0750b1d5e4d4af586faf307d7b9d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1431552 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* build: add centroiding C++ supportRong Chang2019-01-243-2/+5
| | | | | | | | | | | | | | | | Centroiding source is in C++. This CL removes -W flags only for building C files from CFLAGS and also prevents typedef existing C++ keyword wchar_t. BUG=b:120961468 BRANCH=none TEST=make buildall Change-Id: Ifb8793a8e7e69b26a742b7dbf70289747a0ee7b3 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1372874 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Tai-Hsu Lin <sheckylin@chromium.org>
* casta : Add battery informationYongBeum Ha2019-01-243-3/+167
| | | | | | | | | | | | | | | | Casta uses same battery as nautilus. BUG=b:122868858 BRANCH=octopus TEST=make -j buildall; flash EC & check battery information Change-Id: I55894821744d242958c2dcf31da355b315d9ac8f Signed-off-by: YongBeum Ha <ybha@samsung.com> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1385764 Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1430740 Reviewed-by: Jett Rink <jettrink@chromium.org>
* powerbtn/button: fix crash on 0ms sleepRuben Rodriguez Buchillon2019-01-242-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | This change guards against crashing the EC when calling button or powerbtn with a 0 as the argument. BRANCH=None BUG=chromium:905829 TEST=manual testing on soraka > powerbtn 0 Simulating 0 ms power button press. Simulating power button release. > button vup 0 > Change-Id: I022c9e48b0977b71b8706e5ffe8356a226a59077 Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1428500 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* octopus/ampton: disable espi pad when system goes into G3Dino Li2019-01-241-0/+20
| | | | | | | | | | | | | | | | | | On Ampton, the EC's power consumption is about 5.5mA on battery mode in G3 state. This is because EC unable to go into low power mode properly in idle task when eSPI CS# pin is low. So we disable eSPI pad when system goes into G3 state to reduce power number. BUG=b:121105042 BRANCH=none TEST=On Ampton, EC power rail drops to about 1.1mA in G3. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I1c85bd0e909936e7f143b15b5e9b7c1884d5cc62 Reviewed-on: https://chromium-review.googlesource.com/1426304 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* hatch: Add support for power sequencingScott Collyer2019-01-246-2/+140
| | | | | | | | | | | | | | | | This CL adds config options, board specific functions and GPIO signals required to add power sequencing support. BRANCH=none BUG=b:122251649 TEST=make buildall, verified at factory that AP reaches S0 Change-Id: I5c7e8331b0f46a830b6e0f6722e7b05ba05212cb Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1377571 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cometlake: Add power sequencing support for cometlake chipsetScott Collyer2019-01-245-2/+172
| | | | | | | | | | | | | | | This CL adds cometlake specific portions of power sequencing. BRANCH=none BUG=b:122251649 TEST=make buildall, verified in factory that AP gets to S0 Change-Id: I84726cd522ab55ca9ec095b94392ffa387fb253f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1377570 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* hatch: Initial skeleton for hatchScott Collyer2019-01-249-0/+221
| | | | | | | | | | | | | | | | | | This CL adds hatch in /board and /baseboard. Only some GPIO signals, flash configuration, and I2C port map/pins required for NPCX to successfully build have been included. BRANCH=none BUG=b:122251649 TEST=make buildall Change-Id: Ief19223473f31b1f3a55e1466cc47d7cfeef8060 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1377569 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mt_scp: Add support to store some code in DRAMNicolas Boichat2019-01-247-1/+61
| | | | | | | | | | | | | | | | | This allows to store specific code/data in a .dram region. This is used by mt_scp to run code off DRAM, as we plan to have more code than what can fit in SRAM. BRANCH=none BUG=b:122058243 TEST=make BOARD=kukui_scp -j objdump -x build/kukui_scp/ec.obj => Some code is loaded in DRAM TEST=Load kukui_scp, icachetest works Change-Id: Idbab809ba86cabe3b984944adc2781b37d2d544b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1391542
* mt_scp: Enable I/D-cache on bootNicolas Boichat2019-01-243-7/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable cache mapping on boot, add functions for cache support. Invalidate the cache on boot, and add benchmarching function. BRANCH=none BUG=b:117804463 TEST=Boot kukui_scp with TEST-ONLY CL. TEST=Run dcachetest command, see performance difference, and lack of coherency if the data is updated from AP side. > dcachetest cached: 19745 us (val: ef915230) cached+inval: 39402 us (val: ef915230) direct: 94096 us (val: ef915230) TEST=See that icachetest (cached) and perftest have similar performance: > icachetest run from DRAM (cached): 102779 us (total: 12a052eb9) run from DRAM (direct): 1867168 us (total: 12a052eb9) > perftest run from SRAM: 102566 us (total: 12a052eb9) TEST=cacheinfo reports sensible data: > cacheinfo Icache hit count: 12000127 Icache access count: 12000131 Dcache hit count: 960034 Dcache access count: 1024034 Change-Id: I3272f4ff9edc0059c4937908b1235346c582c680 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1391529 Reviewed-by: Rong Chang <rongchang@chromium.org>
* mt_scp/memmap: Enable memmap between AP and SCP.Yilun Lin2019-01-245-23/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCP/AP can access the AP/SCP address via memory address translation. TEST=Run memmap (TEST-ONLY CL), see direct mapping makes sense: Direct mapping: 00001000 INVAL 0f002000 INVAL 10003000 INVAL 1f004000 INVAL 20005000 40005000 => 20005000 OK 2f006000 4f006000 => 2f006000 OK 30007000 50007000 => 30007000 OK 3f008000 5f008000 => 3f008000 OK 40009000 INVAL 4f00a000 INVAL 5000b000 INVAL 5f00c000 INVAL 6000d000 6000d000 => 6000d000 OK 6f00e000 6f00e000 => 6f00e000 OK 7000f000 7000f000 => 7000f000 OK 7f010000 7f010000 => 7f010000 OK 80011000 80011000 => 80011000 OK 8f012000 8f012000 => 8f012000 OK 90013000 00013000 => 90013000 OK 9f014000 0f014000 => 9f014000 OK a0015000 10015000 => a0015000 OK af016000 1f016000 => af016000 OK b0017000 20017000 => b0017000 OK bf018000 2f018000 => bf018000 OK c0019000 30019000 => c0019000 OK cf01a000 3f01a000 => cf01a000 OK d001b000 1001b000 => a001b000 BAD df01c000 1f01c000 => af01c000 BAD (these are ok as 0x1* is mapped from both 0xd* and 0xa*) e001d000 a001d000 => e001d000 OK ef01e000 af01e000 => ef01e000 OK f001f000 9001f000 => f001f000 OK ff020000 9f020000 => ff020000 OK BRANCH=None BUG=b:114326670 Change-Id: I29298c2e5a897d08d21390c751bdd881170adb59 Signed-off-by: Yilun Lin <yllin@google.com> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1385910 Reviewed-by: Erin Lo <erin.lo@mediatek.com> Reviewed-by: Rong Chang <rongchang@chromium.org>
* kukui: Add BOARD_REV 2 configs.Yilun Lin2019-01-234-4/+50
| | | | | | | | | | | | | | TEST=BOOTBLOCK=... make BOARD=kukui -j flash_ec; and see AP boots. BUG=b:122993147 BRANCH=None Change-Id: I1f76d87aa152ba3c3d7c8697140c7c4769b55d28 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1420247 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* rammus: fix incorrect power mode configuration for the USB Type-AZhuohao Lee2019-01-231-0/+2
| | | | | | | | | | | | | | | | | On Rammus, the power mode of the USB Type-A is CDP. However, the default configuration is SDP2. We don't meet any problem on previous setting because of missing CONFIG_USB_PORT_POWER_SMART_INVERTED. This patch fixes the incorrect CONFIG in board.h. BUG=none BRANCH=firmware-rammus-11275 TEST=make -j buildall connect phone to type-a port, CDP works Change-Id: I19a6f2c01faa452131fa036a28be2fc37ce06e58 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1424039 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Ampton: tune motion sensorsJames_Chao2019-01-231-1/+7
| | | | | | | | | | | | | | BUG=b:118756407 BRANCH=octopus TEST=On Ampton EVT, Check the x,y,z direction is correct. Change-Id: Ia84d5db0723d8b24e7725333f35d466b7438598b Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1425138 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* flash_ec: add "--read" and "--verify" flags for stm32 chip.Namyoon Woo2019-01-231-14/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "--read" takes a following string as a path to store the image file. If it is specified, flash_ec reads only an EC firmware image and store it to the given path, but does not program EC firmware. "--verify" lets flash_ec read EC firmware image after flashing it, and compare the read image to the source image to check if they match. These two flags are supported for stm32 chip only for now. CQ-DEPEND=CL:1394284 BUG=b:112163028 BRANCH=none TEST=manually ran flash_ec on scarlet. util/flash_ec --board scarlet --image ${IMG_PATH} --verify --bitbang_rate 57600 --logfile /tmp/flash_ec.log util/flash_ec --board scarlet --read ${TEMP_IMG_PATH} --bitbang_rate 57600 --logfile /tmp/flash_ec.log util/flash_ec --chip stm32 --raiden --image ${IMG_PATH} --verify --bitbang_rate 57600 --verbose --logfile /tmp/flash_ec.log util/flash_ec --chip stm32 --raiden --read ${TEMP_IMG_PATH} --bitbang_rate 57600 --verbose --logfile /tmp/flash_ec.log Change-Id: I0913da7b8bf51313c7ff758a1ed3250a88c13b54 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1409497 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* util/ectool: Update usages for cros_scp.Yilun Lin2019-01-221-2/+2
| | | | | | | | | | | | | | | | | cros_scp uses cros_ec_dev kernel driver, additional implementation is not needed. TEST=use "ectool --name=cros_scp version" in AP console, and see the version info. BRANCH=None BUG=b:114326670 Change-Id: Ie01fc4e3463d42daecf3c02302f8863aabfaa7da Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1424044 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: Use coreboot-sdk by default.Yilun Lin2019-01-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kukui has a very limited size for RO image. We found that using coreboot-sdk brings us a lot of extra space on kukui, so we decide to use coreboot-sdk BRANCH=None BUG=b:122874284 TEST=build both targes with emerge-kukui coreboot && make BOARD=kukui -B -j \ BOOTBLOCK=/build/kukui/firmware/kukui/coreboot/bootblock.bin and compare the results of grep hey build/kukui/RO/ec.RO.map 1. with coreboot-sdk 0x000000000001d7c8 __hey_flash_used = ((LOADADDR (.data) + SIZEOF ... 0x000000000001d7c8 __image_size = __hey_flash_used 2. without coreboot-sdk 0x000000000001df48 __hey_flash_used = ((LOADADDR (.data) + SIZEOF ... 0x000000000001df48 __image_size = __hey_flash_used and it saves 1940 byte in this case. Change-Id: Ic856db7d17a23df01b91152868eddb0920c3b069 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1424045 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* Nami: Re-enable search key scanning on SyndraDaisuke Nojiri2019-01-221-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | Search key coordinate was moved to col=0,row=3 on Ekko and Bard and CL 1343640 was merged to adjust the scan mask. Syndra doesn't have this move. So, this patch will make the search key scanned like before while keeping the previous change applied to only Ekko & Bard. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:119798830 BRANCH=none TEST=Verify search key works on Syndra, Sona, Ekko, and Bard. Change-Id: Ia672383ca8df8e2e212c8c9deb0410c968e357e4 Reviewed-on: https://chromium-review.googlesource.com/c/1366300 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1426152 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx: add enable/disable espi pad functionDino Li2019-01-223-4/+18
| | | | | | | | | | | | | | | We can call this function to enable/disable espi pad if needed. BUG=b:121105042 BRANCH=none TEST=buildall Change-Id: I61561b1a4657947e27053de3e8b2ef053651d949 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1426303 Commit-Ready: Justin TerAvest <teravest@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: REFRESH+PWR combinatinon to enter recovery modeDuncan Laurie2019-01-223-4/+111
| | | | | | | | | | | | | | | | | | | | | | | Add support for entering recovery mode via the REFRESH_PWR key combination. This is needed on a platform with a closed source EC when the EC cannot be trusted to handle the normal ESC+REFRRESH+PWR combination. Add an interrupt handler for the RBOX key combo and when it is detected, generate an EC reset pulse via RBOX. The recovery state is latched into NVMEM so it can be queried by coreboot/verstage on the next boot. This change also ensures that all EC resets initiated by the Cr50 have a minimum pulse width of 30 ms to meet the EC requirement. BUG=b:122715254,b:119275910, BRANCH=cr50 TEST=make buildall. Verified boot to recovery mode screen after pressing REFRESH+PWR. Verified recovery mode entry from S0 and S5 states. Change-Id: I840ee1024bbfba00e47050eeb8b1ede244148c05 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389061 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* tcpm/it83xx.c: don't reload cc parameter settings for DxRuibin Chang2019-01-222-0/+4
| | | | | | | | | | | | | | | | | | The USB-PD PHY trimming value is reloaded wrongly after software reset. BUG=b:123173731 BRANCH=none TEST=cc parameters are the same, after ec software reset and hardware reset on Bx and Dx. Change-Id: I0c7144afbb648680bb60cc128c8212abb43ccd68 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1426300 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* kukui: Remove BOARD_REV 0 GPIO configs.Yilun Lin2019-01-224-28/+1
| | | | | | | | | | | | | | | We don't use P0 boards anymore, so let's remove P0 GPIO configs. TEST=make BOARD=kukui -j BUG=b:122993147 BRANCH=None Change-Id: I1859c4c9b182a0acee6e314e8c06fb34a3973f10 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1420246 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* LSM6: Throw out junk data after ODR changesDiana Z2019-01-192-15/+34
| | | | | | | | | | | | | | | | | | | | | | | | After an ODR change on the LSM6DSx sensor, a certain amount of data will be invalid until the filter for the sensor settles. This change is to throw out datapoints after an ODR change to avoid sending the AP any outright bad values. Currently, we're waiting for clarification from ST about how many data points to throw out and whether the accelerometer and gyroscope ODR changes affect each other. For now, we're being conservative and throwing out 4 samples of any sensors on after an ODR change. BUG=b:122912601 BRANCH=octopus TEST=almost all standard deviation failures gone when running CTS on phaser360, a few very close gyro errors remain Change-Id: Ie00c85e18333ce578152ed3ac616815405e8111d Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1423123 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* LSM6: Follow ODR change procedure from application notesDiana Z2019-01-193-31/+52
| | | | | | | | | | | | | | | | | | There are a few ways the current driver differs from the application notes for the LSM6DS3, notably: - FIFO disable is done before any ODR registers are set - FIFO ODR is set before any FIFO decimations BUG=b:122912601 BRANCH=octopus TEST=used "ectool" to change ODR values on phaser360, ensured "accelinfo on" output looked sane with the exception of points which will be discarded next CL Change-Id: I39fdcc67d0b34382a348dc2442785a847a4bc68d Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1419123 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec_commands: Fix errors spotted by kernel checkpatchGwendal Grignou2019-01-191-13/+27
| | | | | | | | | | | | | | | | | To ease sync with kernel, fix errors found when merging ec_commands.h into kernel tree: - fix multiline comments - defined out BUILD_ASSERT, kernel has different macros for asserting at compilation time (BUILD_BUG_ON_...) can only be used within functions. BRANCH=none BUG=none TEST=Compile. Change-Id: I196a144e0d3392ffd12352b08d5bc9bda9b189ad Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1412641 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "Remove fuzzer test runs from buildall."Allen Webb2019-01-191-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1d9dbd408f7d837cb2725ed0e37d775967f6bb21. Reason for revert: There is a compiler fix in llvm r351247. Original change's description: > Remove fuzzer test runs from buildall. > > This removes the test runs for fuzzer targets temporarily until > crbug.com/918662 is resolved. > > BRANCH=None > BUG=chromium:918662 > TEST=make -j buildall > > Change-Id: I80b9c4cd403924e41704462277da6d288796abc8 > Signed-off-by: Allen Webb <allenwebb@google.com> > Reviewed-on: https://chromium-review.googlesource.com/1399201 > Reviewed-by: Manoj Gupta <manojgupta@chromium.org> Bug: chromium:918662 Change-Id: I002046822af9550312f6a88828331637c83e4682 Reviewed-on: https://chromium-review.googlesource.com/1418250 Commit-Ready: Allen Webb <allenwebb@google.com> Tested-by: Allen Webb <allenwebb@google.com> Reviewed-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Allen Webb <allenwebb@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: Fix adc read crashes EC.Yilun Lin2019-01-191-8/+0
| | | | | | | | | | | | | | | | | | | | The ADC module is diabled after reading the BOARD_ID on system booted. This will hang the adc reading once we commanding "adc" to EC after that, and thus triggers wathdog. TEST=BOOTBLOCK=... make BOARD=kukui -j flash_ec. See AP booted; type "adc" in EC console, and see that it won't trigger watchdog. BRANCH=None BUG=b:122995670 Change-Id: Id13d6ceddf74a06b741ab0c834c75409ab580c74 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1416074 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nocturne: Check IRQ and HPD in DPStatus message.Aseda Aboagye2019-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Per the VESA DisplayPort Alt Mode on USB Type-C spec, IRQ_HPD indicates that a high to low followed by a low to high transition was detected. Therefore, we should be checking when IRQ is high and HPD is low is received as that is an error. This commit fixes that bug where were comparing our level to the GPU instead of what was shown in the PDO. BUG=none BRANCH=firmware-nocturne-10984.B TEST=Flash nocturne, plug in Apple Multiport AV USB-C adapter, verify that external display works. Change-Id: I536dd0d2556794411eb8d54a9a0c34f61fff5253 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1422458 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Benson Leung <bleung@google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 3ed2914348316dd04a4eede7d2f7b1ce0f9434b1) Reviewed-on: https://chromium-review.googlesource.com/1422460 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: only apply internal EC_WP_L pullup when neededCaveh Jalali2019-01-193-1/+11
| | | | | | | | | | | | | | | | | we had applied an internal pullup on the EC side to the EC_WP_L signal to work around a problem. we now have a board level fix on newer boards, so we should only apply this workaround on older boards. BUG=b:122568899,b:116670191 BRANCH=stabilize-atlas-11512.6.B TEST=verified older boards still read EC_WP_L as high Change-Id: Ia95b8649eed240a7c97c6b1cc20ed5ccea40e4f2 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1407245 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* cleanup/ish: update copyright header to styleJett Rink2019-01-1910-10/+10
| | | | | | | | | | | | | (c) Copyright header is no longer the style. Update so presubmit check stops complaining BRANCH=none BUG=none TEST=presumbit no longer complains Change-Id: I0de5558467859cf0b735545161ed9d1c08e0fae4 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1422057
* kukui_scp: Change IPI index.Yilun Lin2019-01-181-7/+7
| | | | | | | | | | | | | | | | Change the IPI index per request in b/122985583. TEST=make BOARD=kukui_scp -j BUG=b:122985583 BRANCH=None Change-Id: Ifed6bf747d6ac1625769aacd57b92f96978eed51 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1420249 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-by: Erin Lo <erin.lo@mediatek.com>
* mt_scp/ipi: Fix typo in IPI macro check.Yilun Lin2019-01-181-1/+1
| | | | | | | | | | | | | TEST=make BOARD=kukui_scp -j BUG=None BRANCH=None Change-Id: I18cef1540fd3fe76269a16edab6c622084417c7e Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1420248 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Pi-Hsun Shih <pihsun@chromium.org>
* drvier: lsm6dsm: Populate Gyroscope scale properlyGwendal Grignou2019-01-196-40/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Range of 250/1000/2000 dps is an approximation. The Gyrscope uses a slighly higher range: range | gain(udps/LSB) | actual value(dps) 250 | 8750 | 286.72 500 | 17500 | 573.44 1000 | 35000 | 1146.88 2000 | 70000 | 2293.76 Returns the actual value for a given range. BUG=b:121279721 BRANCH=octopus TEST=Check scale returns the correct value: cd /sys/bus/iio/devices/... for i in 250 500 1000 2000 ; do echo $i > scale ; V=$(cat scale) ; echo -n "$i: " ; echo -n "$V: " ; echo $V | python -c 'import sys for line in sys.stdin: print float(line) * 32768 * 180 / 3.14159' ; done 250: 0.000152331: 285.996835182 500: 0.000305197: 572.998116648 1000: 0.000610395: 1145.99811077 2000: 0.001221325: 2293.00066781 Check CTS Verifier Gyroscope Measurement Test pass. Change-Id: I76c977140321d01702af16f58a3dfb7036673014 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1423597 Reviewed-by: Enrico Granata <egranata@chromium.org>
* Ampton: add battery configuration for C424James_Chao2019-01-182-0/+28
| | | | | | | | | | | | | | BUG=none BRANCH=octopus TEST=build Change-Id: Ib97e5a0184c9d8f636655713f0ee3bac4d973ebc Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1401886 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* LSM6: Correct timestamp reporting and FIFO lengthDiana Z2019-01-172-8/+12
| | | | | | | | | | | | | | | | | | | When an accelerometer sends a sample to the motion_sense task with a timestamp, the timestamp should represent the time of the IRQ which caused the FIFO read. This change caches a timestamp after the accelerometer data is read to use when pushing all data from that read. This also corrects the number of bits in the FIFO length field. BRANCH=octopus BUG=b:120679547 TEST=builds, phaser360 CTS pass rate unaffected Change-Id: I220aa2e8fa23af3f7833999cdfac966e8695c831 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1413670 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* apel: lower input voltage to 5V when battery fullJett Rink2019-01-171-1/+27
| | | | | | | | | | | | | | | For ERP compliance, we want to ensure that we are using the least amount of power when the device is in S5 and plugged into AC power. BRANCH=octopus BUG=b:113830171 TEST=passes ERP Change-Id: I91f44de96bdab86edabc5031cb92eaa70b9a39b3 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1406852 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* cr50: Support closed source customer diagnostic modeKeith Short2019-01-173-3/+25
| | | | | | | | | | | | | | | | Drives OEM specific GPIOS to enable diagnostic mode on a closed source EC. BUG=b:122312536 BRANCH=cr50 TEST=make buildall. Verified GPIO states with scope at boot and after sending TPM disable command from the AP. Diagnostic mode is cleared on reboot. Change-Id: Id7c9d7e5cc63e5e6f56451ceaca04eeddb254f7d Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1394692 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* ish: balance all __in_isr callsJett Rink2019-01-172-8/+9
| | | | | | | | | | | | | | | | If we encountered an unregistered IRQ vector we would not decrement the __in_isr global properly which would cause the ISH to lock up. BRANCH=none BUG=b:121343650,b:112750896 TEST=With patch stack on arcada (ISH5) 'taskinfo' command works as expected. Change-Id: I3975356226d92a81bfd207d77bba42f3f8b30bb8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1392416 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* driver/ppc/nx20p348.c: Handle overcurrent eventKarthikeyan Ramasubramanian2019-01-171-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the overcurrent event is logged but not handled. Report the overcurrent event to the USB PD framework which in turn will handle the overcurrent event further. BUG=b:115475862 BRANCH=octopus TEST=Boot to ChromeOS in grabbiter. No overcurrent events reported when the sink is drawing <= 3.20 A. Overcurrent events are reported when the sink is drawing > 3.25 A. After 3 reports, the port is latched off and power delivery is stopped. The port is re-enabled only after the sink is disconnected. Also when the sink is drawing current at 3.24 A, there is one report of overcurrent. The port gets disabled in response to that event. But the port is re-enabled after 1 second since overcurrent event is reported only once. After the port is re-enabled, the sink is able to draw the set current. When the overcurrent event is reported, I can see in the kernel logs that the overcurrent condition is detected by the kernel. EC Logs: [3391.984462 C1: PPC detected Vbus overcurrent!] [3391.984953 C1: overcurrent!] [3392.044935 C1: PPC detected Vbus overcurrent!] [3392.045425 C1: overcurrent!] [3392.061404 C1: PPC detected Vbus overcurrent!] [3392.061894 C1: overcurrent!] [3392.062142 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.077226 C1: PPC detected Vbus overcurrent!] [3392.077532 C1: overcurrent!] [3392.077891 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.092660 C1: PPC detected Vbus overcurrent!] [3392.092966 C1: overcurrent!] [3392.093213 C1: OC event limit reached! Source path disabled until physical disconnect.] Kernel Logs: [ 3356.560456] usb usb2-port1: over-current condition [ 3356.768434] usb usb2-port2: over-current condition [ 3356.976446] usb usb2-port4: over-current condition [ 3357.184441] usb usb2-port5: over-current condition [ 3357.392445] usb usb2-port6: over-current condition Change-Id: I0af69a132fdd1dd5bab4d530c3b060b2a5aea501 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/1412448 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* board/octopus: Notify SoC about USB overcurrentKarthikeyan Ramasubramanian2019-01-176-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add board_overcurrent_event function to notify SoC about USB-C overcurrent events. BUG=b:115475862 BRANCH=octopus TEST=Boot to ChromeOS in grabbiter. No overcurrent events reported when the sink is drawing <= 3.20 A. Overcurrent events are reported when the sink is drawing > 3.25 A. After 3 reports, the port is latched off and power delivery is stopped. The port is re-enabled only after the sink is disconnected. Also when the sink is drawing current at 3.24 A, there is one report of overcurrent. The port gets disabled in response to that event. But the port is re-enabled after 1 second since overcurrent event is reported only once. After the port is re-enabled, the sink is able to draw the set current. When the overcurrent event is reported, I can see in the kernel logs that the overcurrent condition is detected by the kernel. EC Logs: [3391.984462 C1: PPC detected Vbus overcurrent!] [3391.984953 C1: overcurrent!] [3392.044935 C1: PPC detected Vbus overcurrent!] [3392.045425 C1: overcurrent!] [3392.061404 C1: PPC detected Vbus overcurrent!] [3392.061894 C1: overcurrent!] [3392.062142 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.077226 C1: PPC detected Vbus overcurrent!] [3392.077532 C1: overcurrent!] [3392.077891 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.092660 C1: PPC detected Vbus overcurrent!] [3392.092966 C1: overcurrent!] [3392.093213 C1: OC event limit reached! Source path disabled until physical disconnect.] Kernel Logs: [ 3356.560456] usb usb2-port1: over-current condition [ 3356.768434] usb usb2-port2: over-current condition [ 3356.976446] usb usb2-port4: over-current condition [ 3357.184441] usb usb2-port5: over-current condition [ 3357.392445] usb usb2-port6: over-current condition Change-Id: I69fdc473a3489922517dc91fc1ea149aabca01cb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/1410142 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* USB PD: PPC: Add overcurrent handling.Aseda Aboagye2019-01-1714-38/+307
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Type-C Power Path Controllers provide overcurrent protection. This commit adds support into the USB PD task for overcurrent events while we are in source role. The USB PD 3.0 spec recommends that ports issue a hard reset when an overcurrent condition occurs on a port. Additionally, we'll allow a source port to overcurrent 3 times before latching off VBUS from the port entirely. The source path will be re-enabled after ~1s after each overcurrent event. BUG=b:69935262,b:114680657 BRANCH=None TEST=Boot to ChromeOS in grabbiter. No overcurrent events reported when the sink is drawing <= 3.20 A. Overcurrent events are reported when the sink is drawing > 3.25 A. After 3 reports, the port is latched off and power delivery is stopped. The port is re-enabled only after the sink is disconnected. Also when the sink is drawing current at 3.24 A, there is one report of overcurrent. The port gets disabled in response to that event. But the port is re-enabled after 1 second since overcurrent event is reported only once. After the port is re-enabled, the sink is able to draw the set current. When the overcurrent event is reported, I can see in the kernel logs that the overcurrent condition is detected by the kernel. EC Logs: [3391.984462 C1: PPC detected Vbus overcurrent!] [3391.984953 C1: overcurrent!] [3392.044935 C1: PPC detected Vbus overcurrent!] [3392.045425 C1: overcurrent!] [3392.061404 C1: PPC detected Vbus overcurrent!] [3392.061894 C1: overcurrent!] [3392.062142 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.077226 C1: PPC detected Vbus overcurrent!] [3392.077532 C1: overcurrent!] [3392.077891 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.092660 C1: PPC detected Vbus overcurrent!] [3392.092966 C1: overcurrent!] [3392.093213 C1: OC event limit reached! Source path disabled until physical disconnect.] Kernel Logs: [ 3356.560456] usb usb2-port1: over-current condition [ 3356.768434] usb usb2-port2: over-current condition [ 3356.976446] usb usb2-port4: over-current condition [ 3357.184441] usb usb2-port5: over-current condition [ 3357.392445] usb usb2-port6: over-current condition Change-Id: Ib070f261e98264cd88725ebce7d10e0798267e3b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1286300 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/807633 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ectool: Check address of comm_init_lpc/_i2c before calling themDaisuke Nojiri2019-01-171-2/+4
| | | | | | | | | | | | | | | | | | | This patch makes ectool check the address of comm_init_lpc and comm_init_i2c before calling them. Related bug:b/35571850 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/122478187 BRANCH=none TEST=buildall Change-Id: I32499174d7f82e45941cd97cf7780ea04517115f Reviewed-on: https://chromium-review.googlesource.com/1414706 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com>
* ish: add inline math functionsRong Chang2019-01-171-1/+203
| | | | | | | | | | | | | | | | | This change adds inline math functions: logf(), expf(), powf(), ceilf(), atan2f(), atanf(), sinf(), cosf(), acosf() BUG=b:120961468 BRANCH=none TEST=none Change-Id: I92460b332b24b6d9971ce989c0cd799111cdd239 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1077709 Reviewed-by: Tai-Hsu Lin <sheckylin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: update copyright header to match styleJett Rink2019-01-1713-13/+13
| | | | | | | | | | | | | Without this fix presubmit checks complain when touching files BRANCH=none BUG=none TEST=no presumbit complains Change-Id: I2c30865d2782642d4030bc3d922ff92212ff97e8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1415830 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* usb_mux_virtual: Update the virtual MUX when HPD level or irq changesVijay Hiremath2019-01-173-14/+35
| | | | | | | | | | | | | | | | | | | HPD level changes when there is an attach or detach event of the HPD. Hence virtual MUX level need to be updated with the current HPD level and a host notification needs to be sent so that host can configure the HPD MUX. BUG=b:118477809 BRANCH=none TEST=Manually tested on Dragonegg, observed HPD event updated by EC is received by Kernel MUX driver. Change-Id: Ib916ebb3f6cbcfe2cb3e738f5b3e14d29e1bc27c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1340491 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* checkpatch: reinstate check for C99 style commentsVadim Bendebury2019-01-161-0/+2
| | | | | | | | | | | | | | | Recent update of checkpatch.pl made it ignore C99 style comment in the new patches. This change will reinstate the check. BRANCH=none BUG=none TEST=attempt to repo upload patches with C99 style comments fail at pre-upload check phase. Change-Id: I606e2618cc39abcf2dc0b051aefea722a2359f3b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1409495 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kukui: Take scarlet charger workaround CLs.Yilun Lin2019-01-161-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | This CL squashed several scarlet charger fixes. https://crrev.com/c/1055194 scarlet: Clamp reported battery SOC when charge terminates https://crrev.com/c/1200416 scarlet: Limit PD max voltage in a special case https://crrev.com/c/1311753 scarlet: Throttle PD voltage based on battery level https://crrev.com/c/1338601 scarlet: Consider power state transition when throttling PD https://crrev.com/c/1344799 scarlet: Limit PD voltage when battery SOC > 85% https://crrev.com/c/1378765 scarlet: Throttle PD voltage regardless of power state In general, it reduces the PD charging voltage to 5.5V when the battery percent is over 85 percent. TEST=Charge kukui with PD charger <= 85%, and see it switches to 5V when battery > 85%. BUG=b:78792296 BRANCH=None Change-Id: Ibdd496085f25b715ab2efb1b284f1aa5e3246653 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1411436 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
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