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* hatch_fp: update SPIIDstabilize-12061.BTom Hughes2019-04-161-1/+1
| | | | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: I8cf3255147cad0de4ee2461813c4ad6a1dff6f48 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1568894 Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* hatch_fp: STM32F412 can have up to 1 MB Flash (some have less)Tom Hughes2019-04-091-15/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | For sizes, see: See https://www.st.com/resource/en/reference_manual/dm00180369.pdf Section 3.3 Embedded Flash Memory We read the Flash size data register to get the actual size: See https://www.st.com/resource/en/reference_manual/dm00180369.pdf Section 31 Device electronic signature BRANCH=none BUG=b:126455006,b:124996507 TEST=make BOARD=hatch_fp -j ./build/host/util/stm32mon -b 115200 -d /dev/pts/24 \ -u -e -w ./build/hatch_fp/ec.bin Change-Id: I105840150cde68c7c7579d44c8d8c43b6b567233 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1541818 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit b438ce1a026503d37ab14c537b15f3ae49cc44a2) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1560338
* ish/ish5: enable AON low power mode on arcada_ish boardHu, Hebo2019-04-081-0/+12
| | | | | | | | | | | | | | | | | enabled D0i-3 low power mode and reset_prep and D3 features BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I6c3949a7ac229a3f33cd75bd103e343f8e9a26f9 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1536487 Commit-Ready: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish/ish5: packing aontask binary and ecos main FW binary to final ec.binHu, Hebo2019-04-082-15/+82
| | | | | | | | | | | | | | | | | | | | 1: fixed module size not round up with page issue 2: fixed wrong kernel binary file issue, ISH only support RW image at current 3: add aontask binary into ec.bin BUG=b:122364080, b:120682121 BRANCH=none TEST=tested on arcada Change-Id: I786169c32b0e2c50cbe6ad7bf476ae9c56ea1d09 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1545073 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish/ish5: implement reset, reset_prep and D3 flowHu, Hebo2019-04-088-78/+309
| | | | | | | | | | | | | | | | | 1: reset and reset_prep implemented 2: D3 flow implemented BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: Ie6bacd89e2363578d85157dfb1dd8b56e2828d05 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1536486 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish/ish5: implement AON low power mode (D0i1-3)Hu, Hebo2019-04-0810-24/+383
| | | | | | | | | | | | | | | | | 1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented 2: D0i3 (TCG + SRAM power off) implemented BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1531772 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish/ish5: implement AON low power management frameworkHu, Hebo2019-04-0816-0/+1208
| | | | | | | | | | | | | | | | | | | | | AON PM framework including: 1: AON task skeleton 2: task switching between main FW and AON task 3: 'idlestats' console command for D0ix statistic information 4: D0ix entrance in idle task BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: Iefa9e067892d5c42d9f0c795275fe88e5a36115b Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1510518 Commit-Ready: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* bc12: pi3usb9201: Save supplier to update charge managerstabilize-12060.Bstabilize-12058.Bstabilize-12054.BScott Collyer2019-04-051-6/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | When bc1.2 detection is completed, it will update the available charge for the supplier type which was detected. When bc1.2 is powered down (upon CC detach), the charge manager needs to be informed that the available charge for this supplier type is 0, This CL modifies the pi3usb9201 driver to store the most recent bc1.2 detection supplier type for each port. When the bc1.2 chip is powered down, then the charge manager can be properly updated. BUG=b:129435454 BRANCH=none TEST=Connected, then removed charger to both ports 0 and 1. The checked status via ectool: localhost ~ # ectool usbpdpower Port 0: Disconnected Port 1: Disconnected Change-Id: Ic6ae27bb498d2a82389803019f948bc11e3dec23 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1545076 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cr50: use board_wipe_tpm to clear the tpmMary Ruthven2019-04-056-52/+38
| | | | | | | | | | | | | | | | | | | | | | | | | We were clearing the tpm in two different ways. There was one implementation in factory_mode.c and one in wp.c. This change merges the two, so there's only one board_wipe_tpm. While modifying the wipe tpm code from factory_mode.c I noticed the factory_enable_failed stuff is maybe a bit more complicated than necessary. I opened a bug for cleaning that up(b/129956462). It wont be addressed in this change. BUG=none BRANCH=none TEST=Run the processes that wipe the tpm open ccd. enable factory mode from vendor command. run rma open process Change-Id: Ia76df19f7d9e4f308f3f1a7175f130f1ef7249a2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1535156 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* iteflash.md: Document procedure for reflashing ITE ECs.Matthew Blecker2019-04-051-0/+119
| | | | | | | | | | BRANCH=none BUG=b:79684405,b:124388894 TEST=Viewed the document through Gitiles, verified formatting. Change-Id: I95ffccca3d7b88f4ab478e85bc1af252813100ff Signed-off-by: Matthew Blecker <matthewb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1549982
* i2c-pseudo: Simplify install shell script.Matthew Blecker2019-04-051-18/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The script now unconditionally attempts to (re)install the module, even if it is already loaded. (This also removes a message which had a typo, mistakingly referring to i2c-dev instead of i2c-pseudo.) The script no longer attempts to load i2c-dev, since servod does that now. The script now runs "make clean" before "make" . The header comment no longer references a section of the README that was never checked in. BRANCH=none BUG=b:79684405 TEST=I ran the install script in various scenarios: 1) No i2c-pseudo module loaded or installed. 2) i2c-pseudo module loaded but not installed. 3) i2c-pseudo module installed but not loaded 4) i2c-pseudo module loaded and installed. In all cases the module was (re)installed and either left loaded (if applicable), or loaded (if not previously loaded). The script does not attempt to unload and re-load the module when re-installing only for simplicity. Change-Id: I5f2677b92406b8a49d229bc84d2efcca5504f501 Signed-off-by: Matthew Blecker <matthewb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1552245 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* cr50 signer: make sure SQA images can not be signed with prod keysVadim Bendebury2019-04-051-2/+2
| | | | | | | | | | | | | | | This patch makes sure that SQA images can not be signed with prod keys. BRANCH=none BUG=none TEST=manually verified that the modified grep expression triggers for both DBG and SQA containing strings. Change-Id: I3c8b8c45dbbf5d38bc9c35f766e80ada8257cb65 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1553575 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: complete support of the new NVMEM structureVadim Bendebury2019-04-0516-603/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch eliminates unnecessary legacy nvmem.c and nvmem_vars.c code and brings the code base to the state where the new NVMEM layout is fully functional. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 CQ-DEPEND=CL:1450278 TEST=the following tests pass: - test cases in ./test/nvmem.c - TCG suite (passes on par with the existing Cr50 code with the reduced code footprint TPM2 library) - Chrome OS device migrates from legacy to new implementation with user account maintained. - Chrome OS user account is maintained over AP and H1 reboots and deep sleep cycles. Change-Id: If4bc2dd125873a79dbe0e268eb32100a8b8b352d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496607 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* nvmem: test modifications to support the new schemeVadim Bendebury2019-04-0514-1154/+2936
| | | | | | | | | | | | | | | | | | | | | This patch includes changes to support testing of the new nvmem implementation. Making fizz compatible required duplicating a lot of functionality available in the test/ directory (fuzz/nvmem_tpm2_mock.c is very similar to test/nvmem_tpm2_mock.c), but I could not find an easy way to avoid it. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 CQ-DEPEND=CL:1496607 TEST=with the rest of the patches applied 'make buildall -j' succeeds, which confirms both test and fuzz success. Change-Id: Ife999b04d22f8ddbe9ea5d35f4c3e21f57592754 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1450278 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: Update to VENDOR_CC_GET_PWR_BTNKeith Short2019-04-051-1/+12
| | | | | | | | | | | | | | | | | | | | | | | Change the VENDOR_CC_GET_PWR_BTN behavior to report the live state of the power button. On Wilco devices, the AP needs to poll for both a power button press and release prior to booting an untrusted OS. The falling edge of the power button is still latched, so the first call to VENDOR_CC_GET_PWR_BTN command will return a button state of 1 if this call is made within 10 seconds. Once the latched state is clear, VENDOR_CC_GET_PWR_BTN returns the live state of the power button. BUG=b:128431787 BRANCH=cr50 TEST=Added test code into vboot recovery screen to poll VENDOR_CC_GET_PWR_BTN command for a power button press and a power button release. Change-Id: I8bc34e4e6309f6b3bd8020655370eb50032a00f1 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1534337 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Matt Delco <delco@google.com>
* cr50: convert functions into staticNamyoon Woo2019-04-056-18/+6
| | | | | | | | | | | BUG=b:112778363 BRANCH=cr50 TEST=ran test_that suite:faft_cr50_prepvt on coral. Change-Id: I1b3c573ee5fcb40290541f231c78bf31650c13c4 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1410482 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cbi: Allow cbi command included optionallyDaisuke Nojiri2019-04-052-0/+4
| | | | | | | | | | | | | | | | | | | | Currently, console command 'cbi' is always included when cbi is enabled. This patch adds CONFIG_CMD_CBI so that a board can choose to include or exclude the command. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/129746223,b/127720872 BRANCH=none TEST=buildall Change-Id: I465d9b52af91d54a686022bf19a1c4e698d2a727 Reviewed-on: https://chromium-review.googlesource.com/1552359 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org>
* ish: print heci error messages when occurJett Rink2019-04-052-13/+2
| | | | | | | | | | | | | | | | | | | | The error message for the HECI bus should print to the console if errors occur. Only the spammy debug message should be guarded by the debug compiler option. BRANCH=none BUG=none TEST=see prints on console This exposes that we are failing to send HECI (ISHTP) messages due to a flow control issue (no cred) Change-Id: I7ca8d47531df8a206165d4b3f14cb367d9d5d745 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1553299 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
* cr50: make is_sys_rst_asserted staticMary Ruthven2019-04-052-2/+1
| | | | | | | | | | | | | BUG=none BRANCH=cr50 TEST=make buildall -j Change-Id: Ic95e75cbfaa15103d83c78dcb9efd5b985f2f190 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1542799 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: make sys_rst_l_out pseudo open drainMary Ruthven2019-04-053-29/+14
| | | | | | | | | | | | | | | | | | | | | | | | | The existing SYS_RST_L implementation enables the output on SYS_RST_L before setting the level to 0, which results in cr50 briefly driving SYS_RST_L high when SYS_RST_L is asserted. This patch switches SYS_RST_L to a pseudo open drain mode, which eliminates the pulse. The internal pull up on SYS_RST_L is not being removed, so the H1 will still pull this line up when SYS_RST_L output is set to 1. Removing the pull up will require careful analysis of existing designs, and if safe will be done in a different patch. BUG=b:117676461 BRANCH=cr50 TEST=assert/deassert sys_rst_l and check that 'sysrst' shows the correct state. Verify this works on cheza which only pulls SYS_RST_L up to 1.8V even though VDDIOM is 3.3V. Change-Id: I50c9569e70c97cec434df3095f1b109f3248076b Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1282020 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* gpio: add config option for using gpio_get_flagsMary Ruthven2019-04-054-3/+10
| | | | | | | | | | | | | | | Separate gpio_get_flags from the CONFIG_CMD_GPIO_EXTENDED, so we can enable getting the gpio flags without enabling the ability to set them. BUG=none BRANCH=cr50 TEST=none Change-Id: Ib8e3a13fdcfe8ebec4523eb070b2425b5dc28278 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1542798 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kblight: Remove dependency on PWMDaisuke Nojiri2019-04-045-6/+19
| | | | | | | | | | | | | | | | | | | | | | Keyboard backlight can be controlled either by PWM or an external controller. This patch decouples keyboard backlight common code and PWM based backlight control. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=Nami TEST=Verify keyboard backlight can be adjusted on Ekko. Change-Id: I332b01a2a2b15bd37ce385b6c30591c90f078dfc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1549476 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit e879713cee3212b4afffb3f0dd3c4dfbf8237c4a) Reviewed-on: https://chromium-review.googlesource.com/1549606 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* rowan: Delete boardEvan Green2019-04-048-1424/+0
| | | | | | | | | | | | | | | | | Rowan is long dead. Remove the board. Signed-off-by: Evan Green <evgreen@chromium.org> BUG=chromium:840888 BRANCH=none TEST=make -j buildall CQ-DEPEND=CL:*1087044,CL:1538915 Change-Id: Ia18d95c8f283d4b2dc2aa29cb0b8b17b574f9bf8 Reviewed-on: https://chromium-review.googlesource.com/1540516 Commit-Ready: Evan Green <evgreen@chromium.org> Tested-by: Evan Green <evgreen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx7_evb: illustrate the flash configuration of npcx7m7wcCHLin2019-04-042-3/+5
| | | | | | | | | | | | | | | | | | | | | There are only 512 Kbytes of internal flash in Rev.C of npcx7m7w (i.e. npcx7m7wc.) It is different from the Rev.B of npcx7m7w (i.e. npcx7m7wb.) This CL illustrates how to set the flash type and flash size when chip variant is npcx7m7wc. BRANCH=none BUG=none TEST=pass "make buildall". TEST=with related CLs, switch to different chip variant in build.mk; build and flash the image; make sure each EC image can boot up on EVB or internal testing board of different chip variant. Change-Id: I2b50c7a023b1634ed4a200cb826532174baae117 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1543063 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* minute-ia: clean up comments about ISR=0 bugJack Rosenthal2019-04-042-10/+8
| | | | | | | | | | | | | | According to Intel, ISR=0 is actually the intended behavior, so these scary comments linking to buganizer can be cleaned up. BUG=b:28444630 BRANCH=none TEST=make buildall -j Change-Id: I877556f1719826cb72eee39e4d14e2c10412c7a9 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1550706 Reviewed-by: Raul E Rangel <rrangel@chromium.org>
* cr50: New NVMEM flash storage implementationVadim Bendebury2019-04-044-0/+3148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a proposed implementation of the new TPM NVMEM flash layer. There is a big comment block in common/new_nvmem.c describing the approach taken, changes to the API and outstanding issues. This implementation follows the design document attached to b:69907320. With all required changes to the rest of the code this new flash storage scheme consumes 7816(!) bytes of code storage. One of the more important aspects of this implementation is that the (key, value) pair objects are stored in the flash only, they are not duplicated in the SRAM cache. The advantage of this is that there could be more space dedicated to these objects. Soft limit is set to 1K as opposed to 272 bytes available with the legacy scheme. The major disadvantage is the need for the user not to forget to release the (key, value) pair retrieved from NVMEM, as it occupies space on the heap. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 TEST=with the rest of the patches applied the following tests pass: - test cases in ./test (completely reworked for the new scheme) - TCG suite (passes on par with the existing Cr50 code with the reduced code footprint TPM2 library) - Chrome OS device migrates from legacy to new implementation with user account maintained. - Chrome OS user account is maintained over AP and H1 reboots and deep sleep cycles. Change-Id: I6252649597c03abd4a08e2d55d61e384fe037ef7 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1450277 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: make ccd_mode_l pseudo open drainMary Ruthven2019-04-042-11/+6
| | | | | | | | | | | | | | | | | | gpio.c has support for making pins open drain. This implementation will prevent the signals from being driven high. Use the gpio.c support instead of the hack we were using before. BUG=none BRANCH=cr50 TEST=the EC can assert CCD_MODE_L when cr50 has it deasserted. Verify this on a ARM and x86 device in the lab. Change-Id: I7f2a465782f2c60a850c25153fb65eb96fff0712 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1282019 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add kukui strapMary Ruthven2019-04-041-0/+6
| | | | | | | | | | | BUG=b:126476180 BRANCH=cr50 TEST=kukui uses SPI and PLT_RST_L Change-Id: Ibeb28b1c40d07d56c0d9bb760026a01cd7a1a754 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1541693 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kohaku: Initial image copied from hatchScott Collyer2019-04-047-0/+888
| | | | | | | | | | | | | | | | This CL adds kohaku as a project and is a just a copy of the hatch reference with no kohaku specific changes. BUG=b:129714630 BRANCH=none TEST=make -j BOARD=kohaku Change-Id: Ibf3059cc9548c66fe8fe560d7d352e11adb2ebf8 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1551580 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Casta: Add MKBP events on EC_AP_INT_ODLDiana Z2019-04-042-3/+3
| | | | | | | | | | | | | | | Though casta isn't using sensors, the GPIO for the MKBP events is still populated so configure and enable it. BUG=None BRANCH=octopus TEST=builds Change-Id: Id5efe1dd79efaeb43a94b6fcd005d5ae7078a03c Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1545084 Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* kukui: scp: fix udelay hangs the system in clock enable.Pi-Hsun Shih2019-04-041-2/+15
| | | | | | | | | | | | | | | | | It seems that udelay doesn't work before the clock is properly configured and enabled, causing the SCP image not able to boot. Remove the udelay in scp_clock_high_enable. BUG=b:128877063 TEST=manually, make sure SCP firmware works on boot. BRANCH=none Change-Id: Idc505a33a7e88d136a5b50f2e5bd52bd5213393b Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1530410 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* bmm150: lower max frequency to match a frequency supported by BMI160Gwendal Grignou2019-04-041-2/+14
| | | | | | | | | | | | | | | | | | | | Be sure the frequency we report does not need to be rounded up by BMI160 when BMM150 is behind BMI160. For instance, if we set 29Hz as maximum frequency, 29Hz will be rounded up to 50Hz (BMI160 samples at its own recognized frequency). At that speed, the BMM150 will lock up. BUG=b:120942904 BRANCH=none TEST=On eve with magnetometer check the maximum frequency reported by the magnetometer is 25Hz. Check the magnetometer is working with 'ectool motionsense 3' Change-Id: I7025fe8a400e050907af490784521295d987051a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1535161 Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* bmi160: Fix ODR to REG when rate is less than 100HzGwendal Grignou2019-04-041-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The calculation was wrong and always returned the next value. We were lucky that we always ask to round up, so the frequencies were rounded up from the get go. BUG=b:120942904 BRANCH=none TEST=Test with several ODR for correctness: cout << "10:" << BMI160_ODR_TO_REG(10000) << ":" << BMI160_REG_TO_ODR(BMI160_ODR_TO_REG(10000)) << "\n" << "29:" << BMI160_ODR_TO_REG(29000) << ":" << BMI160_REG_TO_ODR(BMI160_ODR_TO_REG(29000)) << "\n" << "59:" << BMI160_ODR_TO_REG(59000) << ":" << BMI160_REG_TO_ODR(BMI160_ODR_TO_REG(59000)) << "\n" << "99:" << BMI160_ODR_TO_REG(99000) << ":" << BMI160_REG_TO_ODR(BMI160_ODR_TO_REG(99000)) << "\n" << "109:" << BMI160_ODR_TO_REG(109000) << ":" << BMI160_REG_TO_ODR(BMI160_ODR_TO_REG(109000)) << "\n" << "209:" << BMI160_ODR_TO_REG(209000) << ":" << BMI160_REG_TO_ODR(BMI160_ODR_TO_REG(209000)) << "\n" ; Returns: 10:4:6250 29:6:25000 59:7:50000 99:7:50000 109:8:100000 209:9:200000 Change-Id: I898d1077af78ab1d0e65ac0e8f7714a2a3b042b3 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1535160 Reviewed-by: Yilun Lin <yllin@chromium.org>
* Makefile.toolchain: strip leading whitespace in set-optionPatrick Georgi2019-04-031-1/+1
| | | | | | | | | | | | | | | | | That function is only used to set CROSS_COMPILE, and we never need leading whitespace in there. It sneaks in when the set-option call is split across several lines, breaking the analyzestack target. BUG=chromium:875295 BRANCH=none TEST=make BOARD=yorp analyzestack works Change-Id: I1b2dccd9753b0662067d77bd9c58d4ccf6daeb4d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1547563 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* factory_mode: change how reset_required is savedMary Ruthven2019-04-031-1/+1
| | | | | | | | | | | | | | | | Logically OR reset_required with the saved reset_required state when enabling factory mode, so there is no way to cancel a reset once it's requested. BUG=none BRANCH=cr50 TEST=enable factory mode. Change-Id: I7a432989b83946570a914f27e806ec2dbc9e9791 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1548273 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* flapjack: Enable hall_interrupt via lid_switchPhoenix Wu2019-04-033-8/+3
| | | | | | | | | | | | BUG=b:124344730 BRANCH=None TEST=Invoke hall interrupt by a magnet and see that EC console will output a lid close/open event Change-Id: I78290ba4240a494674f2f9e8c7deaa365969319f Reviewed-on: https://chromium-review.googlesource.com/1475104 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Phoenix Wu <wujing6@huaqin.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* arcada_ish: remove unlocked config optionJett Rink2019-04-031-6/+0
| | | | | | | | | | | | | | The Unlocked config option doesn't really even apply to arcada, remove as we get further along. BRANCH=none BUG=none TEST=Flashed on to arcada without issue. Change-Id: I1de4508a7fa7ee51f562a8806e6a1bbf13f40135 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1548504 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* hatch: Enable CONFIG_POWER_S0IX_FAILURE_DETECTIONEvan Green2019-04-031-0/+1
| | | | | | | | | | | | | | | | | | Enable the shiny new S0ix failure detection code that will wake the AP after a specified timeout if the system attempted to go into S0ix but went into a shallower state instead. BUG=b:123716513 BRANCH=None TEST=Test S0ix with a modified EC firmware and kernel changes. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ia981cdc34a98bcf877dec78067173bf1c0f9e700 Reviewed-on: https://chromium-review.googlesource.com/1509717 Commit-Ready: Evan Green <evgreen@chromium.org> Tested-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cr50: add command to override BATT_PRES_LMary Ruthven2019-04-034-14/+107
| | | | | | | | | | | | | | | | | | | | | | | | We use BATT_PRES_L to determine if factory mode can be enabled. We need to be able to control this for cr50 testing. Add a command that can be used to override battery presence. This change also adds a ccd capability to control access to this command. If this capability is enabled, someone can easily use console commands and AP commands to enable factory mode, so it should be controlled separately from WP and GscFullConsole. BUG=b:126197850 BRANCH=cr50 TEST=override battery presence using bpforce. Make sure the state lasts through reboot, deep sleep, and power-on reset. When bp is forced disabled you can do ccd open without physical presence and you can enable factory mode. Change-Id: I026a537142b6780824192caa2a147c7bdac1545c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1505213 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* hatch_fp: Fix flash erase in stm32monTom Hughes2019-04-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hatch_fp uses STM32F412, which *does* support mass erase. The original commit that matches against STM32F41 seems to be targeted to the STM32F411 based on the commit message: 09a7fa4ae When trying to erase the STM32F412 for hatch_fp by page, the command fails: Waiting for the monitor startup ...Done. ChipID 0x441 : STM32F412 Bootloader v1.1, commands : 00 01 02 11 21 31 44 63 73 82 92 Unprotecting flash read... Flash read unprotected. Waiting for the monitor startup ...Done. Flash write unprotected. Waiting for the monitor startup ...Timeout Done. Erasing... NACK payload 0 ACK failed for CMD44 BRANCH=None BUG=b:124996507 TEST=hatch_dut> flash_fp_mcu ec.bin Change-Id: Idc800b1f3ae29f7776405b1e952f71ef2d7c8a14 Signed-off-by: Nicolas Norvez <norvez@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1539016 Commit-Ready: Tom Hughes <tomhughes@chromium.org> Tested-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* npcx7: introduce npcx7m7wc chip and refine memory layout of npcx7m7wbCHLin2019-04-035-16/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL includes the following changes: 1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to define what (RAM, features...) is supported in npcx7m7wc. 2. add the chip id and chip revision id of npcx7m7wc. 3. re-organize the memory of npcx7m7wb from: current: 320 KB code RAM + 64 KB data RAM. to : 256 KB code RAM + 128 KB data RAM. The reason is that the extra 64 KB RAM is excepted to store the WoV voice data when it operates under RAM mode. Under the limitation of current memory layout, the 64 KB voice buffer is declared as const to force it allocated in the code section, which is strange. This can be fixed after changing the layout. BRANCH=none BUG=none TEST=pass "make buildall" TEST=with related CLs, change CHIP_VARIANT to npcx7m7wc in board/npcx7_evb/build.mk; flash image in the internal testing board of npcx7m7wc; make sure the EC can boot up; check the chip ID and chip revision ID are correct by console command "version". TEST=build npcx7m7wb image and test it on npcx7_evb, no symptom found. Change-Id: I7533c1f5490e151571696ac615da2d0430827a78 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1543062 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* util:ecst: add the support of CHIP_VARIANT npcx7m7wc for NPCX7CHLin2019-04-031-3/+5
| | | | | | | | | | | | | | | | | | This CL adds the support for chip variant npcx7m7wc in the ecst utility. BRANCH:none BUG=none TEST=pass "make buildall" TEST=in the follow CL, change CHIP_VARIANT to npcx7m7wc in board/npcx7_evb/build.mk; build the image by "BOARD=npcx7_evb make"; check the image can be built and the image header is correct. Change-Id: I6031a6f188f06e31ca7ce0571065b11ee68b27ab Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1543061 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* arcada_ish: ensure tests target buildsJett Rink2019-04-033-0/+13
| | | | | | | | | | | | | | | | Fix the test target for ish which is run during the test phase of chromeos-ish which is not run under buildall in EC codebase. BRANCH=none BUG=b:12237171 TEST=make BOARD=arcada_ish tests builds successfully. FEATURES=test emerge-sarien chromeos-ish now works Change-Id: I6eeaa7a15a5a026b189b67d54f28d994e6a56bb7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1548503 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* hatch_fp: add flash_fp_mcu scriptNicolas Norvez2019-04-031-0/+35
| | | | | | | | | | | | | | | | Set the correct GPIOs, SPI dev and ID for Hatch. Keep the GPIO_PWREN variable empty since there is not such GPIO on Hatch, power is always on for the FPMCU BRANCH=None BUG=b:124405913 BUG=b:126455006 TEST=flash_fp_mcu on hatch doesn't bail Change-Id: I544868bc088d3aeb0896b8123bfc83c1ea0a156c Signed-off-by: Nicolas Norvez <norvez@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1532345 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* hatch_fp: initial uploadNicolas Norvez2019-04-036-0/+376
| | | | | | | | | | | | | | | | First draft, lots of features still missing. Dev key generated with this command: openssl genrsa -3 -out board/hatch_fp/dev_key.pem 3072 BRANCH=none BUG=b:124996507 TEST=make BOARD=hatch_fp Change-Id: I7d7f0ce6807f7db9ee67e2e9b72ba6b2a0b87591 Signed-off-by: Nicolas Norvez <norvez@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1482059 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* stm32f412: add TRNG supportNicolas Norvez2019-04-032-0/+8
| | | | | | | | | | | | | | No need to set up the TRNG's clock, on STM32F4 it always uses the PLL's output that is set on boot. BRANCH=None BUG=b:124770147 TEST=hatch_fp builds. STM32F412's TRNG is not used on other projects. Change-Id: Ie1f268137ee9a3a76cd0350e3ea5b2e85def1b76 Signed-off-by: Nicolas Norvez <norvez@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1481653 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32: spi: fix unused variable errorNicolas Norvez2019-04-031-2/+2
| | | | | | | | | | | | | Don't error out when building for STM32F412. BRANCH=none BUG=none TEST=hatch_fp firmware builds successfully Change-Id: I996a39a6319b7ad5bbfae7e0c7b7746e3f3a243d Signed-off-by: Nicolas Norvez <norvez@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1482058 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core/minute-ia: add IA32/x86 arch related data structure definitionsHu, Hebo2019-04-024-68/+204
| | | | | | | | | | | | | | | | | includes GDT, LDT, IDT, and TSS tables data structures definitions BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I2e9fea21501a16485fbc4e05163c1f2ffbbc17f4 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1531275 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* flash_ec: sort STM32 boards alphabeticallyNicolas Norvez2019-04-021-1/+1
| | | | | | | | | | | | | | hatch_fp had been added in the wrong place, fix the ordering. No functional changes. BRANCH=None BUG=b:124996507 TEST=None Change-Id: I7e1602d80db9366bf0e97f03abe1f0f7af2aa670 Signed-off-by: Nicolas Norvez <norvez@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1547141 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* ish: add memory dma driver for ISH5Leifu Zhao2019-04-026-0/+379
| | | | | | | | | | | | | | | | | | | Arcada/ISH5 power management needs the support for dma between UMA and SRAM to do SRAM swap in and swap out. Add the dma driver and API which utilizes dma engine to perform dma transfer between UMA and SRAM. BUG=b:127723182 BRANCH=none TEST=tested on arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I22172b176eed92d7f487641f9b5c79dfd04f602a Reviewed-on: https://chromium-review.googlesource.com/1507326 Commit-Ready: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
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