| Commit message (Collapse) | Author | Age | Files | Lines |
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They take up flash space, and should not be super useful.
BRANCH=none
BUG=chromium:988303
TEST=make buildall before and after
Save 64-100 bytes on most boards
Change-Id: I8eafb19b971f0823c0b0b704e680e063aa23dbd8
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1723610
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit d31dd57e48b58171d86666007a712a1af5dd3f8c)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1731140
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No need to use up flash space if the command is not supported
anyway.
BRANCH=none
BUG=chromium:988303
TEST=make buildall -j
TEST=make BOARD=jerry -j32, see that there is still 156 bytes free
Save 64-128 bytes on most boards.
Change-Id: Ib0494969840dfc4c11d236a2932f5de688ad6d14
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1723611
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 7c34f1301021a998d41b7970201c79cfe846d199)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730968
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During suspend, pmic wrap will be waken up by scp which is due to hw design.
However, the clock of pmic wrap is 26mhz which would be turned off in the
suspend mode, so we needs to change the clock of pmic wrap from 26mhz to
ULPOSC.
BRANCH=none
BUG=b:135985700
TEST=make BOARD=kukui_scp -j && \
bash board/kukui_scp/update_scp $IP
alias rtcalm='echo "+15" > \
/sys/class/rtc/rtc0/wakealarm'
rtcalm
cat /proc/driver/rtc
powerd_dbus_suspend
TEST=Can resume in suspend.
Change-Id: I07b9d76f574fe1007e20f185bb278e0884397176
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686990
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Yilun Lin <yllin@chromium.org>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
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This command stress tests the channel between the user-side
ec command interface and the target MCU.
This can be used to expose rare communication errors, such as
exceeding communication timeouts.
BRANCH=none
BUG=b:131724307,b:116065496
TEST=make buildall -j
TEST=cros_workon --board=nocturne start chromeos-base/ec-utils
emerge-nocturne chromeos-base/ec-utils
cros deploy dut1 chromeos-base/ec-utils
# On dut1
ectool stress
ectool --name=cros_fp stress
ectool --name=cros_fp stress reboot
Change-Id: I485e915d0bc027ccee8d2d78b90fe0d066a3ff4d
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686712
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The Linux kernel now has an official .clang-format file
available. Import this file to EC codebase.
Changes made:
- Uncommented options that were disabled since kernel targets
clang-format 4.0, but we have 9.0 in the chroot
- Removed kernel-specific foreach macros
BUG=none
BRANCH=none
TEST=clang-formatted some files, made sure they looked Linux-kernel
like
Change-Id: I8255fad43f965186852f82120ed07ca5f7fff643
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1718830
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
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This commit adds a new host command, EC_CMD_MKBP_WAKE_MASK which allows
the host to retrieve and set the MKBP host event wake mask along with
the MKBP event wake mask. An accompanying console command,
`mkbpwakemask` is present as well to view and adjust the wake masks. In
order to use this host command, one of the following EC CONFIG_* options
must be enabled in the EC: CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK or
CONFIG_MKBP_EVENT_WAKEUP_MASK.
BUG=chromium:786721
BRANCH=None
TEST=Deploy new version of ectool and EC firmware on nocturne, verify
that ectool can view and adjust the wake masks. Verify that masks can
be adjusted via the console command as well.
Change-Id: I01a389ccd571328220eadd19ded4167dea8c6faa
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700004
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
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None of the existing i2c addresses in the EC code base are less than 0x08
and those addresses are reserved by the i2c and SMBus specification.
BRANCH=none
BUG=b:138156666
TEST=i2c bus scan with a smart battery doesn't "misbehave" any more and
other devices can be detected properly.
Change-Id: I561b082c4c7e3df7caaa33b6ef6ad467dabbd5a5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715326
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Support 3 Byte Chip ID.
Support 3 Byte DBGR Address.
Change the flash size determination method.
BUG=none
BRANCH=none
TEST=Check it ok on both it8320 and it8xxx2 series.
There are several new chip from ITE.
The Chip ID : 81201 81202 83201 83202
We temporarily defined it as it8xxx1 and it8xxx2 series.
The new chip id is from 2 bytes to 3 bytes.
We verify it ok from Servo V2 + ITE evboard.
(cr) (asus-serve-v4) donald@donald-Aspire-4752 ~/trunk/src/platform/ec $
sudo ~/trunk/src/platform/ec/util/flash_ec --board=it83xx_evb
INFO: Using servo_v2.
INFO: Using ec image :
/mnt/host/source/src/platform/ec/build/it83xx_evb/ec.bin
INFO: Flashing chip it83xx.
INFO: Closing servod connection to ftdi_i2c interface
INFO: Programming EC firmware image using iteflash...
CHIPID 81201, CHIPVER 40, Flash size 256 kB
Done with sending special waveform.
Disabling watchdog...
Disabling protect path...
Erasing flash...erase size=262144
\100%
Erasing Done.
Writing 262144 bytes at 0x00000000.......
\100%
Writing Done.
Verify 262144 bytes at 0x00000000
\ 99%
Verify Done.
INFO: Flashing done.
INFO: Reinitializing ftdi_i2c interface
Change-Id: If17f85cb5d67d262a85d5cdeb89044646c39a0e1
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1655213
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Donald Huang <cguwinds@gmail.com>
Tested-by: Donald Huang <cguwinds@gmail.com>
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Add treeya board. Initially base on aleena.
BUG=b:135551210
BRANCH=none
TEST=emerge-grunt chromeos-ec
Ensure that ec.bin are created
Change-Id: I16abc65af81d5127c0f964a42327e60a8674be22
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1710209
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Tested-by: Edward Hill <ecgh@chromium.org>
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For TCS3400, performing calibration is not just a one-shot event:
The RBG sensor stays in calibration mode: returns raw value in R, G, B
space.
When out of calibration, it returns light information in X, Y and Z
space.
BUG=b:124512628
BRANCH=hatch,flapjack
TEST=unit test
Change-Id: I6766907054c8e79a3cbcb629ef91a0967ea0780a
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1702543
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Support Kindred LED Behavior as below
Charge: Amber on (S0/S3/S5)
Full: Blue on (S0/S3/S5)
Discharge in s0: Blue on
Discharge in s3: Amber on 1 sec off 3 sec
Discharge in s5: off
Erro: Amber on 1 sec off 1 sec
Factory mode: Blue on 2 sec Amber on 2 sec
BUG=b:135720559
BRANCH=master
TEST=none
Change-Id: I2ff503e0f4b874e2a3785d0c0cf6f0fd5c7f1e3c
Signed-off-by: ben.chen2@quanta.corp-partner.google.com
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1695564
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: David Huang <David.Huang@quantatw.com>
Commit-Queue: Philip Chen <philipchen@chromium.org>
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Add new before/after test functions to be used for clean-up and
tear-down of tests.
Add new asserting functions:
- TEST_EQ ensures that two values are equal
- TEST_NE ensures that two values are not equal
- TEST_BITS_SET ensures that a value contains all bits in mask
- TEST_BITS_CLEARED ensures that a value doesn't contain any
bits in mask
The benefit of these is that unlike TEST_ASSERT they will
also print the values when the assersion is wrong.
BRANCH=None
BUG=b:137758297
TEST=None yet
Change-Id: I2f305ef34e541c289f22c6596f53ee5cd977c7a8
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704165
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Add some print statements to closed loop reset, so it's easier to tell
what cr50 is doing.
BUG=none
BRANCH=cr50
TEST=none
Change-Id: I2b6b28d8eabcd8950fe7105b4382d8b8ed94afa6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1716927
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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In the board_hibernate function, shut down the AP, and wait 300ms
for the chipset state machine to settle down. This allows the EC
to actually hibernate; otherwise, it would simply reboot the device.
BUG=b:135073910
BRANCH=none
TEST=Verify that EC goes into hibernate with Alt+Volume Up+H, then
boots back up from time 0 on PB press. Verified that EC will wake
from hibernate on insertion of AC.
Change-Id: Ie98333e9ce65778df8d07ce6ae165b5c7140edf1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715907
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Nuvoton TCPC NCT38XX series chips have some pins which can be used as
GPIO function. we can treat it as the IO expander chip also.
This commit adds the driver to support it.
BRANCH=none
BUG=none
TEST=No error for "make buildall"
TEST=Apply this and related CLs, manually test each API, make sure each
function works correctly with NCT3807 and NCT3808 at the same time.
Change-Id: I2254c2e867445e55d1c261172e4b7175d22f28ef
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1657859
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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BUG=b:135986521,b:136786005
BRANCH=octopus
TEST=Test on charging/discharging/battery cut off pass.
Change-Id: Idda1c4bc027b44980e047dc89ccae3c26e23cfbe
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1710208
Reviewed-by: Marco Chen <marcochen@chromium.org>
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The unimplemented fields in tcpm_drv may cause ec jumping into some
undefined address. Prevent this happen by checking flags at compile
time.
BUG=None
TEST=make buildall -j
BRANCH=master
Change-Id: I68f47cdc34046e7551f00f72267850b4f0464200
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1710211
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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Implement the common code to provide a friendly interface to control the
IOs of IO expander. It adopts a similar concept to GPIO.
1. Define the IO expander IO in gpio.inc by the format:
IOEX(name, EXPIN(ioex, port, offset), flags)
- name: the name of this IO pin
- EXPIN(ioex, port, offset)
- ioex: the IO expander port (defined in board.c) this IO
pin belongs to.
- port: the port number in the IO expander chip.
- offset: the bit offset in the port above.
- flags: the same as the flags of GPIO.
2. The following APIs are supported:
1. ioex_get_flags_by_mask
2. ioex_set_flags_by_mask
3. ioex_get_flags
4. ioex_set_flags
5. ioex_get_level
6. ioex_set_level
7. ioex_init
3. The following console commands are supported:
1. ioexget [IO_EXPANDER_PIN_NAME]
2. ioexset IO_EXPANDER_PIN_NAME 0/1
BRANCH=none
BUG=none
TEST=No error for "make buildall"
TEST=Apply this and related CLs, manually test each API, make sure each
function works correctly with IO expander chip (NCT3807/NCT3808.)
Change-Id: I79c9813abccc67d5554e2ceb5c119dcf549b7dce
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1657858
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
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These boards are the new FPMCU names that make it easier to separate out
the FPMCU from the underlying platform that the FPMCU is connected to.
We need to keep the old names around for legacy build and signing
purposes, so we just use symlinks.
BRANCH=none
BUG=b:136678758,b:137108509
TEST=make BOARD=bloonchipper -j
make BOARD=dartmonkey -j
make buildall -j
Change-Id: I792c182962f9699ac16f6cc29f4da10716808915
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715638
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This patch fixes how the console messages in isl923x.c are printed.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I81cd1fc9f0a20a4908013b7b3051fc23953eefc2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1670699
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
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The ACProchot register takes a value in multiple of 128 up to 6400
mA. This patch makes isl923x_set_ac_prochot return error when a
value exceeding the max is passed.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b/130387567
BRANCH=Nami
TEST=buildall
Change-Id: I1854f091d6ee7eb042fefeff35094abeca452c2f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1669796
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
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For fingerprint firmware we are moving towards a model where the "board"
(in EC terminology) is a specific MCU+FP_SENSOR combination and not tied
to the main system board that it's connected to (e.g., "hatch",
"nocturne", etc.). This change decouples flash_fp_mcu from the EC
"board".
BRANCH=none
BUG=b:136678758,b:137108509
TEST=make buildall -j
hatch:
flash_fp_mcu /opt/google/biod/fw/hatch_fp_v2.0.1359-6f54be08d.bin
nocturne:
flash_fp_mcu /opt/google/biod/fw/nocturne_fp_v2.0.1765+87bb17a39.bin
nami:
flash_fp_mcu /opt/google/biod/fw/nami_fp_v2.2.144-7a08e07eb.bin
Cq-Depend:chromium:1705055
Change-Id: Idfe298f59ab9df8657a570cc47e956b4e94ee1a1
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1704808
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
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BRANCH=none
BUG=b:125419658
TEST=Remove "-U" flag in STM32MON_READ_FLAGS in flash_fp_mcu_common.sh
flash_fp_mcu -r foo.bin => success
hexdump foo.bin => valid data
ectool --name=cros_fp flashprotect enable
ectool --name=cros_fp reboot_ec
flash_fp_mcu -r foo.bin => fails
Add "-U" flag back to STM32MON_READ_FLAGS in flash_fp_mcu_common.sh
flash_fp_mcu -r foo.bin => success
hexdump foo.bin => all 0xFF
Change-Id: Ic3ec18262e653b72baf239caa8db12186a63613c
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692220
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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report_no_payload_failure() function gets an input 'failure type',
but it always marks failure type as 'inconsistent flash content'
instead of that input.
BUG=None
BRANCH=cr50, cr50-mp
TEST=none
Change-Id: I5bac69478416eeabf735faf5333f5f7eaa98b54e
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715910
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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EC code changed over to a 7-bit slave address and stored in a uint16_t
to generically be able to handle 10-bit addresses, if they are ever
needed, as well as common bit flags in the most significant bits.
This code does not use more than the 8 least significant bits but to
be EC consistent, I am making this 16 bits.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Ic5f4b3500ae7b3c18380b188efbc37c01d58d7e9
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1714136
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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In case sighing failure happens, let's not delete temporary files and
let's report the full failed signer invocation command line so that it
is easy to debug the problem.
BRANCH=none
BUG=none
TEST=debugged failure to sign the MP image which happened after
transitioning into a new sighing environment.
Change-Id: I55accb6887ad00103c9aa7b69aa373f886bce64e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715325
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This is needed to support CCD testing of UART to USB bridging.
BRANCH=none
BUG=b:38448364
TEST=ran 'make BOARD=hatch -j', verified that command is included in
the symbol map.
Change-Id: I11a9dcf7c3204a4464eb5305d0b6b38f51205575
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688135
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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The Hatch platform uses dedicated interrupt lines for the SN5S330
PPC. This patch helps to ensure that all PPC interrupts are processed,
even when interrupts happen during processing.
BUG=b:137783988
BRANCH=none
TEST=Verified that charging/discharging are still processed as expected.
Change-Id: I5c3b003f60aaa239d3ee7a477006913ce8f83ac5
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1714137
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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In the original firmware (in the uart_buffering.c), it clears the
SLEEP_MASK_UART immediately after it pushes all characters from its Tx
buffer to UART's FIFO without checking the status of transmission. It
may break the transmission because EC goes to deep sleep before UART TX
(FIFO or shift register) becomes empty. This CL fixes it by:
(1) Don't clear SLEEP_MASK_UART immediately when uart_tx_stop is called.
(2) Enable the NXMIP (No Transmit in Progress) interrupt.
(3) Clear SLEEP_MASK_UART in the UART interrupt handler when NXMIP is
set.
This fix only needs to apply to NPCX7 chips which have UART FIFO support.
BRANCH=none
BUG=b:137143640
TEST=No error for "make buildall"
TEST=run 10 iterations of uart_stress_tester on yorp with command:
./util/uart_stress_tester.py /dev/ttyUSB2 -t 360;
make sure no character lost in each iteration as below:
...
INFO | UartSerial| /dev/ttyUSB2 | Detected as EC UART
INFO | UartSerial| EC | Ready to test
INFO | ChargenTest | Ports are ready to test
INFO | ChargenTest | Test starts
INFO | UartSerial| EC | Test thread starts
INFO | UartSerial| EC | Test thread is done
INFO | UartSerial| EC | 0 char lost / 4147200 (0.0 %)
INFO | ChargenTest | PASS: lost 0 character(s) from the test
INFO | ChargenTest | Test is done
Change-Id: I97b1f572e8b9ebdb5102aa3e98ae2963d768b5b3
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703944
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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This should apply to all Kranes.
BUG=b:131081336
TEST=factory accelometer test
BRANCH=master
Change-Id: I44313d73bf6dd484101973e153c6b5209128a789
Signed-off-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1687832
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Confirmed by HW eng, this fix should apply to all board revisions.
BUG=b:133655155
TEST=none
BRANCH=master
Change-Id: I20a72ec744c6d6fbf08d0cf57ad78902e35c2df9
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1679784
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Yilun Lin <yllin@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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Support an argument pol0/pol1 to the console command to change the CC
polarity. When CC polarity change, apply the Rd/Rp to the proper CC line
and fake the proper CC voltage.
BRANCH=servo
BUG=b:136014621
TEST=Tried the console commands:
* Typed "cc src pol0" on servo v4 and checked DUT detected CC1:
Port C0 CC1, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x4946
* Typed "cc src pol1" on servo v4 and checked DUT detected CC2:
Port C0 CC2, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x4946
* Typed "cc snk pol0" on servo v4 and checked DUT detected CC1:
Port C0 CC1, Ena - Role: SRC-DFP-VC State: SRC_DISCOVERY, Flags: 0x1608
* Typed "cc snk pol1" on servo v4 and checked DUT detected CC2:
Port C0 CC2, Ena - Role: SRC-DFP-VC State: SRC_DISCOVERY, Flags: 0x1608
* Typed "cc srcdts pol0" on servo v4 and checked DUT detected CC1:
Port C0 CC1, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x14946
* Typed "cc srcdts pol1" on servo v4 but resulted some hard reset issue
during PD negotiation; need further investigation.
Port C0 CC2, Ena - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x10608
TEST=Ran the entire PD FAFT suite passed on both CC polarities.
Change-Id: I7f983179b13e87a219bd26fe3665446df36de86e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693843
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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firmware_PDVbusRequest forces servo v4 to different max_voltage
limits to verify the PD negotiation. Add the firmware support for it.
The console command usbc_action is the same as Plankton. So the test
side doesn't need any change.
BRANCH=servo
BUG=b:134700685
TEST=Tried usbc_action command and ran firmware_PDVbusRequest passed.
Change-Id: I5f05d73d9a2f92fe26514285e7c251e9fa27aba8
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686221
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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BRANCH=none
BUG=none
TEST=verified markdown rendering
Change-Id: Ibef37a8f9818d2cb9e2bd50097819d2c6a646398
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1713737
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The following bug
https://buganizer.corp.google.com/issues/136002955
indicates after my initial move of snowball to use the
linker map instead of hard defined addresses that
0xFF801E80 was reading back as all zeroes.
The change that was made for this is
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593
I double checked the map files and everything looked
good. For some reason using the linker to map the location
of this structure, the system does not run properly.
If I remove the link map placement of this structure
then the issue goes away. I looked at how aon_share
was placed at the specific address in AON memory and
this CL is doing the same thing and it is working.
I think this is the way we should keep this fix and not
try to get the linker map to place this structure where
we want it.
BUG=b:136002955
BRANCH=none
TEST=make buildall -j
TEST=verify soft reboot does not indicate power reset
Change-Id: Ibb6dbd3a4414b5c546e99f5ad7e0409250de6256
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1707998
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Support hooking on AC_CHANGE when external power plugged and unplugged.
BUG=b:137903027
TEST=on kukui, shutdown -h now, and plug power adapter on kukui, and see
battery LED turning on immediately, and also see console prints
"AC on"
BRANCH=master
Change-Id: I6e2704cfe2d3ed09cc6e1c76b8d03a5030a400ed
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1712400
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
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The extentions were added to make the compiler perform most
of the verification that the conversion was being done correctly
to remove 8bit addressing as the standard I2C/SPI address type.
Now that the compiler has verified the code, the extra
extentions are being removed
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
TEST=verify sensor functionality on arcada_ish
Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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* Update **test** directory description to README.md.
* Add ** fuzz** directory description to README.md.
* Add unit test and fuzzer make targets to `make help`
* Change showboards to print-boards to be more consistent
* Change showboards to use auto pretty print
* Add print-tests, print-host-tests, and print-host-fuzzers
This is necessary to remove the ambiguity about what a special
name is for a given unit test.
Documentation Story:
The idea is to give a brief overview of what the test and fuzz
directories are in README.md.
README.md also mentions you should see `make help` for more detail.
Running `make help` shows you more general test/fuzz commands,
including the print-* commands.
Running the print-* commands show you exact target names for all
possible unit/fuzz test (both the build-only and run target names).
BRANCH=none
BUG=none
TEST=make help
TEST=make print-tests
TEST=make print-host-tests
TEST=make print-host-fuzzers
TEST=make print-host-fuzzers | cat
TEST=make print-boards
TEST=make print-boards | cat
TEST=make buildall -j
Change-Id: I34b68196ac635ba71a1d45ceb5d35a3b36fd129f
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684714
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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For the normal lab use, emulating a sink has no PD comm, like a passive
hub. For the PD FAFT use, we need to validate some PD behavior, should
support sink roles with PD comm enabled. Two new roles "pdsnk" and
"pdsnkdts" are introduced.
BRANCH=servo
BUG=b:134700685
TEST=Typed "cc pdsnk" or "cc pdsnkdts" can transit the DUT port to
the PD state "SNK_READY", instead "SNK_DISCOVERY".
Change-Id: If6a7c39cd296986b8b28de1c1fbe66ee8438c709
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682920
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Support a new flag to enable DRP. The do_cc() function becomes having 4
arguments. So change to merge them into a single cc_config with
different bit masks.
For the force_source or force_sink role, we explicitly set the the Rp
or Rd resistors on CC lines. But for DRP role, the Rp/Rd toggling is
controlled by the PD state machine. So don't set any CC pull resistor
for DRP.
Support an "on" option in "cc" command to restore the previous role
before emulating detach.
Add "usbc_action drp" to toggle the DRP state, which is compatible with
Plankton.
BRANCH=servo
BUG=b:135691171
TEST=Ran the firmware_PDTrySrc test passed, and not break all the
existing PD FAFT tests.
Change-Id: I3b90611c9840f502e496c42f80354e7ee002f96e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682919
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Update the PD policy and comments:
* Only allow data role swap on DUT port;
* Remove the dts mode condition to initiate a data role swap
(not necessary to limit it to dts mode).
BRANCH=servo
BUG=b:135691171
TEST=Checked the CHG port is always UFP.
TEST=Checked the DUT port is SRC/UFP, a data role swap happened (but
it was initiated by DUT).
Change-Id: I668703209301a9542e94768f31f6ce8e2d9eb0f4
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682918
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The pd_config_init() does two things:
* pd_tx_init() to init the GPIO MODULE_USB_PD;
* pd_set_host_mode() to set CC pull resistors.
The pd_config_init() is called on PD phy init hook.
For setting CC pull resistors, calling pd_set_host_mode() is enough.
Don't need to reinit GPIO MODULE_USB_PD.
BRANCH=servo
BUG=b:135691171
TEST=Set "cc" role to "src", "snk", "srcdts", "snkdts", and "off".
TEST=Unplugged and replugged the CHG port cable.
Change-Id: I1e783dfa5da4f8e8f1d9d591818eb1128b7a8caa
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682917
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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When the requester does not expect the chip information from the live
target, return the hardcoded vendor and product id.
BUG=b:128820536,b:119046668
BRANCH=None
TEST=Boot to ChromeOS
Change-Id: I74affb00951411a3483258a8db165038e7eb683f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617894
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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Semantics of renew field in EC_CMD_USB_PD_CHIP_INFO is changing as
follows:
0 -> Return hard-coded info for Vendor ID/Product ID and cached info for
the Firmware Version
1 -> Return the live chip info for Vendor ID/Product ID/Firmware Version
Also rename the 'renew' field to 'live' to match the new semantics.
BUG=b:128820536,b:119046668
BRANCH=None
TEST=make -j buildall; Boot to ChromeOS.
Change-Id: Ie3dd022336b0be5c9728bb0ebabef32b7a6b5d57
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617893
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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The octopus baseboard should only declare the sensor CONFIG_ values
if we didn't define the NO_SENSORS variant
BUG=b:137758297
BRANCH=None
TEST=buildall
Change-Id: I32443f08ee7d1412b425bd55c8c40d67f22ef089
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706687
Reviewed-by: Enrico Granata <egranata@chromium.org>
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Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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In servo v4 hardware logic, both CC lines are wired directly
to DUT. When servo v4 as a snk, DUT may source Vconn to CC2
and make the voltage high as vRd-3.0, which makes the PD
state mess up. As the PD state machine doesn't handle this
case. It assumes that CC2 is separated by a Type-C cable,
resulting a voltage lower than the max of vRa.
It fakes the voltage within vRa so the PD state machine
checks the value as expected.
This is an issue only happening on servo v4 as it wires both
CC lines to DUT.
BUG=b:134700685
BRANCH=servo
TEST=Servo v4 as snk, verified the CC2 is sensed vRa, i.e.
the output "CC1:0" (TYPEC_CC_VOLT_OPEN), instead of "CC1:7"
(TYPEC_CC_VOLT_SNK_3_0).
2019-06-18 15:05:47 > cc snk
2019-06-18 15:05:50 cc: on
2019-06-18 15:05:50 dts mode: off
2019-06-18 15:05:50 chg mode: off
2019-06-18 15:05:50 chg allowed: off
2019-06-18 15:05:50 > C1 st2 SNK_DISCONNECTED
2019-06-18 15:05:50 C1 st3 SNK_DISCONNECTED_DEBOUNCE
2019-06-18 15:05:50 C1 st5 SNK_DISCOVERY
2019-06-18 15:05:51 > tcpc 1 state
2019-06-18 15:05:53 Port C1, Dis - CC:2, CC0:6, CC1:0
2019-06-18 15:05:53 Alert: 0x00 Mask: 0x007d
2019-06-18 15:05:53 Power Status: 0x48 Mask: 0x00
TEST=Ran the PD FAFT test firmware_PDConnect passed.
Change-Id: I10f1ffe80768100ee3ed4c374598df7c2f9a8d05
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1666468
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This patch let the tester exit with an error code on test failure.
It would make easy the future autotest to detect a failure.
BUG=None
BRANCH=None
TEST=ran on fleex.
$ uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 -t 120 -d
[before patch]
...
INFO | UartSerial| EC | 14888 char lost / 1382400 (1.1 %)
INFO | UartSerial| AP | 0 char lost / 1382400 (0.0 %)
ERROR | ChargenTest | FAIL: lost 14888 character(s) from the test
...
$ echo $?
0
[after patch]
...
INFO | UartSerial| EC | 14888 char lost / 1382400 (1.1 %)
INFO | UartSerial| AP | 0 char lost / 1382400 (0.0 %)
ERROR | ChargenTest | FAIL: lost 14888 character(s) from the test
Error: Test failed for losing 144888 character(s)
...
$ echo $?
1
$ ./util/uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 -t 120 -d
Error: /dev/ttyUSB1 does not exist.
$ echo $?
1
Change-Id: I210efd4ad7fdb8eb612206624eda6c39c5bb3b1c
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1696115
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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During initialization, uart_stress_tester checks each of ports
exists, and raises an error if not.
BUG=None
BRANCH=None
TEST=ran on fleex.
$ uart_stress_tester.py /dev/ttyUSBX -t 120
Error: [Errno 2] No such file or directory: '/dev/ttyUSBX'
$ ./util/uart_stress_tester.py ./util/uart_stress_tester.py -t 120
Error: ./util/uart_stress_tester.py is not a character device.
Change-Id: I989a9e767796b04b059861aea2a3412877c1d739
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706626
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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According to the DisplayPort Alt Mode on USB Type-C specification, if
the DisplayPort Source device does not need to maintain HPD connectivity
information prior to entering a low power state, the device shall exit
the DP Alternate Mode. Previously, we were always entering DP Alt Mode
regardless of the SoC state. When we are shutting the device down to S5
or G3, there's no need to monitor the HPD connectivity information.
This commit simply does not enter DP Alt Mode when the SoC is off.
BUG=chromium:927636
BRANCH=firmware-nocturne-10984.B
TEST=Flash nocturne, shut DUT down to S5/G3, plug in a USB-C monitor
that can also act as a Source, verify with PD analyzer that DUT does not
Enter DP Alt mode, boot system up, verify that external display works.
Change-Id: I2ad3619cabeae5d90e8af1bfa9cab67452d9fc16
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1450815
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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