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* tablet-mode: Fix header file guard and API definitionsDaisuke Nojiri2019-07-181-6/+15
| | | | | | | | | | | | | | | | | | This patch adds a usual inclusion guard (#ifdef __CROS_EC_*_H) and fixes API descriptions. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: I96149cfe76cff7ab85be4785252a600b565e4a92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1696913 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* presubmit: don't require buildall for changes only in docs/Jack Rosenthal2019-07-181-0/+2
| | | | | | | | | | | | | Markdown docs don't affect the build. Make presubmit slightly nicer. BUG=none BRANCH=none TEST=run util/presubmit_check.sh after committing docs/ only changes Change-Id: I273dd071e3cf5e859a0a4f0f97e9011cc4391f0d Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706613 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* nocturne: Only source 5V when chipset is on.Aseda Aboagye2019-07-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | The power rail for the 5V used for sourcing is not available while the chipset is off. Therefore pd_set_power_supply_ready() should return an error if chipset is off. BUG=b:118646299 BRANCH=firmware-nocturne-10984.B TEST=Flash nocturne; plug in a USB Type-C ethernet adapter, run `dut-control power_state:rec` and verify that VBUS is present at the insert screen. TEST=Repeat the above test 20 times and verify that it always succeeds. Change-Id: Ie675d862dfbbe1e1ce08f6b203008ee784eb8ede Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1307699 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b6db88f25366a4519ad45d4b54e91cb40e7ea7fb) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1708266 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* driver/tcs3400: make error message in sensor read less spammy.Ting Shen2019-07-181-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | In EMULATED_IRQ_EVENT mode, we try to estimate the time between a read request and data ready. If the estimated time is shorter, an error message is printed to the console on every retry. On Kukui, this caused ec console spamming one line per second. Change the behavior to print only when returning error. No need to adjust the estimate time because one retry per read is still good enough. BUG=b:137345336 TEST=manually, verify that error message disappeared. BRANCH=None Change-Id: Ie85e8f1a80ea36ca5c50f57a19eba35f3f79f86d Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697889 Tested-by: Fei Shao <fshao@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Helios:Initial Type-C Controller PS8751 settingBarney_Liao2019-07-181-0/+7
| | | | | | | | | | | | | | | | Setting Type-C Port1 controller register 0xE8 (High Speed Signal Detector threshold adjustment) to 0x80 (-25%). BUG=b:136531130 BRANCH=master TEST=Manual Check Type-C Port1 register 0xE8. Change-Id: I5957fcd3389296500992ea3075dcde4a3b690f98 Signed-off-by: Barney_Liao <barney_liao@pegatron.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703724 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* printf: Fix hexdump and string 0 precisionCraig Hesling2019-07-183-49/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addresses a few issues with the current formatter. The major points are as follows: 1. Cannot specify precision 0 (truncate all) for string or hexdump 2. Forced safe precision for malformed strings 3. No padding when using hexdump 4. Bad error EC_ERROR_INVAL in vsnprintf 5. Documentation errors For (1), no piece of code explicitly sets the precision to 0 in order to invoke the default behavior, which is currently no precision limit. You can check using the following grep line: grep -rI '%[\*0-9]\{0,20\}\.0\{1,20\}[a-zA-Z]' However, there are many cases where the precision is used to limit the character output (as it should be). grep -rI '%[\*0-9]\{0,20\}\.[\*0-9]\{1,20\}[a-zA-Z]' There are many more instances that use variable precision without checking if the precision is zero. One of which is the following: crrev.com/4a4e2c71a0f6aaa50e0728922f84a7d54c14380a/test/host_command_fuzz.c#116 https://clusterfuzz.com/testcase-detail/5699023975088128 Our current implementation will insert ERROR and stop processing, if a precision of zero is detected when using the hexdump flag. This results in a badly formatted console line or runtime string, when the intended behavior would be to simply read no bytes. In the aforementioned fuzzer case, outputting ERROR triggers a false positive. Our printf should handle explicit zero precision similar to stdlib's printf, which means truncating all the way to zero positions, if specified. For (2), our current implementation uses strlen to identify the length of the input string, regardless of the set precision. Since this is an embedded platform, we should use strnlen to impose safe limits, when a precision is specified. For (3), our implementation should support padding and adjusting of all formatter types, since that is a primary feature of a printf formatter. The remaining commented code highlights odd behavior that should be fixed at some point, but is not critical. BUG=chromium:974084 TEST=Checked for any format lines that rely on a set precision of 0 grep -rI '%[\*0-9]\{0,20\}\.[\*0-9]\{1,20\}[a-zA-Z]' TEST=make run-printf V=1 BRANCH=none Change-Id: I897c53cce20a701fcbe8fb9572eb878817525cc3 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1659835 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip/host: Add spi+trng support, and add gpio funcCraig Hesling2019-07-185-1/+94
| | | | | | | | | | | | | | | | | | | | This adds fake SPI Master and TRNG support to the host target. This change also adds the missing emulated gpio interface function. Although general purpose, these changes are setup for allowing fuzzing of the FPMCU specific host commands. Thus, they do not impact any outstanding code. BRANCH=none BUG=b:116065496 TEST=make buildall -j Change-Id: Icfc40e7bf8ee421a4c3ad15377fd56ae68c763d7 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684223 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nocturne: Don't wake on any MKBP in suspend.Aseda Aboagye2019-07-171-1/+2
| | | | | | | | | | | | | | | | | | | | By fixing the bug(b/136282898) to allow MKBP events to wake the system in suspend, all MKBP events would wake the system which goes against our chrome OS wake sources spec. By defining CONFIG_MKBP_EVENT_WAKEUP_MASK, nocturne will not wake on any MKBP event. BUG=chromium:786721 BRANCH=firmware-nocturne-10984.B TEST=Build and flash nocturne, suspend DUT, plug in powered charge-thru hub w/ an external display connected, verify that DUT does not wakes up and display is not shown. Change-Id: I0810d0ea625689ee39f0e52b62a8ee7c00c49aad Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685788 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* pd_policy: Change DP AltMode event from host event to MKBP.Aseda Aboagye2019-07-173-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the EC could notify the AP that it had entered into DisplayPort Alternate mode by sending a MODE_CHANGE host event. However, there was no mechanism to disable that functionality if desired without effecting the other MODE_CHANGE events (i.e. - base attach/detach). By changing the DisplayPort Alternate mode entry to an MKBP event, we can have more granularity and only affect this single event. - This commit adds a new MKBP event, EC_MKBP_EVENT_DP_ALT_MODE_ENTERED. - The commit also changes the DP AltMode entry notification from sending a MODE_CHANGE host event to this new MKBP event. BUG=chromium:786721 BRANCH=None TEST=Build and flash nocturne, verify that system still wakes up on DisplayPort Alternate Mode entry. Change-Id: Ia5f294b26701c3c98c9b7f948fc693d26234c835 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685787 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* mkbp_event: Add CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT.Aseda Aboagye2019-07-172-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | MKBP was recently refactored to offer choice in the MKBP notification method. However, if a board is using a GPIO to notify the AP of a MKBP event, and the AP cannot wake from the GPIO, the MKBP event cannot wake the system up from suspend as is. This commit simply adds a new config option, CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT such that MKBP events can wake the system from suspend. Note that the board will have to add MKBP events to the host event sleep mask in coreboot. Typically on ARM devices, EC_INT_L is already a wake pin, but on Intel devices it is not; there's actually a different pin, PCH_WAKE_L which is set via sending a host event and wakes the system. BUG=b:136272898,chromium:786721 BRANCH=None TEST=Enable config option on nocturne, flash nocturne, suspend DUT, verify that MKBP events can wake the AP. Change-Id: If5026bfe3efacbc051f99a180e061c6fd679ce5a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685786 Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* common: add i2c tracing functionalityJack Rosenthal2019-07-175-6/+275
| | | | | | | | | | | | | | | | | | | crbug.com/982442 requests a way for developers to enable tracing of i2c commands when debugging. This adds a new debug feature, the i2ctrace command, which provides that. The command is guarded by CONFIG_I2C_DEBUG. BUG=chromium:982442 BRANCH=none TEST=enabled CONFIG_I2C_DEBUG on arcada_ish, made sure that command functioned as it says on the tin Change-Id: I9c762271237cbf131e5ef7c0f605c89af4f209fd Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699347 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* Basic implentation of the Maxim Integrated MAX32660 within the EC OSJerry Bradshaw2019-07-1723-0/+6305
| | | | | | | | | | | Includes System Clock, Timer, Uart, Watchdog Change-Id: I195059c87d97e70c6a134304143613b86b623e22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647741 Reviewed-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Jerry Bradshaw <jerry.bradshaw@maximintegrated.com> Commit-Queue: Jes Klinke <jbk@chromium.org>
* common: remove CONFIG_SMBUS dead codeDenis Brockus2019-07-175-342/+16
| | | | | | | | | | | | | | | | | CONFIG_SMBUS is not used. Cleaning up the code by removing this. Added a comment to document the removal and why. This will give a way to find the code if we ever needed to bring it back BUG=chromium:982316 BRANCH=none TEST=make buildall Change-Id: I40703a95bc849538e1aee32f6f96beab811285bd Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704279 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Add the functions to read and write EAR.Pai Peng2019-07-172-34/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | EAR (extended address register) is used to access addresses above 16MiB when 3-byte address mode is used. These two functions allow to write to and read from EAR to set up what addresses to access in 3-byte mode. For example, for a 64MiB EEPROM: EAR value Addresses to access 0 0x0000000 - 0x0FFFFFF 1 0x1000000 - 0x1FFFFFF 2 0x2000000 - 0x2FFFFFF 3 0x3000000 - 0x3FFFFFF BUG=b:132252340 BRANCH=none TEST=manual Testing: 1. Writing to EAR returns successfully. 2. Writing different values to EAR, verify that accessing EERPOM in 3-byte mode is to the correct address, e.g., when EAR=2, accessing 0x0FFFFFF is actually to 0x2FFFFFF. Change-Id: I2a8bde7fc4b9069afc80a81042fb47359bffa015 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688150 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Pai Peng <paipeng@google.com> Commit-Queue: Pai Peng <paipeng@google.com>
* cr50: do not enable TPM when compiling for dcrypto testsVadim Bendebury2019-07-172-6/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no room in the flash for both dcrypto tests and the TPM library. Let's disable TPM function (and not link the library) when the image is compiled with dcrypto tests included. BRANCH=cr50, cr50-mp BUG=b:137659935 TEST=verified that there is plenty of room for tests now: $ make BOARD=cr50 -j -k CRYPTO_TEST=1 CR50_DEV=1 . . . *** 8124 bytes in flash and 61564 bytes in RAM still ... in cr50 RO *** *** 66100 bytes in flash and 6000 bytes in RAM still ... in cr50 RW *** - building without CRYPTO_TEST=1 still produces a functional Cr50 image; - when building with CRYPTO_TEST=1, the version string reflects it: $ strings build/cr50/ec.bin | grep cr50_v | head -1 DBG/CT/cr50_v2.0.1776-46b015f6a - CCD of the images built with crypto test enabled is fully functional, in particular USB updates are operational. Change-Id: Iae91ca36dc203301ac423fe048fc67eb44ef5de6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704608 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* cr50: provide separate environment variable to enable crypto testsVadim Bendebury2019-07-172-5/+6
| | | | | | | | | | | | | | | | | | | | Presently the CR50_DEV environment variable is overloaded, if its value is a number exceeding 1, it enables inclusion in the image of the dcrypto tests. To make things cleaner let's use a separate environment variable to add dcrypto tests to the image. Note that the tests still can not be enabled, as they do not fit into the flash code space. BRANCH=cr50, cr50-mp BUG=b:137659935 TEST=verified that image building with CRYPTO_TEST=1 fails due to exceeded code size. Change-Id: I550c219c1eefe01fbe035b85a1d5aae88ea439de Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704607 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cleanup: refactor CPRINTF("[%T ...]\n") to CPRINTSJack Rosenthal2019-07-1713-43/+44
| | | | | | | | | | | | | | | | Looking at where the non-standard %T printf modifier is used in EC codebase, the majority is cases where CPRINTS could have been used instead of CPRINTF. This is a somewhat-mechanical refactor of these cases, which will make implementing a standard printf easier. BUG=chromium:984041 BRANCH=none TEST=buildall Change-Id: I75ea0be261bfbfa50fb850a0a37fe2ca6ab67cb9 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703128 Reviewed-by: Evan Green <evgreen@chromium.org>
* mt_scp: Trigger IRQ if has pending IPC when re-enable SCP_IRQ_IPC0.Yilun Lin2019-07-171-3/+18
| | | | | | | | | | | | | | | | | | | | Prevent a starved waiting IPC. IPC may be requested while SCP_IRQ_IPC0 is disabled, and this may result in AP dead waiting for a reply from SCP. This CL forces triggering the SCP_IRQ_IPC0 if seeing a pending IPC when re-enable the SCP_IRQ_IPC0. TEST=run factory front_camera_test for over 1 hr and see AP doesn't complains HC not respsonsed. BUG=b:136809224, b:136616282 BRANCH=None Change-Id: Ic36da774994f6c571c3b79fd6717562f8866b7df Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697884 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* mt_scp: Drop TCM and L1 cache setting.Yilun Lin2019-07-172-8/+11
| | | | | | | | | | | | | | | | | | | | This config has been moved to kernel https://crrev.com/c/1687454 to correctly initialize L1 cache. We should drop the config in SCP side. Also, update the comment for CM4_MOD registers. TEST=Boot SCP with kernel https://crrev.com/c/1627394/10 BUG=b:132658087 BRANCH=none Change-Id: I37613533563acc00017f96a3d3009383057f072b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703946 Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Erin Lo <erin.lo@mediatek.com> Commit-Queue: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org>
* Helios:Modify lid and base rotation matrixBarney_Liao2019-07-171-9/+4
| | | | | | | | | | | | | | Depend on placement modify rotation matrix for the lid and base sensor. BUG=b:135554555 BRANCH=ToT TEST=Manual Check EC console accleinfo. Change-Id: I287808dde06ff752f9e10766f3c348e0d63606f3 Signed-off-by: Barney_Liao <barney_liao@pegatron.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1687037 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* stm32: Add known variants to registers filesCraig Hesling2019-07-175-0/+21
| | | | | | | | | | | | | | | | | | Although these registers files may support other variants, these listed variants are the only ones that are referenced throughout EC codebase. They were collected using the following grep line: grep -rIi 'variant.*stm32.' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I3691d8db5c2a6c1a94bb5df40edf12504c3fee7e Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700168 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Factor out stm32f7 family registersCraig Hesling2019-07-174-55/+1093
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extracts the STM32F76X variant from the STM32F4 family registers file. This also removed a redundant #ifdef CHIP_FAMILY_STM32F4 inside the F4 family register file. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash # Make dummy board for STM32F76X using STM32f7 fammily mkdir -p board/usestm32f7 printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f7\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk touch board/usestm32f7/board.h ./registers-extract.bash board-regs-new git checkout cros/master # Change family back to STM32F4 printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f4\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new # Expect only a difference in CHIP_FAMILY Change-Id: I5ff87e1c82c5d27d78c3ea62fed29d647a0f98db Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700167 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Add header guard and fix fmt/doc of registers header fileCraig Hesling2019-07-177-260/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | We enforce that all family specific registers file can only be included from registers.h. We add a brief history and rationale behind splitting registers.h into multiple family specific header files. We fix formatting of preprocessor conditionals and documentation. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I5d5983eb1e0cf7fb46339cba2987d551ff6b16cc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693879 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cleanup: Segregate USB MUX related drivers in usb_mux folderVijay Hiremath2019-07-1713-17/+17
| | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: If44a363d1288cbfabe5c6545e550f2b8fc623227 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700793 Reviewed-by: Jett Rink <jettrink@chromium.org>
* kohaku: Support SDI battery packPhilip Chen2019-07-172-1/+30
| | | | | | | | | | | | | BUG=b:130578043 BRANCH=none TEST=battery command on EC console Change-Id: I2518892dac3daeae8734bd3b45f225f4723dc7c6 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704788 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* ectool: put help menu items in alphabetical orderCurtis Malainey2019-07-171-2/+2
| | | | | | | | | | | | | fo* should come before fp* TEST=print help Change-Id: Ic8ea8582bd1aebfb389427d959b8819aecb67378 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703391 Tested-by: Curtis Malainey <cujomalainey@chromium.org> Auto-Submit: Curtis Malainey <cujomalainey@chromium.org> Reviewed-by: Jon Flatley <jflat@chromium.org> Commit-Queue: Jon Flatley <jflat@chromium.org>
* config: Add CONFIG_MKBP_EVENT_WAKEUP_MASKAseda Aboagye2019-07-172-4/+30
| | | | | | | | | | | | | | | | | | | This commit adds a new CONFIG_* option, CONFIG_MKBP_EVENT_WAKEUP_MASK. This allows a board to specify which MKBP events are allowed to wake the system when it is in suspend. BUG=b:136282898,chromium:786721 BRANCH=None TEST=With some other code, flash nocturne, suspend DUT, verify that only the MKBP events in the CONFIG_MKBP_EVENT_WAKEUP_MASK wake the system up. Change-Id: Ib4d04418aacab209d0e26703500df119924090b7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685785 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* fluffy: Initial board commit.Aseda Aboagye2019-07-176-0/+566
| | | | | | | | | | | | | | | | | | | | This contains the initial firmware for Fluffy rev 1.1 boards. Fluffy is a 20:1 USB-C power mux. For more information, see go/usbc-fluffy. BUG=b:136671092,b:134075217,b:134074302,b:134074465,b:134075521, b:134075834 BRANCH=None TEST=flash fluffy, verify it boots and functions. Change-Id: Ica6817e7cfa4481aa98fed1c24ea243bf622eb2a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1535117 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* stm32: Manually fix separate register filesCraig Hesling2019-07-165-92/+4
| | | | | | | | | | | | | | | | | | | | | | This fixes the CPP conditionals that could not be separated using the split script. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I40eac114cd5ed7abe708cc51242a3b267aaaf118 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693876 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* kohaku: Always return BP_YES for battery presence for board id 1Furquan Shaikh2019-07-161-0/+15
| | | | | | | | | | | | | | | | | | | | | | For kohaku board id 1, there is a known issue which prevents in getting battery presence signal correctly. This change returns BP_YES if the board id reads out as 1. In all other cases, it returns BP_NOT_SURE to allow baseboard to read gpio to determine battery present state. BUG=b:135278000 BRANCH=None TEST=None Change-Id: I882f05ddcf4e8a0127f336b4a524bf162ad796b5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1702870 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YongBeum Ha <ybha@samsung.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Tested-by: YongBeum Ha <ybha@samsung.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* baseboard/hatch: Allow hatch variant to provide battery present infoFurquan Shaikh2019-07-162-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | In case of some hatch variants, there might be a need to identify battery hardware presence using custom method i.e. GPIO_EC_BATT_PRES_ODL might not work correctly. In order to accommodate these variants, this change provides a callback variant_battery_present() that allows variant to provide its own implementation if required. By default, a weak implementation is provided which returns BP_NOT_SURE to use the default GPIO for reading battery present state. BUG=b:135278000 BRANCH=None TEST=None Change-Id: I8504e807cff853dc3276d76a0cd3db1ccb587b9e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1702869 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YongBeum Ha <ybha@samsung.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Tested-by: YongBeum Ha <ybha@samsung.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* util: ecst: Fix Coverity print format warningsEvan Green2019-07-162-13/+8
| | | | | | | | | | | | | | | | | | | | | | | I noticed Coverity is complaining about a handful of printf format warnings. These were all valid. It looks like a robot, or perhaps a very hasty human went through and split printf strings that extended over 80 columns into multiple calls. But they didn't make sure that the arguments went into the correct corresponding printf call. Recombine a few of those printfs back into a single call, and fix a few other printf-related odds and ends. Also, add the format specifier to my_printf so that these errors are detected at compile time in the future. BUG=chromium:984041 TEST=make -j buildall BRANCH=None Change-Id: I27b352b97d50fbbaee2fb801b817ef82ad90ca98 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1698488
* stm32: Split registers.h into independent filesCraig Hesling2019-07-157-2706/+6243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the sort_file.bash script from this bit: http://go/bit/hesling/5840756455505920/7 $ git fetch "https://chromium.googlesource.com/chromiumos/platform/ec" refs/changes/78/1674678/6 && git cherry-pick FETCH_HEAD $ cp registers.h registers-split.h $ ./sort_file.bash chip/stm32/registers-split.h f0=chip/stm32/registers-stm32f0.h f3=chip/stm32/registers-stm32f3.h f4=chip/stm32/registers-stm32f4.h h7=chip/stm32/registers-stm32h7.h l=chip/stm32/registers-stm32l.h l4=chip/stm32/registers-stm32l4.h com=chip/stm32/registers.h Modified registers.h to include chip family specific header file. Modify copyright year of output files. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: Ia7804e9a346ed94f881bd5583f5a4bf78422cb47 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1674679 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ectool: Add support for EC_CMD_FLASH_INFO version 2Tom Hughes2019-07-151-12/+70
| | | | | | | | | | | | | | | | | BRANCH=none BUG=b:132444384 TEST=On hatch_fp: ectool --name=cros_fp reboot_ec; sleep 0.5; ectool --name=cros_fp rwsigaction abort; dd if=/dev/urandom of=/tmp/rand_file bs=1 count=131072; ectool --name=cros_fp flashwrite 262144 /tmp/rand_file Change-Id: I22f70ae29285dc5bded558b9f0bcbe5040a80750 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1677234 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* fpsensor: Extend unit test for FPTPM seed set status.Yicheng Li2019-07-151-27/+48
| | | | | | | | | | | | | | | | Extend the unit test for checking FPTPM seed status, specifically: 1. After seed is set, try set the seed again, expect failure. 2. At this point, check that the seed is still set. BRANCH=nocturne BUG=chromium:952275 TEST=make -j buildall TEST=tested enrollment, matching and multifinger on DUT nocturne. Change-Id: I2be9d2c21b552f242dd88f33361398755b6c2e84 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1643659 Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* arcada: ensure i2c transmit fifo is emptyLeifu Zhao2019-07-141-2/+3
| | | | | | | | | | | | | | | | | | | | Make sure transmit fifo is empty before disable i2c controller during transfer, otherwise the i2c write may fail for speed 100k, it also helps 400K and 1M. BUG=b:137218876 BRANCH=none TEST=tested on arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I6f9fb9a71c28f2d3f9696340cc87fe3b72c25a02 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697061 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* Bobba: Add new LGC batteryben.chen2@quanta.corp-partner.google.com2019-07-122-0/+30
| | | | | | | | | | | | | | | | new battery: LGC AP19A8K BUG=b:135496272 BRANCH=octopus TEST=Make sure battery can cutoff by console "cutoff" or "ectool cutoff" and resume by plug in adapter. Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Change-Id: I11a00c0ee88a668dcfd995b46f4b6dd43fec318b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1657076 Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: David Huang <David.Huang@quantatw.com> Tested-by: David Huang <David.Huang@quantatw.com>
* ish: fix aon task not auto rebuild issue in increment buildHu, Hebo2019-07-123-29/+38
| | | | | | | | | | | | | | | | | | | | | aon task image build rules are lack of dependent rules of source code, so can't track the source code changes and trigger auto build. Refactor build rules for aon task to make sure always auto rebuild when aon task's source code and dependent header files update BUG=b:136691893 BRANCH=none TEST= ish aon task should always rebuild when it's code and dependent header files update Change-Id: I0d8c7c6a4a2b7e99d724b88b233e09a29b8facea Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688701 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* stm32h7: Fail build if CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE not usedTom Hughes2019-07-111-0/+3
| | | | | | | | | | | | | | | | As comment indicates, we're not sure that using RSS1 for the write protect PSTATE is safe. BRANCH=none BUG=chromium:888104 TEST=In nocturne_fp board.h file: #undef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE => Build fails with error as expected Change-Id: I0236381738e7ecf9b18a8d10dc7ba4b9dc370001 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693339 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* util: uart stress tester using 'chargen' commandNamyoon Woo2019-07-103-353/+511
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Uart stress tester runs a 'chargen' UART command on EC and/or AP, and checks if any characters are lost from UART output. BUG=b:131340067 BRANCH=None TEST=ran on Bob and Octopus (Fleex) $ ./util/uart_stress_tester.py -h usage: uart_stress_tester.py [-h] [-c] [-d] [-t TIME] [port [port ...]] uart_stress_tester.py repeats sending a uart console command to each UART device for a given time, and check if output has any missing characters. Examples: uart_stress_tester.py /dev/ttyUSB2 --time 3600 uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 --debug uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 --cr50 positional arguments: port UART device path to test optional arguments: -h, --help show this help message and exit -c, --cr50 generate TPM workload on cr50 -d, --debug enable debug messages -t TIME, --time TIME Test duration in second $ ./util/uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 -t 120 INFO | UartSerial| EC | 0 char lost / 1382400 (0.0 %) INFO | UartSerial| AP | 0 char lost / 1382400 (0.0 %) INFO | ChargenTest | PASS: lost 0 character(s) from the test $ ./util/uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 -t 120 --cr50 INFO | UartSerial| EC | 0 char lost / 1382400 (0.0 %) INFO | UartSerial| AP | 0 char lost / 1382400 (0.0 %) INFO | ChargenTest | PASS: lost 0 character(s) from the test Change-Id: I713fb0180db3ca5904bd7aae0dd26a4633733d2e Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1683011 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* stm32: Make sure watchdog is enabled when using it to resetTom Hughes2019-07-101-0/+30
| | | | | | | | | | | | | | | | | | | | | On hatch (using hatch_fp), the watchdog appears to never fire when issuing the following commands: ectool --name=cros_fp flashprotect enable ectool --name=cros_fp reboot_ec Adding the explicit enable of the watchdog here fixes that. BRANCH=none BUG=b:137045370 TEST=On hatch: ectool --name=cros_fp flashprotect enable ectool --name=cros_fp reboot_ec Change-Id: Ib42b67a2c88a5c11e3064523d74c9ded51f71379 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692078 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Don't refer to specific MCUs in the README introHarry Cutts2019-07-091-5/+1
| | | | | | | | | | | | | | | | | | | | This statement seems pretty out-of-date, and keeping it up-to-date isn't going to be worthwhile, so just make it more generic. (This is the same change as was made in revision #41 of the sites page before it was migrated [0], but it seems the Markdown migration took the version before.) [0]: https://sites.google.com/a/chromium.org/dev/system/app/pages/admin/compare?wuid=wuid:gx:3ac9dfd5b19509d3&rev1=41&rev2=40 BRANCH=none BUG=none TEST=none Change-Id: I0570b719af6699b4467309fccd312e1be68d6f14 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693335 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ish: cleanup i2c constantsJett Rink2019-07-092-21/+26
| | | | | | | | | | | | | | Rename i2c constants to expose the speed they represent. BRANCH=none BUG=none TEST=builds. arcada i2c bus speed is correct Change-Id: If26f4868053f5df0a83bf1f06b62b6969dd5a44f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1691310 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* arcada: lower i2c bus speed to 400kHzJett Rink2019-07-091-1/+1
| | | | | | | | | | | | | | | | The sensors on the i2c line do not operate reliably at 1Mhz i2c bus speed. Lower to 400kHz BRANCH=75,76 BUG=b:136676970 TEST=verify that i2c bus speed when from ~1Mhz to ~400kHz after this change with an oscilloscope. Change-Id: Ie970f76fe7408de17f92bfc9f22a951b635fd278 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1691309 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* kukui: code cleanupTing Shen2019-07-093-39/+4
| | | | | | | | | | | | | | | Remove unused clode blocks and includes. BUG=None TEST=make BRANCH=master Change-Id: I66994039e4c215ce652cdef227207a6bbd94b316 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692364 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* kohaku: coordinate a rotation matrix for accel sensorstabilize-12331.BInno.Park2019-07-091-3/+3
| | | | | | | | | | | | | Adjust the rotation matrix for lid accel to fit the kohaku board. BUG=b:136626453 BRANCH=master TEST=Boot and check if the system keyboard and touchpad work Change-Id: Icd1f634924693b2e951bbb7cf5d090c980fa95b0 Signed-off-by: Inno.Park <ih.yoo.park@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686925 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Revert "ish: enter ISH ROM during reset prep"Jack Rosenthal2019-07-091-1/+1
| | | | | | | | | | | | | | | | | | This reverts commit 58f535e8c175311d866d4c1dd2d283d69230e9c5. Now that b:136265450 has an actual fix landed, we need to revert this workaround to reduce power usage when the system is off. BUG=b:136265450 BRANCH=R76,master TEST=press 'shut down' on normally failed DUT, observe ISH come alive at next boot multiple times Change-Id: I623249dfcb697a055378ca721721f346b01b7a8e Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1691116 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* ish: fix osscaisonally not load issue when doing shutdown & rebootHu, Hebo2019-07-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before switch to aon task, cache and ROM will be power gated (PMU_RF_ROM_PWR_CTRL control register) in ecos, and resume after switched back to ecos. But for reset_prep/D3 process, aon task will reset minute ia to ROM finally but forget to resume the power of ROM. This keeps ROM still power gated and make ROM code can't run correctly. The fix is simple, just disable power gating of ROM before reset to ROM in aon task. BUG=b:136265450 BRANCH=none TEST=ISH fw should always load Change-Id: Ib26678bbfdd5dbb17389154478f2565c44d392ab Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684825 Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Yangzhong Ge <yangzhong.ge@intel.corp-partner.google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* kukui: add chargen to the set of CLI commandsVadim Bendebury2019-07-041-0/+1
| | | | | | | | | | | | | | | This is needed to support CCD testing of UART to USB bridging. BRANCH=none BUG=b:38448364 TEST=ran 'make BOARD=kukui -j', verified that command is included in the symbol map. Change-Id: I675df026c16b5c0b07ed55c99aa5e8b333fd0fab Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688136 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* Rename CONFIG_CHARGEN to CONFIG_CMD_CHARGENVadim Bendebury2019-07-042-4/+2
| | | | | | | | | | | | | | The updated name is more is better aligned with EC codebase use of CONFIG_ variables. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I52a35e33debb2cab41c009dbb8938614a810baef Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688134 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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