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* host_command: clear any leftover dataJett Rink2019-11-263-2/+153
| | | | | | | | | | | | | | | We want to ensure that the entire buffer we may be sending back to the host from the EC does not contain any data from previous host command responses. Clear the data in common code so all chips do not have to implement this functionality. BRANCH=none BUG=b:144878983,chromium:1026994 TEST=new unit test shows cleared data Change-Id: I93ad4d36923ba1bf171f740e94830640d3fde3b0 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930931
* cortex-m/m0: Reformat linkers script with tabsCraig Hesling2019-11-262-604/+635
| | | | | | | | | | | | | | This is just a cleanup of the linker scripts for cortex-m chips. This brings no functional change. BRANCH=none BUG=none TEST=make buildall Change-Id: If9fa43157e8955fed7c7426b910c6af957794b0b Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930392 Reviewed-by: Jett Rink <jettrink@chromium.org>
* puff: update PP3300_SNS dividerPeter Marheine2019-11-261-3/+9
| | | | | | | | | | | | | | The schematic has changed to 9.31k / 47k resistors on this input. BUG=b:1829597655 TEST=still builds BRANCH=None Change-Id: I2856df05b2611edd30d497a35bb871b8f5b173e9 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1935467 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* treeya : Add new battery informationxiaoqiang.zhu2019-11-262-1/+94
| | | | | | | | | | | | | | | | | | | | | | | treeya need support three new batteries --SMP:L19M3PG1 --LGC:L19L3PG1 --Celxpert:L19C3PG1 The same manufacturer(SMP) has two kinds of batteries, manuf_name can't specify the unique battery, so need to check device_name. BUG=none BRANCH=none TEST=boot treeya board with new batteries, charging/discharging/cutoff work as expected. Change-Id: I09e2a68961e5df92c6b6d639963ac8894eb7ec20 Signed-off-by: xiaoqiang.zhu <xiaoqiang.zhu@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1933788 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Tested-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Commit-Queue: Edward Hill <ecgh@chromium.org>
* flash_ec: Fix accidental dut-control invocationFei Shao2019-11-261-1/+1
| | | | | | | | | | | | | | | | There's a typo when calling dut_control in CL:1884252, which causes "--port" argument is missing when executing flash_ec. BUG=b:145103343 BRANCH=kukui TEST="util/flash_ec --image ${IMG} --board ${BOARD} --port 9998" works Change-Id: I8c79797be4a665bd9ab8c3770c5199f2f798c6c4 Signed-off-by: Fei Shao <fshao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1932869 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* trembyle: tcpc fault needs to be clearedDenis Brockus2019-11-251-0/+22
| | | | | | | | | | | | | | | | | We currently do not use the TCPCI fault for anything but need to clear any faults to stop an alert storm. Added debug output so we can see what is coming out in times of fault, just as an FYI. BUG=b:144126745 BRANCH=none TEST=insert-extract charger from USB-C0 and verify AC on/off Change-Id: Ifc5ffc4e18790e6fc9763bbeb334cbdff901ad43 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1934045 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: make BB virtual mux retimer compatible with non-virtualDenis Brockus2019-11-259-109/+49
| | | | | | | | | | | | | | | | Changed the driver interface for BB virtual mux retimer to stop using global functions and use the usb_retimers array instead. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I56befaca1720eb2f4e0599a983629b4df45dc76b Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928121 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* zork: make product ID project levelDenis Brockus2019-11-252-8/+8
| | | | | | | | | | | BUG=none BRANCH=none TEST=none Change-Id: I7cd71e246708dd4423b7fc3021a644e2988e2771 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930868 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Reland "smart_battery: add smbus error checking support"Ting Shen2019-11-255-44/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reland of daccb3adea9394116d7ab2c807e4a360cb5a93a1 Original change's description: > smart_battery: add smbus error checking support > > Jacuzzi/Kodama has a unstable software controlled i2c bus, its data > transmission may be interrupted by other higher priority tasks and > causes device timeout. > > If timeout happens when ec is reading data, it has no knowledge about > what's happening on slave, and keep receiving bad data (0xFF's) until > end. The standard i2c/smbus error handling mechanism can not handle this > case, so we need the error checking feature from smbus 1.1 to ensure our > received data is correct. > > This CL adds the error checking (PEC) functions to i2c and smart battery > module. > > BUG=b:138415463 > TEST=On kodama, enable CONFIG_CMD_I2C_STRESS_TEST, > no failure after 100k read/writes. > test code at CL:1865054 > BRANCH=master > > Change-Id: Ibb9ad3aa03d7690a08f59c617c2cd9c1b9cb0ff3 > Signed-off-by: Ting Shen <phoenixshen@google.com> > Reviewed-on: http://crrev.com/c/1827138 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Tested-by: Ting Shen <phoenixshen@chromium.org> > Commit-Queue: Ting Shen <phoenixshen@chromium.org> BUG=b:138415463 TEST=in addition to the TESTs above, verified this CL boots on hatch(npcx chips), and reef_it8320(it83xx chips). BRANCH=master Change-Id: I67975eee677cfd6e383742d48103662372cac061 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1913940 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* battery : differentiate overtemperature conditionYongBeum.Ha2019-11-251-2/+13
| | | | | | | | | | | | | | | | Battery charging is stopped over 55'C during charging and started below 45'C. BUG=b:140596424 BRANCH=hatch TEST=make -j BOARD=kohaku && ./util/flash_ec --board=kohaku check charging status & led on chamber Change-Id: Ib4a8ba5236d107397db904ca7075f0d0f29dd724 Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928539 Tested-by: YongBeum Ha <ybha@samsung.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* TCPMv2: Keep message transmission and reception synchronizedSam Hurst2019-11-242-52/+114
| | | | | | | | | | | | | | | | | | | | | If a message is expected after a transmit, hold off on checking for that until the sender response timer is set. BUG=chromium:1022715 BRANCH=none TEST=make -j buildall manual tests: Connect StarTech CDP2DP USB-C to DP dongle Observe REQUEST send less than 1ms after SRC_CAP Look for ACCEPT message sent by PE and PD Change-Id: I1d155ead698ac39172c604cc3f656631565855d5 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907807 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* jinlon: add FAN2 supportDevin Lu2019-11-243-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:141259174 BRANCH=hatch TEST=faninfo can see the 2nd fan works with console. 2019-11-22 14:23:55 Fan 0 Actual: 3309 rpm 2019-11-22 14:23:55 Fan 0 Target: 3291 rpm 2019-11-22 14:23:55 Fan 0 Duty: 42% 2019-11-22 14:23:55 Fan 0 Status: 2 (locked) 2019-11-22 14:23:55 Fan 0 Mode: rpm 2019-11-22 14:23:55 Fan 0 Auto: yes 2019-11-22 14:23:55 Fan 0 Enable: yes 2019-11-22 14:23:55 Fan 0 Power: yes 2019-11-22 14:23:55 2019-11-22 14:23:55 Fan 1 Actual: 3101 rpm 2019-11-22 14:23:55 Fan 1 Target: 3291 rpm 2019-11-22 14:23:55 Fan 1 Duty: 37% 2019-11-22 14:23:55 Fan 1 Status: 2 (locked) 2019-11-22 14:23:55 Fan 1 Mode: rpm 2019-11-22 14:23:55 Fan 1 Auto: yes 2019-11-22 14:23:55 Fan 1 Enable: yes Change-Id: I88aa8efcbb55d8a64ae51c68b5a142e5a4997f46 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928542 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* TCPMv2: PD: Separately track each SOP and SOP' and SOP''Sam Hurst2019-11-246-94/+177
| | | | | | | | | | | | | | | | | | Tracked PD header spec. version for each port partner type. BUG=chromium:1023025 BRANCH=none TEST=make -j buildall Manual Testing: Connected PD2.0 source charger and made sure we talked PD2.0 Connected PD3.0 source charger and made sure we talked PD3.0 Connected apple 2019 PD2.0 dock with charger and made sure we downgraded from PD3.0 to PD2.0 Change-Id: I3b49d9630acf6c19101ac71334445890c78c4077 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907430 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: ServoV4 is not recognized appropriatelySam Hurst2019-11-223-95/+347
| | | | | | | | | | | | | | | | | | Configure the port as a SNK with PD in DebugAccessory.SNK state BUG=chromium:1020752 BRANCH=none TEST=make -j buildall Manual Test: 1: Connect Servo v4 with NeckTek charger pluged in DUT power port The DUT negotiates to 20V, and starts charging. Change-Id: Id44d566024b5016965f996435d11befdc1c53e98 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906993 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: fix storm tracker overflow issueJett Rink2019-11-226-6/+145
| | | | | | | | | | | | | | | | | | | If there is no USB-C interrupt activity for 2^31 microseconds, then there are more than ALERT_STORM_MAX_COUNT events within 2^31 microsecond (instead of ALERT_STORM_INTERVAL), then the interrupt storm would incorrectly detect a storm and disable the port due to incorrect math regarding 32-bit overflow. BRANCH=octopus and all branches with original storm detection (CL:1650484) BUG=b:144369187 TEST=unit test in CL Change-Id: I90b888ac092f81d151538d6018771fb32f8e9c39 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925668 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* cr50: prepare to release 0.{3,4}.24Vadim Bendebury2019-11-222-2/+2
| | | | | | | | | | | BRANCH=cr50, cr50-mp BUG=none TEST=none Change-Id: I2bef8173536cdf4d584b93169d22c6120daed7f2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930141 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* krane: Use the PWM mode to adjust brightness as lowestLeo Zhou2019-11-221-4/+22
| | | | | | | | | | | | | | | | | | Adjust current=4ma, pwm=1/32, and change the state as: charging is blue charged full is green low battery is red BUG=b:137618886 BRANCH=kukui TEST=Do a full charging test, notice LED indicator status under different charge state Change-Id: Ic1b7a99ab3edaee5c92a5cae56bc6d9a321e9c23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918995 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Tested-by: Kook Zhang <zhangbinbin@huaqin.corp-partner.google.com> Commit-Queue: Leo Zhou <zhoubo@huaqin.corp-partner.google.com>
* npcx7: i2c: enable FIFO mode to transmit and receive dataCHLin2019-11-223-80/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx7, all I2C modules have separate 32-byte transmit FIFO and 32-byte receive FIFO buffers. In this CL, we add the FIFO mode support to the I2C driver. This will help to reduce the firmware overhead (i.e. the occurrence of I2C interrupt) during long I2C transactions by allowing the EC to write/read more than one byte of data at one time to I2C module and hence improve the I2C performance. The FIFO mode is enabled by default on all npcx7 series chips. BUG=none BRANCH=none TEST=No error for "make buildall" TEST=Connect npcx7 EVB to the I2C slave emulator, do stress test: 1. iterate ~2000 times of single i2c_xfer_unlocked API call. i.e. i2c_xfer_unlocked(.., I2C_XFER_SINGLE) 2. iterate ~2000 times of multiple i2c_xfer_unlocked API calls: i.e. i2c_xfer_unlocked(.., I2C_XFER_START) i2c_xfer_unlocked(.., 0) . . i2c_xfer_unlocked(.., I2C_XFER_STOP) 3. Issue 6 I2C transactions by 6 tasks at the same time. iterates ~2000 times. TEST=with this CL; build and upload an image (with/without FIFO mode enabled.) to yorp; no symptom occurs. Change-Id: I387e8ef6e619acef670273f08ab4150e3d2b75f2 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827137 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* it83xx/config_chip: remove configurationtim2019-11-221-1/+0
| | | | | | | | | | | | | | | | The CONFIG_HOSTCMD_X86 will get automatically defined if either CONFIG_HOSTCMD_LPC or CONFIG_HOSTCMD_ESPI are defined. So this definition is redundant in config_chip.h BUG=none BRANCH=none TEST=make buildall -j Change-Id: I3cb9b61d4b006becba5eb75e0dabe61bd9e3c999 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868134 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/spi_master: correct the module IDtim2019-11-222-6/+6
| | | | | | | | | | | | | | The module ID in alternate function setting for spi master should be corrected as MODULE_SPI_MASTER. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ib52b09a5f1e0c496374d4ed2f3a222dab9af2eb0 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868133 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/nds32 and riscv-rv32i/ec.lds.S: no assert if section is not presenttim2019-11-222-2/+4
| | | | | | | | | | | | | | | When the h2ram section is not present, we don't need the assert to check the space whether enough or not. BUG=none BRANCH=none TEST=No error when we don't define configration of CONFIG_HOSTCMD_x86 or CONFIG_H2RAM_SIZE. Change-Id: Id5d0e674f65cfdb220bc996c597740390000d861 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868132 Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/it8xxx1, chip/it8xxx2: GPIO, WUC and IRQ for chip it83201/it83202Ruibin Chang2019-11-223-39/+282
| | | | | | | | | | | | | | | | | | | | GPIO, WUC and IRQ changes for chip it83201/it83202. BRANCH=None BUG=b:133460224 TEST=test GPIO group O, P, Q, R 1.Input: external input 3.3v, GPDR of corresponding pin is 1. (GCR31, GCR32 select 1.8v, validate again for O and P group) 2.Output: GPDR of corresponding pin set 1, measure 3.3v. 3.INT: GPIO_INT input trigger => WU INT (select high, low, rising, falling, both edge trigger mode) => INT => CPU INT 4.Test power-up and down with this CL on ampton. Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704 Reviewed-by: Jett Rink <jettrink@chromium.org>
* all hatch variants: Make sure EC_RST_ODL is GPIO_LOCKEDShelley Chen2019-11-225-0/+55
| | | | | | | | | | | | | BUG=b:144886704 BRANCH=hatch TEST=make buildall Change-Id: I0d520a5c375a2b47c55a335da91f556ccfd59c29 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928422 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* all hatch variants: Assign SYS_RST_ODL to GPIOC5Shelley Chen2019-11-225-4/+5
| | | | | | | | | | | | | | | | | There is an error where SYS_RST_ODL is assigned to GPIO02 where it is actually assigned to GPIOC5 in the schematics. This should cause AP reset to fail from the ec console. BUG=b:141476349 BRANCH=hatch TEST=None (I don't have a hatch board to test this out on) Change-Id: I855a65489ce974ee92be4bf51a83d5af40e4e2da Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928421 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* Ensure CEC bus pin is not driven lowFelix Ekblom2019-11-221-0/+3
| | | | | | | | | | | | | | | | | | We have seen cases where after a cold EC reboot the pin is low until the first CEC message is sent by AP (after which the bus is left in a well defined state again) This is a follow up to https://crrev.com/c/1346990 which initializes the pull up in case not done by the RO FW. BRANCH=none BUG=b:144548408 TEST=CEC pin only goes low for ~40ms instead of 30s. Signed-off-by: Felix Ekblom <felixe@chromium.org> Change-Id: I3c98f8858f407279ad1bd086210969d69df2230b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928993 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* gsctool: delay RO update for old cr50 imagesMary Ruthven2019-11-221-0/+35
| | | | | | | | | | | | | | | | If Cr50 is running older than 0.3.20, delay the RO update 1 minute after the RW update, so Cr50 doesn't reject the RO blocks because their offsets are less than the RW offsets. BUG=b:144873413 BRANCH=none TEST=update board running RO 0.0.10 RW 0.3.18 to the RO 0.0.11 RW 0.3.22 image. Change-Id: I0179cc235c692133b08cd3430d71069b2f94bf69 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1929481 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Dratini/Jinlon: Add support for TEMP_SENSOR3Devin Lu2019-11-226-10/+28
| | | | | | | | | | | | | | A new temperature sensor is added to Dratini/Jinlon boards, close to the CPU. It is used to support the fan control. BUG=none BRANCH=hatch TEST=temp command in EC console Change-Id: Icd5974133da5e1aec81f2201f87e1b83b79c6169 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925802 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* battery : Define CONFIG_BATTERY_DEAD_UNTIL_VALUEYongBeum Ha2019-11-223-0/+15
| | | | | | | | | | | | | | | | It takes 850ms~950ms to get valid RSOC after battery wake-up. Sometimes battery FG returns garbage data(1%) as RSOC and 0 value of desired current / voltage. Add CONFIG_BATTERY_DEAD_UNTIL_VALUE to continue charging. BUG=b:138413964 BRANCH=None TEST=build & flash, check battery charging with dead battery Change-Id: I0cbe30aa973499b0c27faf9b6da03a0344ad1065 Signed-off-by: YongBeum Ha <ybha@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918985 Reviewed-by: Jett Rink <jettrink@chromium.org>
* jinlon: change TCPC port 0 from ANX7447 to PS8751Devin Lu2019-11-223-9/+8
| | | | | | | | | | | | | | | | | This patch chagnes TCPC port 0 from ANX7447 to PS8751, It includes the gpio name, function name and reset signal. BUG=none BRANCH=hatch TEST=make sure tcpc port 0 is workable. Change-Id: I698d70750727080f46cffdc136ffd8a54967ca89 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918984 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
* Trogdor: Initial board commitWai-Hong Tam2019-11-2211-0/+2530
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is an initial commit for Trogdor. Use Cheza as a baseline. Make the change according to the schematic, e.g. * Reflect the GPIO change * Reflect the TCPC/PPC part change * Update the USB topology, e.g. no device mode support * Remove the detachable related code * Add keyboard support * Support keyboard backlight * Update the battery characteristic * Add initial support of muxing DP path * Support a single USB-A port * Change sensors from lid to base * Minor code style improvement BRANCH=None BUG=b:143616352 TEST=BOARD=trogdor make Change-Id: Ia9bb0adfcb8d347e6335fd3ae1e565b0f9d1a025 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1847204 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cleanup: Segregate ioexpander related drivers in ioexpander folderVijay Hiremath2019-11-2216-12/+12
| | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I7fe9ab23254dbd8515936d10ad6782305e76236c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925173 Reviewed-by: Jett Rink <jettrink@chromium.org>
* doc: document USB_PID strategyJett Rink2019-11-221-1/+8
| | | | | | | | | | | | | | | | We want to have a single USB VID/PID per platform. If we need further granularity within a platform, then we can use the HW version field within the AMA VDO. BRANCH=none BUG=none TEST=none Change-Id: Ia32f8c2b41efc04e570c8f6d92b3e1307948863a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1910451 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* flash_ec: Fix servo micro boot0 for fpmcu/usbpdCraig Hesling2019-11-221-0/+4
| | | | | | | | | | | | | | | | | This CL fixes servo micro flashing for fpmcu and usbpd. This broke after crrev.com/c/1884252. The error seen was the following: ./util/flash_ec: line 496: servo_micro_usbpd_boot0: command not found BRANCH=nocturne,hatch BUG=none TEST=./util/flash_ec --board=dartmonkey --image=./build/nocturne_fp/ec.bin Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: Ic98fb31e29ee25d5397d38d5e742727a909994e7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1924990 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: Enable TCPC low power when port is looking for a connectionSam Hurst2019-11-219-256/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port is in a state where it is looking for a connection, to save power, we should put the TCPC in its low power mode and enable auto toggling. Low power mode can happen when DRP auto toggling, acting as a SNK only, or acting as a SRC only. BUG=chromium:1022217 BRANCH=none TEST=make -j buildall manual tests: 1: (S0) Nothing plugged in, port is drp and low power mode 2: (S5/S3/S0ix) Port is SNK only, and low power with nothing plugged in 3: (S3/S0ix) If TypeC sink was previously plugged in, port remains powered 4: (S5/S3/S0ix) TypeC source is recognized 5: (S3->S0) TypeC sink plugged in, port is powered when S0 is reached Low power exit test: Using this command from the AP console: ectool i2cread 8 2 0x16 0x0d Transfer failed with status=0x1 # This means the TCPC was asleep. On the EC console: 2019-11-21 09:50:24 [315.235538 TCPC p1 init ready] 2019-11-21 09:50:24 [315.236048 TCPC p1 Exit Low Power Mode] 2019-11-21 09:50:24 [315.242837 TCPC p1 init ready] 2019-11-21 09:50:24 [315.243229 C1: DRPAutoToggle] 2019-11-21 09:50:24 [315.246471 C1: Unattached.SNK] 2019-11-21 09:50:24 [315.252504 C1: DRPAutoToggle] 2019-11-21 09:50:24 [315.362878 C1: LowPowerMode] 2019-11-21 09:50:24 [315.363314 TCPC p1 Enter Low Power Mode] Change-Id: I7e853d05e0ece1f6b3031f17a18fcbf0d9a15a51 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904974 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: add enter_low_power_mode for retimer muxDenis Brockus2019-11-213-6/+62
| | | | | | | | | | BUG=b:139428185 BRANCH=none TEST=verify mode is set correctly when switching devices Change-Id: I3e40e0321cb1026180b7edc0bfe99439c13acafb Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1922062
* TCPMv1: Improve jitter based collision avoidanceAseda Aboagye2019-11-211-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | For the holdoff timer, we were using the system timestamp as a source of adding jitter. However, it seems that there are certain cases that can cause a periodic collision with the jitter only varying by ~1-2ms. This leads to many repeated collisions until the jitter slides just out of the collision window. This commit changes the jitter calculation to use more of the bits that are changing to reduce the number of collisions. BUG=b:144676183, chromium:925618 BRANCH=hatch,atlas,nocturne,grunt,octopus,rammus,kukui TEST=Flash kohaku, plug some peripherals known for collisions, verify that if a collision is encountered, it's only encountered once (no cycles). TEST=Add debugging prints for the jitter, verify that the jitter is varied and appears non-deterministic. Change-Id: I6c27880551dd35b78993f7130d1ce4eb81aa10ef Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1922751 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* volteer: disable CONFIG_BRINGUPKeith Short2019-11-212-6/+5
| | | | | | | | | | | | | | | | Disable CONFIG_BRINGUP option now that the AP power up sequence is working. Also change the default console mask to disable CC_HOSTCMD, which is flooded with motion sense requests (0x60) from the kernel. BUG=b:142409811 BRANCH=none TEST=make buildall TEST=verify Volteer boots to OS automatically. Change-Id: I58f850188ca3981373af06369eb70c5887c7da31 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919402 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* testing: remove incorrect testing assertJett Rink2019-11-211-1/+7
| | | | | | | | | | | | | | | | | When we go through the suspend code path, we disabled RX monitoring, and we have done that for a 4+ years. We have not had a unit test for that ever. One is come that needs this BRANCH=none BUG=b:144369187 TEST=See that disabling RX in set_state no longer causes assertion failures in tests that it shouldn't. Change-Id: Iab4b44d3f5fdd1fe8657b23ac59df247a384ee32 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925667 Tested-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* cleanup: fixing warnings and formattingJett Rink2019-11-212-2/+2
| | | | | | | | | | | | BRANCH=none BUG=none TEST=builds Change-Id: Idf4b7363ce08a638fcca3407355c8f232100496d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1924786 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org>
* cr50: update ownersVadim Sukhomlinov2019-11-211-0/+1
| | | | | | | | | | | | | | | | | Updated cr50 owners to reflect current status. BUG=none TEST=none BRANCH=cr50 Change-Id: Iac77303a0192af3a40fda598392cbd774f5f3270 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1924781 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* charger/rt946x: fix mt6370 IEOC inaccuracyYilun Lin2019-11-211-8/+63
| | | | | | | | | | | | | | | | mt6370's IEOC is inaccurate when charging current < 900mA; the power path only partially turned on under such situation. Hence, we have to raise the IEOC setting if the current is under 900mA to compensate the IEOC original setting. BUG=b:144532905 BRANCH=kukui TEST=ensure IEOC is raised when Ichg < 900mA. Change-Id: I9f1575bb707bc91e428c06a93c4682dde22d90fc Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1924167 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* ish: Use lsm6dsm polling mode on tgl rvp platformLeifu Zhao2019-11-211-16/+0
| | | | | | | | | | | | | | | | | Need to use polling mode for lsm6dsm on tgl rvp. BUG=b:141519691 BRANCH=none TEST=tested on tgl rvp Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I1161e0c38c81f8205e28ae2428224a9e6552e820 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1916680 Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* driver: lsm6dsm: Allow building without CONFIG_ACCEL_FIFOYuval Peress2019-11-2113-48/+79
| | | | | | | | | | | | | | | | This change refactors the lsm6dsm to allow building without the use of the FIFO or sensor interrupts. BUG=None BRANCH=None TEST=make buildall Change-Id: I5b338d81061f25fd1c8209b4555f63ea4d8b2dbc Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1916679 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* cr50: drop unused definition of CONFIG_FLASH_READOUT_PROTECTIONVadim Bendebury2019-11-211-1/+0
| | | | | | | | | | | | | | | No code depending on this define is relevant for Cr50, it was added to this board file by mistake. BRANCH=cr50, cr50-mp BUG=none TEST=size of the generated Cr50 image remains the same before and after this patch. Change-Id: I31d5bffdc9b5109f1d4bb929dea66834a3bfa660 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925681 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: switch to new dev keyVadim Bendebury2019-11-213-9/+9
| | | | | | | | | | | | | | | The new RO has a new dev key, modify the dev manifest to match the new RO expectations. BUG=b:74100307 BRANCH=cr50, cr50-mp TEST=built a node locked image for ro 0.0.11 and observed it boot and run Change-Id: I3ce9ca8d23be6b2d959d4457ea6d08afa05376ac Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1866173 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: remove flash nonvolatile counter spaceVadim Bendebury2019-11-214-23/+9
| | | | | | | | | | | | | | Counter implementation has been moved to the AP, no need to keep space for it in the flash. BUG=b:65253310 BRANCH=cr50, cr50-mp TEST=generated image uses 2048 bytes less than before this patch. Change-Id: I8225e9923932ce06ca0a4333c06508cf7d7c70d8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753677 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: Add support for ACVP tests of HMAC SHA-256 DRBGVadim Sukhomlinov2019-11-215-6/+239
| | | | | | | | | | | | | | | | | | | HMAC DRBG is used for U2F key generation, and as such is subject for ACVP tests. Expose DRBG Init, Generate and Seed commands for automated testing with externally provided test vectors. BUG=b:138578319 BRANCH=cr50 TEST=make CRYPTO_TEST=1 BOARD=cr50 -j && test/tpm_test/tpmtest.py Change-Id: I50a6750864d3cd9a304a9b8a8524ef29cec04410 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1912662 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* kappa: fix charge/discharge control setting orderDevin Lu2019-11-211-3/+3
| | | | | | | | | | | | | Clone form CL:1916160 BUG=none BRANCH=none TEST=make BOARD=kappa Change-Id: I18905f7ace402debf1fad93e72b8a86ee27d1f50 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918986 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* volteer: enable EC controlled fanKeith Short2019-11-212-0/+18
| | | | | | | | | | | | | | | | Enable simple GPIO control of the fan. Still need to add PWM controls once a smart fan is available. BUG=b:140582490 BRANCH=none TEST=make buildall TEST=verify fan turns on when exiting G3 and turns off before entering G3. Change-Id: I3ec5b36fd5c7ca607f03efa9a76f8dc2efacbb22 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1924503 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* volteer: Add USB-C policyVijay Hiremath2019-11-215-12/+194
| | | | | | | | | | | BUG=b:140578872 BRANCH=none TEST=USB2.0 & USB3.0 device detected over Type-C port 0 Change-Id: I44790aac3543589c32dcd60f84e4e67d5d76cdab Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1922752 Reviewed-by: Keith Short <keithshort@chromium.org>
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