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* Volteer: move USB product ID to baseboardstabilize-12859.B-masterKeith Short2020-01-242-8/+7
| | | | | | | | | | | | | | | The selected ID has been properly allocated in http://google3/hardware/standards/usb/ BUG=b:140578872 BRANCH=none TEST=make buildall Change-Id: I718050fbf6db2a205cd0d76796ab57e72606b28b Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018464 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Trogdor: Deprecate AP_RST_REQ handling logicWai-Hong Tam2020-01-242-15/+1
| | | | | | | | | | | | | | This logic is no longer used. Should be deprecated. BRANCH=None BUG=b:148238496 TEST=Assert the AP_RST_REQ signal, no reboot happens. Change-Id: Icade7ede9a8fb48313123ad59b5a36a8aa1a71bf Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018056 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* pi3usb3x532: Pack i2c port in port_addrAseda Aboagye2020-01-248-12/+27
| | | | | | | | | | | | | | | | | | | | | The PI3USB3X532 driver in the EC assumes that all superspeed muxes are on the same i2c bus, I2C_PORT_USB_MUX. However, that may not be true for some boards. This commit utilizes the MUX_PORT(...) macro to determine the i2c port to use from the usb_mux table. The boards that use this driver have been updated to pack the i2c port in the port_addr member. There should be no functional changes to those boards. BUG=b:147689445 BRANCH=None TEST=`make -j buildall` Change-Id: If6460b84a5e39610d658f06a42ca1db0bd4da048 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013658 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* waddledoo: don't enable pull-ups with low-voltage modeDavid Schneider2020-01-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | It is not valid on the NPCX7 to simultaneously use low-voltage mode and enable the pull-up, so pull-ups were being ignored. This caused spurious volume up and volume down button presses. Prochot is similarly misconfigured and really should be an ADC input, but for now just remove the pull-up. These changes have been updated on the EC pinout table as well. BUG=None BRANCH=None TEST=press buttons on waddledoo Change-Id: I8fd6e13d0e0ca79dbb777563443da0858ac62187 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018033 Tested-by: David Schneider <dnschneid@chromium.org> Auto-Submit: David Schneider <dnschneid@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* TCPMv1/v2: Move EC_CMD_USB_PD_DEV_INFO host command to common fileVijay Hiremath2020-01-245-47/+59
| | | | | | | | | | | BUG=b:142911453 BRANCH=none TEST=make buildall -j Change-Id: If9d902ef77da7d56a123c0c78b1ebbcd0d95bc3b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2008301 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move EC_CMD_USB_PD_SET_AMODE host command to common fileVijay Hiremath2020-01-243-67/+41
| | | | | | | | | | | | BUG=b:142911453 BRANCH=none TEST=make buildall -j Change-Id: Id5cb4475a4bdf37947a6b1484441dadb7aa2d214 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2008300 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move EC_CMD_PD_CHIP_INFO host command to common fileVijay Hiremath2020-01-244-62/+35
| | | | | | | | | | | BUG=b:142911453 BRANCH=none TEST=make buildall -j Change-Id: Ia858db061811c58a14b2525d17d6abdc35ea6fa7 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2008299 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move EC_CMD_USB_PD_RW_HASH_ENTRY host command to common fileVijay Hiremath2020-01-244-82/+47
| | | | | | | | | | | BUG=b:142911453 BRANCH=none TEST=make buildall -j Change-Id: Ibcf7b23c9b4c166a59c00b4805d1fbad5e79e5f1 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2008298 Reviewed-by: Keith Short <keithshort@chromium.org>
* volteer: use CBI for board ID and DB configCaveh Jalali2020-01-242-0/+72
| | | | | | | | | | | | | | | | | | | | | This adds support for reading the board ID and daughterboard ID from CBI. The FW_CONFIG CBI tag is used to determine which daughterboard is attached. Current boards do not have the FW_CONFIG tag set up, so we'll default to the USB4 board type when this tag is not found to preserve current behavior. BRANCH=none BUG=b:148117843 TEST=verified volteer can read daughterboard type from CBI Change-Id: Ie2f808a794e668f52497f041738e724e848016de Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013655 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* uart: Add uart_put_rawDaisuke Nojiri2020-01-242-6/+33
| | | | | | | | | | | | | | | | | | uart_put_raw sends byte stream without translating '\n' to '\r\n'. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/119329144,chromium:998135 BRANCH=none TEST=Boot Nami Change-Id: Iaac4244d45231bf5904d917f2f446f87e8e10c50 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757273 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* ioexpander: fix out-of-bounds access in last_val_changedMichael Auchter2020-01-241-1/+5
| | | | | | | | | | | | | | | | | | | | | Commit 9f392b0d6 gave unique values to IO signals implemented on an IO expander, but last_val_changed was not updated to remove the newly added offset before indexing the array that tracks changes between `ioexget` invocations. Remove the offset and add an assertion to ensure the array index is valid. BUG=None BRANCH=None TEST=`ioexget` doesn't assert or stomp on memory Signed-off-by: Michael Auchter <michael.auchter@ni.com> Change-Id: If06d300abaeed2905939d9724a1152d4da10035b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2012448 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* util: revise uart_stress_tester for python3Namyoon Woo2020-01-241-29/+31
| | | | | | | | | | | | | | | | | | | Convert the code for python3, and fixed some pylint errors. BUG=none BRANCH=none TEST=manually ran it on Fleex. 'uart_stress_tester.py -d -t 300 /dev/ttyUSB2' Also ran pylint. 'pylint --rcfile /mnt/host/source/chromite/pylintrc uart_stress_tester.py' Change-Id: Ie983eff06e0757af14ebc16878ca892fc1f629a5 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015351 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* PD: Add support for new host command, EC_CMD_GET_PD_PORT_CAPSTim Wawrzynczak2020-01-243-0/+125
| | | | | | | | | | | | | | | | | This host command is used to report the static capabilities of a USB-PD port, including its power role, Try power role, data role, and its physical port location on the device. This will be used to expose the information in ACPI, via the EC object. BUG=b:146506369 BRANCH=none TEST=Along with coreboot changes, dump the SSDT, and verify that the object looks as expected. Change-Id: Ie1975a8b391eba6e924b0552ba9b0973fd2c63f3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015825 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* driver: lis2mdl: Define LIS2MDL_CAL even when CONFIG_MAG_CALIBRATE is notGwendal Grignou2020-01-242-8/+17
| | | | | | | | | | | | | | | | | mag_cal_t holds offset information for the sensor, even when online calibration is not defined. Allow driver to work with online calibration disabled (it could be set from the host). BUG=none BRANCH=none TEST=using nucleo-f072rb_iks01a2, check magnetometer is working with or without CONFIG_MAG_CALIBRATE enabled. Change-Id: I2e259f53c620c593b516a12d6dff47dfbadb26c8 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1993584 Reviewed-by: Yuval Peress <peress@chromium.org>
* docs/fingerprint: Add details on using fingerprint with Chrome OS buildTom Hughes2020-01-242-1/+97
| | | | | | | | | | | | BRANCH=none BUG=none TEST=view in gitiles Change-Id: Icedacbe7897d8aaf441e7d76be50e440f46c5a54 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2017576 Commit-Queue: Craig Hesling <hesling@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* zork: PS8802/PS8818 dynamic detection cleanupDenis Brockus2020-01-237-86/+239
| | | | | | | | | | | | | | | | | | | | | | | | | Changed the method for detection to a non-destructive mechanism so it could be called from any of the interfaces. Added in switching to direct calling the detected driver once the hardware has been determined. The 8802 is the main mux when it is present and the fp5 mux should only select the lanes to send. Flip should not be sent to the FP5. It is a specialized form of a secondary MUX and currently being placed in as a retimer. In the future the retimers will all become MUXes and they will chain... just not today. BUG=b:147428570 BRANCH=none TEST=verify USB-C1 device with AP running Change-Id: I6b0eedd1dfcc91c3114f8dc481f5ca2841eb9e85 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014311 Reviewed-by: Edward Hill <ecgh@chromium.org>
* volteer: enable PD_CONTROLCaveh Jalali2020-01-231-0/+2
| | | | | | | | | | | | BRANCH=none BUG=b:147459088 TEST=successfully updated to firmware 0x03 Change-Id: I9dddb9d68714f8befd1e28d837daf2e8041cf298 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013657 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com>
* ec3po: Add OWNERS file.Matthew Blecker2020-01-231-0/+3
| | | | | | | | | | | | | | This deliberately inherits from parent dirs, so this may be a no-op at the moment. BRANCH=none BUG=none TEST=none Change-Id: I13e15af246a47e9e740f5ad07de86764234767b4 Signed-off-by: Matthew Blecker <matthewb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015350 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* puff: correctly re-init charge ports after sysjumpPeter Marheine2020-01-231-14/+28
| | | | | | | | | | | | | | | | | | | | | When the AP does SW sync with the EC, it can make the EC reset (sysjump) while the AP is on. This would cause us to incorrectly forget what charge port was active because we didn't allow any changes while the AP was on, even if the EC didn't have a current state. Change port selection policy to allow changes while the AP is on, provided no port is currently selected and the request agrees with the state of the hardware. BUG=b:148036160 TEST=chgsup now remains unchanged after sysjump with the AP on, port changes remain forbidden. BRANCH=None Change-Id: Ibf1d4de2298a9a5e631af457d8618cb0accd5e08 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014561 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* lick: Cannot power on DUT on AC only mode.Hash.Hung2020-01-231-1/+0
| | | | | | | | | | | | | | | | | Remove unnecessary define of 'battert_panasonic' from board.h. BUG=b:147192366 TEST=cros_workon-octopus start chromeos-ec emerge-octopus chromeos-ec BRANCH=master BOARD=lick Change-Id: I6394075ab03d637c32184fe4d8ed8dc0946a495f Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014560 Reviewed-by: Henry Sun <henrysun@google.com> Commit-Queue: Henry Sun <henrysun@google.com> Tested-by: Henry Sun <henrysun@google.com>
* puff ec: Add EVT GPIO definitions.Andrew McRae2020-01-232-7/+7
| | | | | | | | | | | | | | | Update the puff EC GPIO definitions to include EVT changes. BRANCH=none BUG=b:147983217 TEST=Ran on puff. Change-Id: I9fa911881dfbd705ee8e264d7f55576b45b80893 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014003 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org>
* driver/opt3100: Set min/max frequency that match the driverGwendal Grignou2020-01-232-5/+8
| | | | | | | | | | | | | | Given we set integration time at 800ms, the host must be aware to not set an ODR over 1Hz. BUG=chromium:615059 BRANCH=nocturne TEST=Check new max_frequency is indeed 1Hz on nocturne. Change-Id: I44252073f59e00cdf4d13b4fa6d88448537c168e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991857 Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* PS8805: Do not enable and disable DCI registersWai-Hong Tam2020-01-231-17/+3
| | | | | | | | | | | | | | | | | | PS8805 is not like PS8751, which needs to rewrite the TCPC reg A0 bit 0 to enable the DCI registers. The DCI registers are always accessible. Also there is a bug on firmware, like 0x8, 0xC, 0xD, that rewriting the reg A0 bit 0 to 1 will make the TCPC I2C not accessible. BRANCH=None BUG=b:147772854 TEST=Verified on Trogdor, fw 0xC, 0xD, and 0xF, the TCPC I2C is accessible. Change-Id: Ie554d2b4022397801423fb3670305bf536b2cc20 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015641 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* Trogdor: Implement board_set_tcpc_power_modeWai-Hong Tam2020-01-232-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | The board_set_tcpc_power_mode() function hasn't been defined. When doing TCPC software sync, AP to ask EC to suspend the TCPC chip, and then resume it when done. Missing the board_set_tcpc_power_mode() function made the TCPC chip can't resume back. BRANCH=None BUG=b:146652805 TEST=Executed the TCPC software sync, verified the TCPC is back, i.e. 2019-12-20 15:33:27 > C0 st1 SUSPENDED 2019-12-20 15:33:30 [286.977749 TCPC p0 suspended!] 2019-12-20 15:34:14 C0 st2 SNK_DISCONNECTED 2019-12-20 15:34:14 [330.333053 Resetting TCPCs...] 2019-12-20 15:34:14 [330.382545 C0 FAULT 0x00 detected] 2019-12-20 15:34:14 [330.383235 C0 FAULT 0x00 handled] 2019-12-20 15:34:14 [330.387583 TCPC p0 resumed!] Without this CL, an error was reported and the TCPC chip still in suspend. 2019-12-20 14:57:52 C0 st2 SNK_DISCONNECTED 2019-12-20 14:57:52 [546.264649 TCPC p0 restart failed!] Change-Id: I6cee0b7a6d24b9b6ab40f5259a659ca234319990 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1979611 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* PS8805: Add the delay between releasing reset and the first I2C readWai-Hong Tam2020-01-233-1/+8
| | | | | | | | | | | | | | | The PS8805 needs time for firmware init. Before the firmware initiated, I2C read may return wrong values. Parade suggests adding a 10ms delay. BRANCH=None BUG=b:147767696 TEST=Built Trogdor and Nocturne without error. Verified Trogdor TCPC reset correctly, with some other CLs too. Change-Id: I9f67612792f72d6075cbf93a516494c1af592259 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015640 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* sdm845, sc7180: Prioritize the power_request for checking power on and offWai-Hong Tam2020-01-232-32/+36
| | | | | | | | | | | | | | | When checking the event for power on or power off, should check the power_request first such that this request can be cleared; otherwise, the request still presents and may result a loop. BRANCH=None BUG=b:145901185 TEST=Toggle the WARM_RESET_L signal and no loop happens. Change-Id: Ifb79107d40b9a4c8e71a459ccd3063a0cacede17 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1963378 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* drallion: Set the rotation matrix for base accelMathew King2020-01-221-1/+8
| | | | | | | | | | | | | | | | | On Drallion the LNG2DM accelerometer is rotated 270 degrees from the same sensor on Arcada. Change the rotation matrix for the sensor to account for this difference. BUG=b:147715895 TEST=run 'ectool --name=cros_ish motionsense' with lid at 180 degrees. Verify that base and lid are in sync at various rotations. BRANCH=none Change-Id: Icc997ae864fb47fef398ca140e96719b39ec054e Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013649 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Mike Wiitala <mwiitala@google.com>
* jinlon: enable OTI502 IR temperature sensorDevin Lu2020-01-224-0/+14
| | | | | | | | | | | BUG=b:141259174 BRANCH=hatch TEST=ec console "temps" to check OTI502 IR temperature sensor can be read. Change-Id: I03254e850809d6968b59ca9d0fbcc45443f097af Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1933789 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* docs/fingerprint: Update chromeos-config and flashing instructionsTom Hughes2020-01-222-9/+32
| | | | | | | | | | | | BRANCH=none BUG=none TEST=view in gitiles Change-Id: Ibc97efb7a1746cb6cbb5422104d72be8b708681e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015141 Commit-Queue: Craig Hesling <hesling@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* driver/temp_sensor: add support OTI502 temperature sensorDevin Lu2020-01-224-0/+96
| | | | | | | | | | | | | | | This patch adds OTI502 IR temperature sensor driver. OT502 has two temperture information which is ambient and object temperature. ambient is chip temperature and object is IR temperature. BUG=b:140817732 BRANCH=none TEST=none Change-Id: Ia49e0c7962eaa446f788a9104204c6dbe18ee97c Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925795 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* waddledoo: Enable TCPCI Rev2 v1.0 for TCPCsAseda Aboagye2020-01-221-10/+6
| | | | | | | | | | | | | | | | | | | The RAA489000 TCPCs that waddledoo is using are a TCPCI Rev2 TCPC. Unfortunately, there seems to be some problems with the TCPCI Rev1 mode, so enable TCPCI Rev2 mode instead which seems to work with the newly added TCPCI Rev2 support. BUG=b:147316570 BRANCH=None TEST=Build and flash waddledoo, verify that TCPC can receive and transmit PD messages. Change-Id: If8fb434d865bf5a6f0439707581ca92cb3e7731d Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006711 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* driver/tcpci: Add support for TCPCI Rev2 v1.0Aseda Aboagye2020-01-224-15/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TCPCI Revision 2.0 made a couple major changes compared to the 1.0 revision. One of these changes was that the method in transmitting and receiving messages from the TCPC had changed. The receive buffer register is now comprised of three sets of registers: READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE, and RX_BUF_BYTE_x. These registers can only be accessed by reading at a common register address 30h. Similarly, the transmit buffer register holds the I2C_WRITE_BYTE_COUNT and the portion of the SOP* USB PD message payload (including the header) in TX_BUF_BYTE_x. TX_BUF_BYTE_x is "hidden" and can only be accessed by writing to register address 51h. This commit adds support for TCPCI Rev2 v1.0 by adding the new mechanisms for transmitting and receiving messages. A flag was introduced to enable the TCPCI Rev2 handling, TCPC_FLAGS_TCPCI_V2_0. A board should set this flag in their tcpc_config structs for those TCPCI-compliant TCPCs which use TCPCI Rev2. BUG=b:147716486 BRANCH=None TEST=Enable TCPCI Rev2.0 on waddledoo, verify that PD messages are able to be received and transmitted. Change-Id: Ie0117adf56c95f85f9c67ed678cf1e367f83eb7e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006710 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* power/cometlake-discrete: stub out espi reset handlerPeter Marheine2020-01-221-11/+1
| | | | | | | | | | | | | | | | | This appears to be an artifact left over from skylake (where the EC can't turn off the AP without also turning itself off) that was copied into cometlake and from there into cometlake-discrete. Since we never mess with the power button like skylake does, there's no reason to include that handling. TEST=no effect on puff's behavior BUG=None BRANCH=None Change-Id: Id383e5b7b28e7cca7c5f5e1fb0d8840a1c15bffa Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014002 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* power/cometlake-discrete: correctly update the SM on forced shutdownPeter Marheine2020-01-221-1/+11
| | | | | | | | | | | | | | | | | | Without this, apshutdown on the EC console turns off the system but it thinks it's in S5 when it's actually in G3 so it doesn't respond to power button presses to turn back on. Make the steady-state S5 handling check whether the system is actually in S5 and transition down as appropriate. TEST=puff goes directly to G3 on apshutdown, but not when shutting down gracefully. BUG=b:147461413 BRANCH=None Change-Id: Ic216b5e908b8a77d8d016f60dd8b0de832cf301e Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014000 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* servo: Adds logging of panic info to USB consoleBrian J. Nemec2020-01-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | There is a console command to log the panic info data to the UART console. This change modifies it so after printing data to UART, it will also pass it to the USB console so the data can be easily logged by servod. BUG=chromium:1018008 BRANCH=servo TEST=Manual testing on Sweetberry, ServoV4, and ServoMicro 1) Unplug device to clean panic info, plug device in to USB 2) Request 'panicinfo' from the console interface 3) Response 'No saved panic data available.' 4) Trigger crash using commands like 'sysjump 0x100' or 'crash assert' 5) Reconnect console 6) Request 'panicinfo'. Fault registers are returned over USB console and UART console. The values match the correct addresses which is easily verified in the sysjump case. Change-Id: I5b0bb102296f5fcc967519bb3a59af49644e6f4b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880579 Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* it83xx/adc: adc control pin order changes for it83202BxRuibin Chang2020-01-222-0/+19
| | | | | | | | | | | | | | | | Add configuration for changing adc control pin order on chip it83202Bx. BUG=none BRANCH=none TEST=ADC16 of PD port2 can read correct Vbus value. Change-Id: I9a7f81bf3cb1ac74a5f07ce817d03f5ab0569d17 Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009539 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* Cleanup: Add chip support pd physical port count configurationRuibin Chang2020-01-226-4/+9
| | | | | | | | | | | | | | | Add chip support pd physical port count configuration. BUG=none BRANCH=none TEST=build all -j Change-Id: Ic473e53af44b5360aad6d2db74cf09ce5a3fa3e8 Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009537 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* it83xx/flash: verify flash from ILMDino Li2020-01-221-0/+9
| | | | | | | | | | | | | | | | Because contents of section 0 ~ 0x1000 of flash are only mapped to ILM on it8xxx2 series (risc-v core). So we changed to verify flash from ILM to fix erase/write the section error. BUG=none BRANCH=none TEST=erase/write section 0 ~ 0x1000 are successful on IT83202. Change-Id: I34165ce9cb04babc8c55ddcc64549df1e65c4ff9 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982296 Reviewed-by: Jett Rink <jettrink@chromium.org>
* riscv-rv32i: Add sqrtf functionDino Li2020-01-223-1/+33
| | | | | | | | | | | | | | | | | | The int_sqrtf() requires this function if we enable FPU. BRANCH=none BUG=none TEST=manual testing on console command: sqrtf(1.23) = 1.10 sqrtf(0.45) = 0.67 sqrtf(0) = 0 Change-Id: I354453674559ff2e1b956c9dba47baa493332871 Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982298 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw>
* core/riscv-rv32i: enable software ctzDino Li2020-01-221-0/+5
| | | | | | | | | | | | | | | Because we don't support risc-v bit manipulation extension (CLZ/CTZ instructions) yet, so we enable the software implementation to fix build error while __ctzsi2 is called. BUG=none BRANCH=none TEST=no build error. Change-Id: If916010b9004f95aa4ccfd533be9539aff4c3f50 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982295 Reviewed-by: Jett Rink <jettrink@chromium.org>
* power/cometlake-discrete: don't treat orderly shutdown as power failurePeter Marheine2020-01-221-6/+12
| | | | | | | | | | | | | | | | | | | | | | The common Intel code looks at IN_PGOOD_ALL_CORE in steady-state S3 and S0, forcing a shutdown if any part of it goes away. By including the DRAM rails, we make it think there's a power failure during orderly shutdown because the PCH turns off the things it controls before the EC notices it's transitioning (they're not in lockstep, the PCH goes as fast as it wants and the EC must catch up). This means the only time we can actually monitor the DRAM rails is when bringing them up, since the PCH may turn them off. BUG=b:147461413 TEST=puff now responds to power button press in S5 after shutdown, and does not log power failure. BRANCH=None Change-Id: Ia18c06ea2eec54c4ff0ccad3c91ba29547014f9c Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009541 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* kohaku: Define CONFIG_MKBP_EVENT_WAKEUP_MASK as 0Tim Wawrzynczak2020-01-221-0/+3
| | | | | | | | | | | | | | | | | | | This allows the AP to set MKBP wake masks, which will enable the EC to wake the system from suspend states. The default is 0, which means that the AP gets to choose which events will wake it from suspend. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=Verify 'ectool mkbpwakemask set event 0x400' succeeds. Also verify with corresponding coreboot CL that the system can wake from suspend when a DP-capable monitor is plugged in. Change-Id: Ife726f341770e6c9cea2ffe39abc9d8ed38b0cbb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013640 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
* TBT: Allow entering TBT mode for passive cables without SVIDVijay Hiremath2020-01-221-10/+32
| | | | | | | | | | | | | | | | | | | Passive cables without Intel SVID can nack to the Discover SVID SOP'. For these cables, limit the speed of TBT device to cables speed or TBT Passive Gen2 cable speed whichever is lowest. Ref: USB Type-C Cable and Connector Specification 2.0 Figure F-1 TBT3 Discovery Flow BUG=b:147732811 BRANCH=none TEST=Manually tested on Volteer. Using Rev2 Gen1 cable device can enter into TBT mode Change-Id: I654056f434501898e60152c52f6d85f81ae35a78 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003506 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* dedede: Add z-state supportAseda Aboagye2020-01-213-3/+19
| | | | | | | | | | | | | | | | | | | | | | Dedede has support for the new low power "Z-state". In this state. the EC and H1 are unpowered, but power will be restored to the EC once one of the wakeup events occurs. These events are ACOK, lid open, and a power button press. This commit simply enables the Z-state when the EC hibernates. BUG=b:147819424 BRANCH=None TEST=build and flash waddledoo, enter `hibernate`, verify that EC power is turned off and can be restored by pressing the power button or plugging in a charger. Change-Id: I4f93efd0632f457354f4bf6bf0274b19a9cd799c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006215 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* waddledoo: Add LED supportAseda Aboagye2020-01-215-1/+98
| | | | | | | | | | | | | | | | | This commit adds LED support to waddledoo utilizing the common PWM LED framework. Waddledoo has a single bi-color PWM LED with amber and white channels. BUG=b:147702767 BRANCH=None TEST=Build and flash on waddledoo, verify that LEDs are working. Change-Id: Ie870a6df194a9e1ccd6b91a96c6e95a390353a8a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2001941 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* led_pwm: Cast PWM_LED_NO_CHANNEL when comparingAseda Aboagye2020-01-211-6/+6
| | | | | | | | | | | | | | | | | Without this change, sometimes the comparison to PWM_LED_NO_CHANNEL would fail causing a panic by attempting to use a non-existent PWM channel. BUG=None BRANCH=None TEST=build and flash waddledoo, verify that EC doesn't panic anymore. Change-Id: I0d496eaea6d7bdbc7c655796a4df12a0f9f7cf0b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2004268 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* waddledoo: Add keyboard supportAseda Aboagye2020-01-217-8/+70
| | | | | | | | | | | | | | | | | This commit adds keyboard support to waddledoo using the default keyboard config. BUG=b:147453459 BRANCH=None TEST=Flash waddledoo, connect keyboard, `ksstate on` verify that each key is registered. Change-Id: I0a10eeb3080170c731f90317d4a0b3c0fbfb9243 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2001940 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* waddledoo: Add Type-C, PD, and charging supportAseda Aboagye2020-01-218-4/+490
| | | | | | | | | | | | | | | | | | | | This commit adds USB Type-C, Power Delivery and charging support to waddledoo. Waddledoo is using the new TCPMv2, low power mode has been disabled for the time being while we sort out issues with the TCPC. Currently in this state, we cannot actually receive any PD messages, but the PD task is running. BUG=b:147257992 BRANCH=None TEST=Build and flash on waddledoo, verify that we can detect Type-C chargers, and that it can charge a battery. Change-Id: Id30218ef685ed27a934bae3a580f47754f659ac6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2001127 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* tcpmv2: Fix issues with low power mode disabledAseda Aboagye2020-01-211-9/+9
| | | | | | | | | | | | | | | | | With low power mode disabled, TCPMv2 was failing to build. Making these changes allowed it to build. BUG=None BRANCH=None TEST=`make -j BOARD=waddledoo` Change-Id: I5bed5d7ca7ceab77d5b764e97853c1d6bc51eb3d Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2001128 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* chip/stm32: Stop timers and watchdogs on STM32F4 when debuggingCraig Hesling2020-01-212-1/+10
| | | | | | | | | | | | | BRANCH=none BUG=none TEST=make buildall -j TEST=Attach SWD to dragonclaw v0.2 Change-Id: I7bd5741c4862bb2f134ae3067715d2301a18ea78 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1962974 Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Tom Hughes <tomhughes@chromium.org>
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