| Commit message (Collapse) | Author | Age | Files | Lines |
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BUG=none
BRANCH=cr50
TEST=git-clang-format
Signed-off-by: Louis Collard <louiscollard@chromium.org>
Change-Id: I2618d7b6d731200e605e207bc7343930e4701293
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2111912
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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To avoid some sort of race in private-cr52 endpoint initialization,
which results in a reboot loop.
Calling usb_console_enable() in HOOK_LAST instead appears stable,
at cost of missing some early console output.
While at it, reduce some SRAM usage and improve legibility
by moving to bool from int.
Strictly opt-in; behavior unchanged for existing code.
BUG=chromium:1063240
BRANCH=cr50
TEST=make buildall; cr52 build w/ usb_console now enumerates w/o resets.
Signed-off-by: mschilder@google.com
Change-Id: I352edb4c045df401cb99573da5765b88deb45d0d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2111450
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Commit-Queue: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Auto-Submit: Marius Schilder <mschilder@chromium.org>
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While working on a different issue it was discovered that
$(out)/RW/board/cr50/board.o is rebuilt every time make is ran, even
if there has been no changes. Further investigation has shown that the
problem is that $(out)/RW/board/cr50/board.o depends on
$(out)/ec_version.h, which is not rebuilt unless something changed,
but is declared .PHONY in Makefile.rules
Turns out the declaration is supposed to be conditional on actual
change in ec_version.h, but the condition is always True. This in turn
was due to the fact that when checking if there is a change, some
relevant make variables (CR50_DEV, CR50_SQA, and CRYPTO_TEST) were not
set when invoking ./util/getversion.sh.
When the variables are set, ec_version.h is not decalred PHONY, no
unnecessary compilation is invoked.
BUG=none
TEST=repetitive running of
make BOARD=cr50 CR50_DEV=1 build/cr50/RW/board/cr50/board.o
does not trigger recompilation of board.o any more
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Ibe75bcda9a774e748f973d85841bbde9c29fd104
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2108920
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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This is the cr50_stab branch, pretty much all patches will have to be
cherry picked into cr50-prepvt and cr50-mp, no need to add noise to
patch descriptions.
BUG=none
TEST='repo upload' does not complain about missing BRANCH= in the
patch descriptions.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Iaac7c4576317025c750872fb6b9c56e64c82cc15
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2108719
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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This path removes CONFIG_USB_HID_KEYBOARD support and
CONFIG_USB_UPDATE support because they are not used in any cr5X
board configuration.
Ths patch also removes some subsidiary configs as upload hook script
guides.
> CONFIG_USB_PAIRING
> CONFIG_TOUCHPAD_VIRTUAL_OFF
> CONFIG_USB_CONSOLE_READ
BUG=none
BRANCH=cr50
TEST=make buildall
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: Iafa553fdf58772744b1d9a5c7f5460f42264f468
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2103045
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
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This patch reprioritizes ec_comm_init() and ec_efs_init() so that
they won't be executed prior to board_init(), which executes
nvmem_init().
BUG=b:151187315
BRANCH=cr50
TEST=let cr50 reboot a few times, and checked the console message
and the ec_comm command output that Kernel secdata was reloaded
without error. Swapped cr50 image from normal to dev, vice versa,
and repeated the rebooting.
[Reset cause: hard]
[0.003799 Inits done]
strap pin readings: a1:2 a9:3 a6:0 a12:0
[0.005893 Valid strap: 0xe properties: 0xa00041]
[0.007991 init_jittery_clock_locking_optional: run level high, ...
[0.045539 init took 29953]
[0.051185 tpm_rst_asserted]
[0.052074 EC-COMM: Initializtion]
Console is enabled; type HELP for help.
...
> ec_comm
...
response : 0xec00
ec_hash : LOADED
secdata_error_code : 0x00000000
>
Change-Id: Ia695896986374ac9d23ac111fe0086ec6a13923e
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2093102
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Two new options for 'ec_comm' are for test usage only.
- ec_comm corrupt: it corrupts the ECRW hash in ec_comm module.
Hash corruption will cause EC-FW verification failure. It can be
useful to check how AP firmware performs software sync on this
failure.
- ec_comm reload: it forces Cr50 to reload ECRW hash from tpm nvmem.
This is to restore the EC EFS2 status in Cr50 from corrupted status.
BUG=b:150650877
BRANCH=cr50
TEST=manually ran 'ec_comm corrupt' or 'ec_comm reload' with dev image.
Checked cr50 normal image refuses those command lines.
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: Ib4aa9532132e1ee786e623bd658a68987e4681dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094781
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This patch adds a test case for EC-EFS functions.
BUG=b:150650877
BRANCH=cr50
TEST=make run-ec_comm
make runhosttests
make buildall -j
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: I90cdc3aa73cf8946da4cf094de5ca0adfaaa0a7c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2096338
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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usart.h doesn't need to be included in ec_comm.c.
This patch also fixes nit output format in cprints.
BUG=none
BRANCH=cr50
TEST=make run-ec_comm
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: Icadf0d860cee8d3cf882cdb4571aaa2bc325adf9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094751
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This patch allows the repeating SET_BOOT_MODE command except one case
that attempts to change the boot mode from NO_BOOT to NORMAL.
Cr50 resets EC on those violating commands.
This patch adds error handling for an unknown boot mode parameter.
BUG=none
BRANCH=cr50
TEST=ran unittest, 'make run-ec_comm'.
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: Ib6c97596ed9c7b7563fbe5e6497cbd668f57a474
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2096840
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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With the upcoming transition to handling console traffic in packet
mode it is very expensive to be shipping one character at a time, each
character results in sending a packet of 16 or so bytes.
This patch modifies print_build_string() such that it splits the long
build version string into manageable substrings and prints them
instead of printing one character at a time.
BRANCH=cr50, cr50-mp
BUG=b:149964350
TEST=built a Cr50 image, verified that build string is printed as
expected.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I743205932892b0f14c161ade5ea856a658fb26e6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2097444
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The extended GPIO state support command uses a lot of format elements
when trying to report properties of the GPIOs.
The upcoming source code processing scripts do not support more than
eight format elements per format string. On top of that there is no
need to even try to generate the string in case extended GPIO command
mode is supported.
Let's move generating the string with properties into the
conditionally compiled section, to make sure that it is
generated/processed only when needed, and let's use snprintf() first
to reduce the number of format elements in the following ccprintf
invocation.
BRANCH=cr50, cr50-mp
BUG=b:149964350
TEST=verified proper 'gpiog' command output when code is compiled both
with and without CONFIG_CMD_GPIO_EXTENDED
Change-Id: I0836a350d1f787c84d2079f10de3652523a8a5a9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2097442
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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This patch moves ec_comm.c and ec_efs.c from board/cr50 to common/,
so that they can be shared with other board configuration (like host).
This is to build unittest for those files.
BUG=none
BRANCH=cr50
TEST=make buildall -j
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: I67ac313054ebe4604848a176f0a42e3483957e74
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094076
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This patch changes fixes the pre-condition to check before
it processes the command, SET_BOOT_MODE. It should check if the
current boot mode is NORMAL mode, but it used to check if the input
parameter value is NORMAL mode.
BUG=none
BRANCH=cr50
TEST=make buildall -j
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: I85e0a3a1ed27a276262a7b9d3889c826cca14d19
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094075
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Add a flash_cr50 script for updating cr50. The script supports updating
through gsctool and cr50-rescue.
BUG=b:144048851
BRANCH=none
TEST=manual
python util/flash_cr50.py -i $IMAGE -p 9999 -c cr50-rescue
on octopus.
python util/flash_cr50.py -i $IMAGE -p 9999
--method=cr50_reset_odl -c cr50-rescue
python util/flash_cr50.py -i $IMAGE -c 'sudo gsctool'
python util/flash_cr50.py -i $IMAGE -s $SERIAL
Change-Id: Ibdd213446fea4cb66f77c6b7249c02914bd0712a
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907469
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit ba216cfef2a005717938b28ceab15b79406f7f3b)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092916
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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BUG=none
BRANCH=none
TEST=manual
sudo CR50_BOARD_ID="FFFF:0:10" H1_DEVIDS="${DEVID}" ./util/signer/bs
Change-Id: I54f149bf5c0248a8672514258b596455d442ef69
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088552
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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BUG=none
BRANCH=none
TEST=none
Change-Id: I63a586c946f1b69547197767753e60f3319aad90
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092211
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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gsctool -g or --getbootmode can get the current system boot mode.
BUG=b:141578322
BRANCH=cr50
TEST=ran on helios.
$ ./extra/usb_updater/gsctool --getbootmode
finding_device 18d1:5014
Found device.
found interface 3 endpoint 4, chunk_len 64
READY
-------
Boot mode = 0x00: NORMAL
$ ./extra/usb_updater/gsctool -g
finding_device 18d1:5014
Found device.
found interface 3 endpoint 4, chunk_len 64
READY
-------
Getting boot mode
Boot mode = 0x00: NORMAL
Change-Id: Id024ac94fb08b680bd5e190bc7eeb2de301b70a2
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2058128
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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By design gsctool does not update the inactive RO unless the running
RO version is lower than the version in the Cr50 image being
transferred.
With transition to the new RO version, keys and rollback map state,
there is a need to enforce that both ROs on the device are updated.
This patch adds a command line option which allows to update the
inactive RO to the contents of the Cr50 image.
BRANCH=none
BUG=b:136284186
TEST=running 'gsctool -q cr50.bin' updates the inactive RO section.
Change-Id: I79c21fc2cd41c40070352d8fbce0b71dd3ae2b1f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949547
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit 53f59f6b361e8cf0a8d1af70306146db90ffae23)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2058127
Tested-by: Namyoon Woo <namyoon@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
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Fix errors from pylint. Use logging to print messages instead of print.
BUG=b:149405690
BRANCH=none
TEST=RMA open a device and enable testlab mode.
Change-Id: I63a8b108b0f436291659f2f787ebcf72e8f4a523
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2052269
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
(cherry picked from commit 63e6072b454d41e85fd3763abff412d73090ce2d)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080634
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BUG=b:149405690
BRANCH=none
TEST=run with python3
Change-Id: I42bcccec83c7c582450c0b599f46b3fbf0ab3f80
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2052268
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
(cherry picked from commit 356f6719d9060523f8302eb93f67be97134831c7)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080593
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cr50_rma_open can be run without servod. dut-control
cr50_uart_timestamp:off fails if the script isn't running through
servod. This change moves disabling timestamps, so it's only done on
servod.
BUG=none
BRANCH=none
TEST=run with and withoout servod
Change-Id: Icc80d021dd7cbad8ae3632625b32b30368e5a94c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1960919
Reviewed-by: Evan Green <evgreen@chromium.org>
(cherry picked from commit 633bca2829532c6cad19cf49774a57f6baf8d1bf)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080633
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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The log timestamps are unexpected by the script, and cause issues.
Send a dut-control command to disable UART timestamps.
Also fix the regex in the board ID portion to accept a colon as well as
a comma, whichever comes first.
BUG=None
TEST=Try cr50_rma_unlock.py
BRANCH=None
Change-Id: Ie9e54e65b86c52aef120fa3249453bfc090cf6f0
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1921703
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
(cherry picked from commit 2f814c9a297f2be7a508676a17052c7fe652c1d2)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080632
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Commit-Queue: Mary Ruthven <mruthven@chromium.org>
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BRANCH=cr50, cr50-mp
BUG=none
TEST=none
Change-Id: I1dffd37d08c7d6209fafb9c18c7c5a87a1b20cba
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076503
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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This will allow using this pin a physical presence indicator on
certain platforms.
BRANCH=cr50,cr50-mp
BUG=b:144455668
TEST=tried the new image on the red board, observed DIOM4 level
changing when shorting it to ground.
Change-Id: I7c20b094d73d49321921c5afa67e0db9825ea82f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076499
Reviewed-by: Yicheng Li <yichengli@chromium.org>
Commit-Queue: Yicheng Li <yichengli@chromium.org>
Tested-by: Yicheng Li <yichengli@chromium.org>
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This patch fixes a coding style violation in enum name.
BUG=none
BRANCH=cr50
TEST=none
Change-Id: I53eb8aa0905ecfc841a4fe7a738df74d571e321b
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2065493
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This patch supports EC-CR50 communication.
EC activates EC-CR50 communication by setting high DIOB3, and send
a command packet to CR50 through UART_EC_TX_CR50_RX. Cr50 processes
the packet, and sends a response packet back to EC. EC deactivates
EC-CR50 communication by putting low DIOB3.
This patch supports two kinds of EC-CR50 commands:
- CR50_COMM_CMD_SET_BOOT_MODE
- CR50_COMM_CMD_VERIFY_HASH
Cr50 stores some of EC-EFS context in a powerdown register before
deep sleep and restores it after wakeup.
This patch increases flash usage by 1456 bytes.
BUG=b:119329144
BRANCH=cr50
TEST=Checked "ec_comm" console command on Octopus and
reworked Helios.
Checked uart_stress_tester.py running without character loss.
Change-Id: I23e90b9f3e860a3d198dcee718d7d11080d06e40
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961145
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Based on the design in go/ec-efs2, this patch adds two TPM
vendor-specific commands:
- VENDOR_CC_GET_BOOT_MODE
- VENDOR_CC_RESET_EC
BUG=b:141578322
BRANCH=cr50
TEST=tested with EC-EFS supporting EC/AP firmware.
With CR50 dev image, tested with gsctool on Octopus and Helios
by sending each of new vendor commands.
Checked flash_ec working on Scarlet in bitbang mode.
Change-Id: Ia8f38a7b9cc45b172a1a1ef7e216034e520b79c7
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956409
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Cr50 reads EC Firmware hash from kernel secdata. This data shall be
used for EC-EFS (Early Firmware Selection) procedure.
BUG=chromium:1020578, b:148489182
BRANCH=cr50
TEST=none
Change-Id: Id8942b5b49dd5b0412d198a12ee0bf87fd59d47f
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956159
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Cr50 related utilities should be coming from the cr50_stab branch of
the EC tree. This patch brings back the ToT version of the
util/chargen script which was previously dropped.
BRANCH=cr50, cr50-mp
BUG=b:149350081
TEST=with the rest of the patches applied installed chargen is taken
from platform/cr50
Change-Id: I407c2e8676b28ecc894a59e977feb474f89e880a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2067163
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This patch introduces 'EC_CR50_COMM' a new option for ccdblock
console command.
It can be useful for system rescue purpose like you want to
force cr50 to yield EC_UART (especially TX) port to servo.
BUG=chromium:1047287
BRANCH=cr50, cr50-mp
TEST=ran manually ccdblock.
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
>
>
> ccdblock EC_CR50_COMM enable
CCD ports blocked: EC_CR50_COMM
> [73.386550 CCD state: UARTEC I2C SPI]
>
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTEC I2C SPI
CCD ports blocked: EC_CR50_COMM
>
>
> ccdblock EC_CR50_COMM disable
CCD ports blocked: (none)
> [104.781623 CCD state: UARTEC+TX I2C SPI]
ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
Change-Id: I7816c201054f1793906bd19d4b58755593d2fbac
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2042118
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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- add ec_efs, which tracks the system boot mode.
- add ec_comm.h header file for EC-EFS related functions.
- revised vboot.h header file.
BUG=b:141143112
BRANCH=cr50
TEST=none
Change-Id: Iec1bf466b832bac5ad6be8a52304c1d699a38fb2
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055363
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This scrip copies the Chrome OS run time code which calculates Cr50
image hash, used as the UMA key to keep track of various TPM versions.
BRANCH=none
BUG=none
TEST=verified that generated fingerprint values match previously
generated values:
$ for b in /opt/google/cr50/firmware/*; do
gsctool -b $b
util/tpm_hash_gen.py $b
done
read 524288(0x80000) bytes from ...
RO_A:0.0.11 RW_A:0.4.24[FFFF:00000000:00000010]...
37564a12 928401938 /opt/google/cr50/firmware/cr50.bin.prepvt
read 524288(0x80000) bytes from ...
RO_A:0.0.11 RW_A:0.3.24[00000000:00000000:00000000]...
795daf5c 2036182876 /opt/google/cr50/firmware/cr50.bin.prod
$
Change-Id: Ie129227cea3c68937223c81c068612b044cd5c8b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051306
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This patch optimizes read_tpm_nvmem() by replacing NvGetIndexData()
and NvGetIndexInfo() with NvReadIndexDta() and NvReadIndexInfo()
respectively.
This will reduce NvFindHandle() calls from three to one.
BUG=b:148489182
BRANCH=cr50, cr50-mp
TEST=The function execution time reduces from 1.2 msec to 550 usec.
Cq-Depend:chromium:2038108
Change-Id: I6659480d8b60578f3d0b9dc3f62a677ae8489a57
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037920
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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This patch allows EC-CR50 communication to enable EC UART only
if EC is on and bitbang mode is disabled. EC UART shall be enabled
even when CCD_CAP_GSC_TX_EC_RX is disabled, EC UART is ccdblocked,
or servo is connected. EC-CR50 comm supporting boards are supposed
to have H1 dominate EC UART TX line against servo.
Servo detection, which is checked every second, shall be delayed
during EC-CR50 communication because EC UART TX pin
(GPIO_SERVO_DETECT) is used as an output. Servo state shall be
held as it was. Once EC-CR50 communication is done, the servo
detection will resume or CCD state gets updated based on what
it used to be before EC-CR50 communication.
BUG=chromium:1035706
BRANCH=cr50
TEST=manually tested on a reworked Helios.
// CCD connection only
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ecrst pulse
Pulsing EC reset
EC_RST_L is deasserted
// Servo connection only
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: disconnected
Servo: connected
CCD EXT: disabled
State flags: I2C
CCD ports blocked: (none)
Change-Id: I02667bee004d237d846393a18f247970982c71b7
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2023239
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This CL separates the control on USB-UART bridge of EC device from
EC UART control. USB-UART bridge shall be enabled if CCD connection
is detected and the CCD capability is enabled. Otherwise, EC USB-UART
shall be disabled. By doing so, CCD capability can be observed even
when EC-CR50 communication enables EC UART.
This patch increases the flash usage by 204 bytes
BUG=b:148247228
BRANCH=cr50, cr50_mp
TEST=ran firmware_Cr50CCDServoCap on Helios.
> ccd
State: Locked
Password: none
Flags: 0x000001
Capabilities: 0000000000000000
...
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC I2C USBEC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTAP+TX UARTEC USBEC
CCD ports blocked: (none)
> ccd
State: Opened
Password: none
Flags: 0x800001
Capabilities: 5555454115000000
...
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC I2C USBEC+TX
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX
CCD ports blocked: (none)
Change-Id: I6bb560a05831105ff68a9e13e4b28b002ed98096
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018061
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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BUG=b:147835918
BRANCH=cr50
TEST=none
Change-Id: I07d4071c4fe99df0a030be1e087f43a696081c3c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051101
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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This uses gpio_set_wakepin() to setup the wake pins instead of writing
to the PINMUX EXITEN registers directly.
This patch reduces the flash usage by 248 bytes.
BUG=b:35587259
BRANCH=cr50
TEST=checked pinmux configuration hasn't changed on coral.
Checked firmware_Cr50DeviceState running good on coral.
Change-Id: Ic4ef1751e34b85ea2719f257ebd9b7ad52355eec
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2047923
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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On Wilco devices the recovery key combination will trigger an irq which
will reboot the EC to enter recovery mode. CL:1881752 moved a 30 ms
delay and made it synchronous. This change works in most contexts except
for within an irq which cannot sleep so when a user presses the recovery
key combo the H1 will hard reboot when the sleep is called. This change
defers the call to board_reboot_ec() so that it is no longer in the irq
context.
BUG=b:147404780
TEST=On Drallion and Sarien press pwr + F2, recovery mode is entered
without to hold the keys for an extended period of time. Also
verified that programming flash over CCD still works on Drallion.
BRANCH=none
Change-Id: Ib7ebbe2c67b575b6a99d01a4055bb00ee9d15b7e
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2020328
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Tested-by: Keith Short <keithshort@chromium.org>
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If the board supports EC-CR50 communication, Cr50 enables both
rising/falling-edge triggered interrupt on DIOB3 pin and makes
it wakable as well.Cr50 connects GPIO_AP_FLASH_SELECT to DIOB4.
If the board does not support EC-CR50 communication, Cr50 connects
GPIO_AP_FLASH_SELECT to DIOB3.
If EC puts high on DIOB3 to activate EC-CR50 communication, CR50
enables UART_EC RX and TX.
BUG=chromium:1035706
BRANCH=cr50
TEST=none
Change-Id: I1221a1a19219274622ab710568ce7c66ab2f1da7
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1989581
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Cr50 needs a cleaner way to enable and disable wakepins. This change
adds gpio_set_wakepin() to enable the wake pin or disable.
The gpio_set_flags() or gpio_set_flags_by_mask() remain unaffecting
wake-pin configuration.
This patch increases the flash usage by 16 bytes.
BUG=b:35587259
BRANCH=cr50
TEST=verify pinmux has the same output before and after the change on
octopus.
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/533674
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
Change-Id: I0387c673aedc046ce9cf6b5f0d683c40f3079281
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044355
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There seems to be some odd interaction between ccache version 3.7.6
and the set of command line options passed to gcc by the EC makefile,
as a result the generated dependency files are wrong, the target file
name is missing the path.
The -MT command line option makes sure that the correct target file
name is generated. Had to make similar changes in
../../third_party/{cryptoc,tpm2} Makefiles.
No need to change extra/usb_updater/Makefile as it puts .o files in
the same directory where .c files are.
BRANCH=all
BUG=b:148943341
TEST=verified that relevant object files are rebuilt when an .h file
is touched.
Also, with companion changes in cryptoc and tpm2 trees verified
that all generated my 'make buildall' .d files have proper target
values (including path), apart froom files in extra/usb_udater,
which place .o files in the same directory with .c files.
Change-Id: I22dfad94c112582230a2b6b60289e029a382d822
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2039988
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit f42be6e2a1eefaee06ed7593373fbe6dedb3dd6c)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044511
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Bit assignment in this enum has been changed.
* BIT(1) : NO_BOOT flag -> RECOVERY flag
* BIT(0) : RECOVERY flag -> NO_BOOT flag
For this change, two members of enum ec_efs_boot_mode are swapped.
- EC_EFS_BOOT_MODE_NO_BOOT = 0x01, // used to be 0x02
- EC_EFS_BOOT_MODE_RECOVERY = 0x02, // used to be 0x01
BUG=b:141578322
BRANCH=cr50
TEST=make buildall -j
Change-Id: I88c4ef02cabd7fc3840467f7ff07444865969b31
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2029200
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This patch reduces redundant condition checking in connecting
or disconnecting UART TX.
BUG=none
BRANCH=cr50
TEST=manually checked ccd state with/without servo connection and/or
ccd connection.
[AFTER]
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: disconnected
Servo: connected
CCD EXT: disabled
State flags:
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTAP+TX I2C SPI
CCD ports blocked: EC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: I2C SPI
CCD ports blocked: AP EC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: ignored
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI
CCD ports blocked: IGNORE_SERVO
WARNING: enabling UART while servo is connected may damage hardware
Change-Id: Icea2978b15e15bbf7cea8e48fd2bf4fdecc78f46
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013823
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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BRANCH=cr50, cr50-mp
BUG=none
TEST=none
Change-Id: I284e295dd2db0564b8f89832fc47cf4d0fbc6a50
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013450
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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This CL defines new macros, an enum and a data structure for EC-EFS2
implementation.
BUG=b:141143112
BRANCH=cr50
TEST=make buildall -j
Change-Id: I0b5d634f8e040638b4c4ffef5c8519959c509577
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956158
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This change introduces a mechanism which allows to use one of board
strap pins as the CCD gpio and makes DIOA9 the CCD pin on boards with
strap os 0xE.
This change uses 2 bits from the board properties to determine which pin
is used as the ccd gpio.
0 - no ccd gpio
1 - DIOA1
2 - DIOA9
3 - DIOA12
DIOA6 is another strap pin, but there's only one valid strap with a 5kPU
left, so I decided not to use another board property bit to support it
as a possible ccd gpio. I want to save the board property bit, since
we're running out of them and there are so many other I2C straps boards
can use. We can add it later if we need to.
BUG=b:147812066
BRANCH=cr50
TEST=manual. Use pinmux and gpiocfg to verify the output is only enabled
when the gpio is asserted.
no added brdproperties - nothing is different with pinmux
run on Puff
gpioset CCD_REC_LID_SWITCH 0
EC shows recovery button pressed
gpioset CCD_REC_LID_SWITCH 0
EC shows recovery button released
add BOARD_CCD_REC_LID_PIN_DIOA1 to SPI board
pinmux output adds
DIOA1 27 IN GPIO1_GPIO10
GPIO1_GPIO10 24 DIOA1
gpioset CCD_REC_LID_SWITCH 0
gpiocfg shows "GPIO1_GPIO10: read 0 drive 0"
gpioset CCD_REC_LID_SWITCH 1
gpiocfg doesn't show GPIO1_GPIO10 as an output
add BOARD_CCD_REC_LID_PIN_DIOA9 to SPI board
pinmux output adds
DIOA9 27 IN GPIO1_GPIO10
GPIO1_GPIO10 16 DIOA9
gpioset CCD_REC_LID_SWITCH 0
gpiocfg shows "GPIO1_GPIO10: read 0 drive 0"
gpioset CCD_REC_LID_SWITCH 1
gpiocfg doesn't show GPIO1_GPIO10 as an output
add BOARD_CCD_REC_LID_PIN_DIOA12 to I2C board
pinmux output adds
DIOA12 27 IN GPIO1_GPIO10
GPIO1_GPIO10 13 DIOA12
gpioset CCD_REC_LID_SWITCH 0
gpiocfg shows "GPIO1_GPIO10: read 0 drive 0"
gpioset CCD_REC_LID_SWITCH 1
gpiocfg doesn't show GPIO1_GPIO10 as an output
Change-Id: If74385135a572e7e5d0763fad9f5368fdec8d7a0
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006210
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Nothing reads this file anymore.
BUG=chromium:1025955
TEST=CQ passes
BRANCH=none
Exempt-From-Owner-Approval: cleanup removing unused file
Change-Id: Ie64006cb87f949ce350b2dde312a79973f190559
Signed-off-by: Ross Zwisler <zwisler@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2008088
Reviewed-by: Sean Abraham <seanabraham@chromium.org>
Commit-Queue: Sean Abraham <seanabraham@chromium.org>
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Modify the issuer and the subject for the certificate to have a way
to distinguish between implementations before and after fixing
b:147097407.
BRANCH=none
BUG=b:147097407
TEST=build
Change-Id: I2b10212384940e101e8f0d0ac711350e64503168
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003533
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This patch extends INT_AP_L pulses to be at least 6.5 micro seconds.
It is a tentative solution to to meet Intel TGL/JSL requirement on
interrupt duration.
BUG=b:130515803
BRANCH=cr50
TEST=checked INT_AP_L pulse length ranges extended to 6.5 ~ 11 usec
with logic analyzer on Hatch.
Checked dmesg and coreboot log has no TPM errors.
Change-Id: Iea8d0a779fff7cbda0c8647f3c1de719c3c3d7e0
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002958
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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