| Commit message (Collapse) | Author | Age | Files | Lines |
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cr50_rma_open can be run without servod. dut-control
cr50_uart_timestamp:off fails if the script isn't running through
servod. This change moves disabling timestamps, so it's only done on
servod.
BUG=none
BRANCH=none
TEST=run with and withoout servod
Change-Id: Icc80d021dd7cbad8ae3632625b32b30368e5a94c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1960919
Reviewed-by: Evan Green <evgreen@chromium.org>
(cherry picked from commit 633bca2829532c6cad19cf49774a57f6baf8d1bf)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080633
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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The log timestamps are unexpected by the script, and cause issues.
Send a dut-control command to disable UART timestamps.
Also fix the regex in the board ID portion to accept a colon as well as
a comma, whichever comes first.
BUG=None
TEST=Try cr50_rma_unlock.py
BRANCH=None
Change-Id: Ie9e54e65b86c52aef120fa3249453bfc090cf6f0
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1921703
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
(cherry picked from commit 2f814c9a297f2be7a508676a17052c7fe652c1d2)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080632
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Commit-Queue: Mary Ruthven <mruthven@chromium.org>
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BRANCH=cr50, cr50-mp
BUG=none
TEST=none
Change-Id: I1dffd37d08c7d6209fafb9c18c7c5a87a1b20cba
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076503
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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This will allow using this pin a physical presence indicator on
certain platforms.
BRANCH=cr50,cr50-mp
BUG=b:144455668
TEST=tried the new image on the red board, observed DIOM4 level
changing when shorting it to ground.
Change-Id: I7c20b094d73d49321921c5afa67e0db9825ea82f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076499
Reviewed-by: Yicheng Li <yichengli@chromium.org>
Commit-Queue: Yicheng Li <yichengli@chromium.org>
Tested-by: Yicheng Li <yichengli@chromium.org>
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This patch fixes a coding style violation in enum name.
BUG=none
BRANCH=cr50
TEST=none
Change-Id: I53eb8aa0905ecfc841a4fe7a738df74d571e321b
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2065493
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This patch supports EC-CR50 communication.
EC activates EC-CR50 communication by setting high DIOB3, and send
a command packet to CR50 through UART_EC_TX_CR50_RX. Cr50 processes
the packet, and sends a response packet back to EC. EC deactivates
EC-CR50 communication by putting low DIOB3.
This patch supports two kinds of EC-CR50 commands:
- CR50_COMM_CMD_SET_BOOT_MODE
- CR50_COMM_CMD_VERIFY_HASH
Cr50 stores some of EC-EFS context in a powerdown register before
deep sleep and restores it after wakeup.
This patch increases flash usage by 1456 bytes.
BUG=b:119329144
BRANCH=cr50
TEST=Checked "ec_comm" console command on Octopus and
reworked Helios.
Checked uart_stress_tester.py running without character loss.
Change-Id: I23e90b9f3e860a3d198dcee718d7d11080d06e40
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961145
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Based on the design in go/ec-efs2, this patch adds two TPM
vendor-specific commands:
- VENDOR_CC_GET_BOOT_MODE
- VENDOR_CC_RESET_EC
BUG=b:141578322
BRANCH=cr50
TEST=tested with EC-EFS supporting EC/AP firmware.
With CR50 dev image, tested with gsctool on Octopus and Helios
by sending each of new vendor commands.
Checked flash_ec working on Scarlet in bitbang mode.
Change-Id: Ia8f38a7b9cc45b172a1a1ef7e216034e520b79c7
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956409
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Cr50 reads EC Firmware hash from kernel secdata. This data shall be
used for EC-EFS (Early Firmware Selection) procedure.
BUG=chromium:1020578, b:148489182
BRANCH=cr50
TEST=none
Change-Id: Id8942b5b49dd5b0412d198a12ee0bf87fd59d47f
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956159
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Cr50 related utilities should be coming from the cr50_stab branch of
the EC tree. This patch brings back the ToT version of the
util/chargen script which was previously dropped.
BRANCH=cr50, cr50-mp
BUG=b:149350081
TEST=with the rest of the patches applied installed chargen is taken
from platform/cr50
Change-Id: I407c2e8676b28ecc894a59e977feb474f89e880a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2067163
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This patch introduces 'EC_CR50_COMM' a new option for ccdblock
console command.
It can be useful for system rescue purpose like you want to
force cr50 to yield EC_UART (especially TX) port to servo.
BUG=chromium:1047287
BRANCH=cr50, cr50-mp
TEST=ran manually ccdblock.
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
>
>
> ccdblock EC_CR50_COMM enable
CCD ports blocked: EC_CR50_COMM
> [73.386550 CCD state: UARTEC I2C SPI]
>
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTEC I2C SPI
CCD ports blocked: EC_CR50_COMM
>
>
> ccdblock EC_CR50_COMM disable
CCD ports blocked: (none)
> [104.781623 CCD state: UARTEC+TX I2C SPI]
ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
Change-Id: I7816c201054f1793906bd19d4b58755593d2fbac
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2042118
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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- add ec_efs, which tracks the system boot mode.
- add ec_comm.h header file for EC-EFS related functions.
- revised vboot.h header file.
BUG=b:141143112
BRANCH=cr50
TEST=none
Change-Id: Iec1bf466b832bac5ad6be8a52304c1d699a38fb2
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055363
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This scrip copies the Chrome OS run time code which calculates Cr50
image hash, used as the UMA key to keep track of various TPM versions.
BRANCH=none
BUG=none
TEST=verified that generated fingerprint values match previously
generated values:
$ for b in /opt/google/cr50/firmware/*; do
gsctool -b $b
util/tpm_hash_gen.py $b
done
read 524288(0x80000) bytes from ...
RO_A:0.0.11 RW_A:0.4.24[FFFF:00000000:00000010]...
37564a12 928401938 /opt/google/cr50/firmware/cr50.bin.prepvt
read 524288(0x80000) bytes from ...
RO_A:0.0.11 RW_A:0.3.24[00000000:00000000:00000000]...
795daf5c 2036182876 /opt/google/cr50/firmware/cr50.bin.prod
$
Change-Id: Ie129227cea3c68937223c81c068612b044cd5c8b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051306
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This patch optimizes read_tpm_nvmem() by replacing NvGetIndexData()
and NvGetIndexInfo() with NvReadIndexDta() and NvReadIndexInfo()
respectively.
This will reduce NvFindHandle() calls from three to one.
BUG=b:148489182
BRANCH=cr50, cr50-mp
TEST=The function execution time reduces from 1.2 msec to 550 usec.
Cq-Depend:chromium:2038108
Change-Id: I6659480d8b60578f3d0b9dc3f62a677ae8489a57
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037920
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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This patch allows EC-CR50 communication to enable EC UART only
if EC is on and bitbang mode is disabled. EC UART shall be enabled
even when CCD_CAP_GSC_TX_EC_RX is disabled, EC UART is ccdblocked,
or servo is connected. EC-CR50 comm supporting boards are supposed
to have H1 dominate EC UART TX line against servo.
Servo detection, which is checked every second, shall be delayed
during EC-CR50 communication because EC UART TX pin
(GPIO_SERVO_DETECT) is used as an output. Servo state shall be
held as it was. Once EC-CR50 communication is done, the servo
detection will resume or CCD state gets updated based on what
it used to be before EC-CR50 communication.
BUG=chromium:1035706
BRANCH=cr50
TEST=manually tested on a reworked Helios.
// CCD connection only
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ecrst pulse
Pulsing EC reset
EC_RST_L is deasserted
// Servo connection only
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: disconnected
Servo: connected
CCD EXT: disabled
State flags: I2C
CCD ports blocked: (none)
Change-Id: I02667bee004d237d846393a18f247970982c71b7
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2023239
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This CL separates the control on USB-UART bridge of EC device from
EC UART control. USB-UART bridge shall be enabled if CCD connection
is detected and the CCD capability is enabled. Otherwise, EC USB-UART
shall be disabled. By doing so, CCD capability can be observed even
when EC-CR50 communication enables EC UART.
This patch increases the flash usage by 204 bytes
BUG=b:148247228
BRANCH=cr50, cr50_mp
TEST=ran firmware_Cr50CCDServoCap on Helios.
> ccd
State: Locked
Password: none
Flags: 0x000001
Capabilities: 0000000000000000
...
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC I2C USBEC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTAP+TX UARTEC USBEC
CCD ports blocked: (none)
> ccd
State: Opened
Password: none
Flags: 0x800001
Capabilities: 5555454115000000
...
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC I2C USBEC+TX
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX
CCD ports blocked: (none)
Change-Id: I6bb560a05831105ff68a9e13e4b28b002ed98096
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018061
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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BUG=b:147835918
BRANCH=cr50
TEST=none
Change-Id: I07d4071c4fe99df0a030be1e087f43a696081c3c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051101
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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This uses gpio_set_wakepin() to setup the wake pins instead of writing
to the PINMUX EXITEN registers directly.
This patch reduces the flash usage by 248 bytes.
BUG=b:35587259
BRANCH=cr50
TEST=checked pinmux configuration hasn't changed on coral.
Checked firmware_Cr50DeviceState running good on coral.
Change-Id: Ic4ef1751e34b85ea2719f257ebd9b7ad52355eec
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2047923
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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On Wilco devices the recovery key combination will trigger an irq which
will reboot the EC to enter recovery mode. CL:1881752 moved a 30 ms
delay and made it synchronous. This change works in most contexts except
for within an irq which cannot sleep so when a user presses the recovery
key combo the H1 will hard reboot when the sleep is called. This change
defers the call to board_reboot_ec() so that it is no longer in the irq
context.
BUG=b:147404780
TEST=On Drallion and Sarien press pwr + F2, recovery mode is entered
without to hold the keys for an extended period of time. Also
verified that programming flash over CCD still works on Drallion.
BRANCH=none
Change-Id: Ib7ebbe2c67b575b6a99d01a4055bb00ee9d15b7e
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2020328
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Tested-by: Keith Short <keithshort@chromium.org>
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If the board supports EC-CR50 communication, Cr50 enables both
rising/falling-edge triggered interrupt on DIOB3 pin and makes
it wakable as well.Cr50 connects GPIO_AP_FLASH_SELECT to DIOB4.
If the board does not support EC-CR50 communication, Cr50 connects
GPIO_AP_FLASH_SELECT to DIOB3.
If EC puts high on DIOB3 to activate EC-CR50 communication, CR50
enables UART_EC RX and TX.
BUG=chromium:1035706
BRANCH=cr50
TEST=none
Change-Id: I1221a1a19219274622ab710568ce7c66ab2f1da7
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1989581
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Cr50 needs a cleaner way to enable and disable wakepins. This change
adds gpio_set_wakepin() to enable the wake pin or disable.
The gpio_set_flags() or gpio_set_flags_by_mask() remain unaffecting
wake-pin configuration.
This patch increases the flash usage by 16 bytes.
BUG=b:35587259
BRANCH=cr50
TEST=verify pinmux has the same output before and after the change on
octopus.
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/533674
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
Change-Id: I0387c673aedc046ce9cf6b5f0d683c40f3079281
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044355
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There seems to be some odd interaction between ccache version 3.7.6
and the set of command line options passed to gcc by the EC makefile,
as a result the generated dependency files are wrong, the target file
name is missing the path.
The -MT command line option makes sure that the correct target file
name is generated. Had to make similar changes in
../../third_party/{cryptoc,tpm2} Makefiles.
No need to change extra/usb_updater/Makefile as it puts .o files in
the same directory where .c files are.
BRANCH=all
BUG=b:148943341
TEST=verified that relevant object files are rebuilt when an .h file
is touched.
Also, with companion changes in cryptoc and tpm2 trees verified
that all generated my 'make buildall' .d files have proper target
values (including path), apart froom files in extra/usb_udater,
which place .o files in the same directory with .c files.
Change-Id: I22dfad94c112582230a2b6b60289e029a382d822
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2039988
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit f42be6e2a1eefaee06ed7593373fbe6dedb3dd6c)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044511
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Bit assignment in this enum has been changed.
* BIT(1) : NO_BOOT flag -> RECOVERY flag
* BIT(0) : RECOVERY flag -> NO_BOOT flag
For this change, two members of enum ec_efs_boot_mode are swapped.
- EC_EFS_BOOT_MODE_NO_BOOT = 0x01, // used to be 0x02
- EC_EFS_BOOT_MODE_RECOVERY = 0x02, // used to be 0x01
BUG=b:141578322
BRANCH=cr50
TEST=make buildall -j
Change-Id: I88c4ef02cabd7fc3840467f7ff07444865969b31
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2029200
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This patch reduces redundant condition checking in connecting
or disconnecting UART TX.
BUG=none
BRANCH=cr50
TEST=manually checked ccd state with/without servo connection and/or
ccd connection.
[AFTER]
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: disconnected
Servo: connected
CCD EXT: disabled
State flags:
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTAP+TX I2C SPI
CCD ports blocked: EC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: I2C SPI
CCD ports blocked: AP EC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: ignored
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI
CCD ports blocked: IGNORE_SERVO
WARNING: enabling UART while servo is connected may damage hardware
Change-Id: Icea2978b15e15bbf7cea8e48fd2bf4fdecc78f46
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013823
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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BRANCH=cr50, cr50-mp
BUG=none
TEST=none
Change-Id: I284e295dd2db0564b8f89832fc47cf4d0fbc6a50
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013450
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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This CL defines new macros, an enum and a data structure for EC-EFS2
implementation.
BUG=b:141143112
BRANCH=cr50
TEST=make buildall -j
Change-Id: I0b5d634f8e040638b4c4ffef5c8519959c509577
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956158
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This change introduces a mechanism which allows to use one of board
strap pins as the CCD gpio and makes DIOA9 the CCD pin on boards with
strap os 0xE.
This change uses 2 bits from the board properties to determine which pin
is used as the ccd gpio.
0 - no ccd gpio
1 - DIOA1
2 - DIOA9
3 - DIOA12
DIOA6 is another strap pin, but there's only one valid strap with a 5kPU
left, so I decided not to use another board property bit to support it
as a possible ccd gpio. I want to save the board property bit, since
we're running out of them and there are so many other I2C straps boards
can use. We can add it later if we need to.
BUG=b:147812066
BRANCH=cr50
TEST=manual. Use pinmux and gpiocfg to verify the output is only enabled
when the gpio is asserted.
no added brdproperties - nothing is different with pinmux
run on Puff
gpioset CCD_REC_LID_SWITCH 0
EC shows recovery button pressed
gpioset CCD_REC_LID_SWITCH 0
EC shows recovery button released
add BOARD_CCD_REC_LID_PIN_DIOA1 to SPI board
pinmux output adds
DIOA1 27 IN GPIO1_GPIO10
GPIO1_GPIO10 24 DIOA1
gpioset CCD_REC_LID_SWITCH 0
gpiocfg shows "GPIO1_GPIO10: read 0 drive 0"
gpioset CCD_REC_LID_SWITCH 1
gpiocfg doesn't show GPIO1_GPIO10 as an output
add BOARD_CCD_REC_LID_PIN_DIOA9 to SPI board
pinmux output adds
DIOA9 27 IN GPIO1_GPIO10
GPIO1_GPIO10 16 DIOA9
gpioset CCD_REC_LID_SWITCH 0
gpiocfg shows "GPIO1_GPIO10: read 0 drive 0"
gpioset CCD_REC_LID_SWITCH 1
gpiocfg doesn't show GPIO1_GPIO10 as an output
add BOARD_CCD_REC_LID_PIN_DIOA12 to I2C board
pinmux output adds
DIOA12 27 IN GPIO1_GPIO10
GPIO1_GPIO10 13 DIOA12
gpioset CCD_REC_LID_SWITCH 0
gpiocfg shows "GPIO1_GPIO10: read 0 drive 0"
gpioset CCD_REC_LID_SWITCH 1
gpiocfg doesn't show GPIO1_GPIO10 as an output
Change-Id: If74385135a572e7e5d0763fad9f5368fdec8d7a0
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006210
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Nothing reads this file anymore.
BUG=chromium:1025955
TEST=CQ passes
BRANCH=none
Exempt-From-Owner-Approval: cleanup removing unused file
Change-Id: Ie64006cb87f949ce350b2dde312a79973f190559
Signed-off-by: Ross Zwisler <zwisler@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2008088
Reviewed-by: Sean Abraham <seanabraham@chromium.org>
Commit-Queue: Sean Abraham <seanabraham@chromium.org>
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Modify the issuer and the subject for the certificate to have a way
to distinguish between implementations before and after fixing
b:147097407.
BRANCH=none
BUG=b:147097407
TEST=build
Change-Id: I2b10212384940e101e8f0d0ac711350e64503168
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003533
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This patch extends INT_AP_L pulses to be at least 6.5 micro seconds.
It is a tentative solution to to meet Intel TGL/JSL requirement on
interrupt duration.
BUG=b:130515803
BRANCH=cr50
TEST=checked INT_AP_L pulse length ranges extended to 6.5 ~ 11 usec
with logic analyzer on Hatch.
Checked dmesg and coreboot log has no TPM errors.
Change-Id: Iea8d0a779fff7cbda0c8647f3c1de719c3c3d7e0
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002958
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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This CL adds checks to U2F_ATTEST and rejects signing of the passed data
if one of the following conditions is not satisfied:
- reserved byte is 0,
- public key matches the key associated with the keyhandle.
BUG=b:147097407
TEST=test_that <dut> firmware_Cr50U2fCommands
Change-Id: I10005742042a182a894eed243e006fcf14f68e28
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1984891
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Andrey Pronin <apronin@chromium.org>
Commit-Queue: Andrey Pronin <apronin@chromium.org>
Auto-Submit: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit aa9cdf2daf1aa2b30866c2d3aa260b47ed40808a)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003403
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This CL updates verification of the message size in U2F_ATTEST after
adding userSecret field.
BUG=b:147020573
TEST=test_that <dut> firmware_Cr50U2fCommands
Change-Id: Ib1e9444fdd13ed27547df27aa9c2fed19ba59496
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1984894
Tested-by: Andrey Pronin <apronin@chromium.org>
Commit-Queue: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit d982955abbd9a7d85ca48d13f85809576f2efc26)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003942
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This CL add a board property indicating EC-CR50 communication
support. The target boards are Volteer,Dedede,Puff, and Zork.
It shall be detected if the H1 strap configuration value is
either 0x0E or 0xE0.
BUG=b:146567516, chromium:1027660
BRANCH=cr50
TEST=Flashed AP firmware through CCD on Grunt, Octopus, Scarlet
and Atlas.
This is the captured console log:
--- UART initialized after reboot ---
...
strap pin readings: a1:2 a9:2 a6:0 a12:0
[0.005886 Valid strap: 0xa properties: 0x41]
> brdprop
properties = 0x1141
> brdprop
properties = 0x201141
> pinmux
...
400600b0: DIOB2 2 IN GPIO0_GPIO1
400600b8: DIOB3 3 IN GPIO0_GPIO2
400600c0: DIOB4 0 IN PD
...
40060100: GPIO0_GPIO2 7 DIOB3
...
40060120: GPIO0_GPIO10 6 DIOB4
Flashed AP firmware on a reworked board with 1M ohm on DIOA1 and
5k ohm on DIOA9.
This is the captured console log:
--- UART initialized after reboot ---
...
strap pin readings: a1:2 a9:3 a6:0 a12:0
[0.005886 Valid strap: 0xe properties: 0x200041]
> brdprop
properties = 0x201141
> pinmux
...
400600b0: DIOB2 2 IN GPIO0_GPIO1
400600c0: DIOB4 3 IN PD GPIO0_GPIO2
...
40060100: GPIO0_GPIO2 6 DIOB4
...
40060120: GPIO0_GPIO10 6 DIOB4
Change-Id: If60765190a385a0e728177911b1ec738c6a00d99
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1979612
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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There is no need to keep the code supporting chip factory mode in
Chrome OS production branches, this code is never used outside of the
chip factory environment.
BRANCH=cr50, cr50-mp
BUG=none
TEST=built an image, verified that an Atlas device boots up into the
previously created Chrome OS account.
Change-Id: If72635b014d15ef6e97fbc4fd5b54b61ec23299a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994369
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The patch which dropped building tools from the util directory
(https://crrev.com/c/1986943) proved to be a bit too aggressive, and
broke building of BOARD=fizz.
This patch reintroduces building of the missing tool
BRANCH=cr50, cr50-mp
BUG=none
TEST='make buildall -j' succeeds.
Change-Id: I7e093b3c74633eabae17834353ca72653a660563
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1990359
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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The vast majority of tools built from the ./util directory and many
built from ./extra/usb_updater directory are not used by Cr50, let's
not build them.
Also eliminating some irrelevant pre-upload checks.
BRANCH=cr50, cr50-mp
BUG=b:145912698
TEST=verified that all the following commands succeed:
make buildall -j
make BOARD=cr50 CR50_DEV=1 -j
make BOARD=cr50 CR50_SQA=1 -j
make -C extra/usb_updater
Change-Id: I0040ceab95ad280bda86ef599b3e902addcbdcde
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986943
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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The only board which would be built from this branch is Cr50. bds,
fizz and host boards are necessary for proper make infrastructure
operation and tests.
lm4 and npcx are chips used by the bds and fizz boards, so they are
also kept around.
BRANCH=cr50, cr50-mp
BUG=b:145912698
TEST='make buildall -j' succeeds
Change-Id: I937b2b8642c1fe91578fc9615438ae22c165b20f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986942
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Rolling back to 0.0.22 requires erasing the INFO1 rollback protection
space, as current RW level is at two, and 0.0.22 is at one.
The only way to erase INFO1 is to run a node locked prod signed 0.3.22
image. But 0.3.22 will destroy board ID along with the rollback spaces
AND it is not capable of rollback, so to roll back to a lower than
0.3.22 version one still needs to run the SQA image. 0.3.22 will not
allow to restore the Board ID either.
Another problem is that SQA image would update the rollback INFO1
space, thus again preventing 0.0.22 from running.
This patch alleviates the situation by allowing the SQA images to
write Board ID fields and preventing SQA images from updating rollback
space in INFO1.
BRANCH=cr50
BUG=b:146522336
TEST=with the new image was able to downgrade a device from 0.4.24 to
0.0.22
Change-Id: I8babf15ae32036dc612ae9c808c773a2b3355762
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1975092
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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It takes 14.5 ms to decrypt two 12K flash spaces into SRAM, then
calculate their hash to see if either one is is a valid NVMEM
space.
There is no need for this check when the 'other' Cr50 image is newer
than {3,4}.18.
BRANCH=Cr50, Cr50-mp
BUG=b:132665283
TEST=with added instrumentation verified that in case the other slot
is occupied by 0.0.22 image, the check takes 14.5 ms, when the
other slot is occupied by 0.4.23 image the check takes 8 us.
Change-Id: I0414ca3d7e90d343589a21e91319f35479632eff
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1967543
Reviewed-by: Keith Short <keithshort@chromium.org>
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Change the OWNERS to cr50 team members and remove OWNERS files from all
subdirectories.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5ddff7c433a55b6724d92c026e9e64e82e1492ad
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957850
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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CR50 used to detects the custom TPM command code if the vendor
specific bit field is set.
This patch enfornces this condition by comparing the command code
to 0x20000000 value.
It is planned to support extended TPM commands, which are not yet
standard, and those commands shall have 0x20000000|x as their command
code. This patch will pass those commands to tpm2 library directly by
calling ExecuteCommand().
BUG=b:140527213
BRANCH=cr50
TEST=ran gsctools with -m, -o, -i options.
Cq-Depend: chromium:1892419
Change-Id: I43ce52bee96f6b6def8e4bf3a14f092b3235740a
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1891523
Reviewed-by: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit 939160b5b82424e57457a3d07dccfe7127681787)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958419
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CONFIG_DCRYPTO compiles and links thirdparty/libcryptoc for cr50.
CONFIG_LIBCRYPTOC does similar things for other boards that configures
it, including host. This resulted in cr50_fuzz having concurrent
recipes for libcryptoc, as it has both configs. This change separates
CONFIG_DCRYPTO from the responsibility of building and linking libcryptoc.
Libcryptoc is now solely handles by CONFIG_LIBCRYPTOC.
BRANCH=none
BUG=b:144811298
TEST=make -j buildall > /dev/null
Observed no more "warning: overriding recipe for target
'build/host/cr50_fuzz/cryptoc/libcryptoc.a' "
Change-Id: I2186cbead773629456da254df5f82b96e9646fc2
Signed-off-by: Yicheng Li <yichengli@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949554
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit a018043265ecb3466863ff9020ab25d552105c61)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956404
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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Both RO and RW sections have their respective rollback spaces in
INFO1, but until now Cr50 code did not honor the RO binaries' headers
rollback maps and did not update the appropriate iNFO1 space.
With this patch both RO and RW info maps are updated to the lowest
level of the two images found in the flash when invoked during
board_init() or to match the currently active RO/RW when invoked
through vendor command indicating successful OS startup.
BRANCH=cr50, cr50-mp
BUG=b:136284186
TEST=tried the new image on a chip with freshly erased INFO1 space:
first running a DBG image, which does not touch INFO1 maps:
> vers
...
RO_A: * 0.0.11/bc74f7dc
RO_B: 0.0.11/4d655eab
RW_A: * 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
RW_B: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
..
> sysinfo
...
Rollback: 0/1/1 0/128/128
...
Then running an image with debug extensions disabled:
> vers
...
RO_A: * 0.0.11/bc74f7dc
RO_B: 0.0.11/4d655eab
RW_A: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
RW_B: * 0.4.24/cr50_v2.0.2744-d79516a9d
...
> sysinfo
...
Rollback: 1/1/1 2/128/2
...
Change-Id: I259a3f46c03199633ca85389872449d667f172fb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949548
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
(cherry picked from commit 94cfd7cee548047d8e0f5dee2995c4c03fba665d)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954342
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Cr50 firmware is required to update the rollback prevention map in
INFO1 for both RO and RW images.
This patch adds code to display the state of the RO map and both RO_A
and RO_B headers in addition to previously reported RW information.
BRANCH=cr50, cr50-mp
BUG=b:136284186
TEST=loaded the new image and observed reported rollback state:
> sysinfo
...
Rollback: 0/1/1 0/128/128
...
Change-Id: I32206545b6a59a5693e4274e62fcf0627780f61f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949546
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
(cherry picked from commit 565c54c270bd93ee30e8f8560d3d1691d128e762)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954341
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Added definition of FWMP_DEV_FIPS_MODE matching same definition in vboot.
Support function board_fwmp_fips_mode_enabled() introduced to read
it's status. It's not currently used, but will be consumed by
FIPS code.
BUG=b:138577491
BRANCH=cr50
TEST=make BOARD=cr50
Change-Id: Iebf672cfebfeb18ae62892097fbf1fa30a770338
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1950813
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
(cherry picked from commit bf8241699ba35984887e3f1a71d29ea1e92b21fe)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954340
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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DCRYPTO_gcm_init hardcoded key length to 128 bit causing preventing
testing of 192 and 256 bit functionality for AES-GCM.
BUG=b:135623371
BRANCH=cr50
TEST=compile, specific test for issue as described in bug
Change-Id: I4fc41f6155661709115c57aa944c8976e17bffac
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766098
Reviewed-by: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit 24f7511e41c1f8140b19d69d9440a3ea6f91bd89)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954339
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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The new RW dev key does not follow the existing convention of bit 0x4
set in prod Key ID and unset in dev key ID.
The suggested approach is to check values of some key manager
registers to determine if the device is running in fully configured
prod mode or not.
BRANCH=cr50, cr50-mp
BUG=b:144455990
TEST=tried running this patch on a node locked image:
> sysinfo
...
RO keyid: 0xaa66150f
RW keyid: 0x334f70df
...
Key Ladder: dev
Change-Id: I73088ce44a8b8bf8e11a0d240d07152b49a3225b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1915504
Reviewed-by: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit 74237689eb277bf1fe0e682cb256825508fa511f)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954338
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Smart erase is used by the haven private-CR51 firmware, I don't
know if other projects use it.
Smart erase attempts to speed up erase by checking if the block
to be erased is all ff's, and only erasing it if there is
content (not ff's).
The bug is that after erasing a block, the code does not wait
for completion of the erase before reading ahead to see if the
next block is already erased (all ff's). This is contrary to the
spec where the only valid operation is a check of the status
after issuing the erase.
On some eeproms, with some timings, this causes the smart erase to
give a flase positive erased block detection. Ie, the eeprom reads
back al ff's while it's busy doing the erase. The upshot is that
only the first non erased block is erased, and the rest of the
eeprom is left untouched.
The code before smart erase looked like:
do
wait for not busy
erase block
until all erased
wait for not busy
Smart erase was added by inserting the check for erased at the top of
the loop. If instead, it's moved down below the wait for not busy,
everything works fine. (Or, the wait for not busy is moved back to
top of the loop.) This is the fix used here.
TEST= Run without and with patch on a Starcard. Without patch
not all of the targeted flash is erased. With patch, all of the
targeted flash is erased.
BUG=b:144868388
BRANCH=barryt/smart
Signed-off-by: barryt@google.com
Change-Id: I679ad4d21c3c353252646394f5631abc42782ded
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931466
Reviewed-by: Jeff Andersen <jeffandersen@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Barry Twycross <barryt@google.com>
Commit-Queue: Barry Twycross <barryt@google.com>
Tested-by: Barry Twycross <barryt@google.com>
Auto-Submit: Barry Twycross <barryt@google.com>
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The formatter should try and reflow comments to fit within the 80
character column limit
BRANCH=none
BUG=none
TEST=verified that long comments get formatted to wrap within the 80
column limit within VScode
Change-Id: I219e8e4d55ebbb7931d1b0e9fb41c7f48744d2aa
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1937887
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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Simplified the usb_mux_get() function and made the MUX info
prints same as in ectool.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Iefb16e1dbd323afbe248b06fe9c53abc63be9a67
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931284
Reviewed-by: Jett Rink <jettrink@chromium.org>
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PD_DP_PIN_CAPS used a lot of magic numbers, which made it difficult
to work out what it's doing. Added a comment about using the
"receptacle type" field to deterimine whether the UFP_D or DFP_D pin
assignments should be used, and replaced magic numbers with #define'd
constants.
BUG=None
BRANCH=None
TEST=`make -j buildall && ./util/flash_ec --board=kohaku` (or
whatever board you're testing with), then verify that a USB-C dock
with HDMI or DisplayPort still works.
Change-Id: I1b5cf6d6cf7d0e1698bd7c727226f10f804ed5e9
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1935088
Reviewed-by: Jett Rink <jettrink@chromium.org>
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