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* Replace __attribute__((noreturn)) with noreturnTom Hughes2020-08-1720-39/+60
| | | | | | | | | | | | | | | _Noreturn was added in C11 and the convenience macro "noreturn" is specified by stdnoreturn.h: https://en.cppreference.com/w/c/language/_Noreturn. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I30361bb5290cea1c776a7356f7e3a68edf1f8e39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324816 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* builtin: Add stdnoreturn.hTom Hughes2020-08-171-0/+20
| | | | | | | | | | | | | | | | | | _Noreturn was added in C11 and the convenience macro "noreturn" is specified by stdnoreturn.h: https://en.cppreference.com/w/c/language/_Noreturn. We need our own implementation of the header since we don't include the compiler's builtins. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie6c83e5ed0c331fc14a7f6092dae6220ba20cd54 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324815 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* terrador: support TBT/USB4 for C0/C1 portDavid Huang2020-08-171-26/+0
| | | | | | | | | | | | | Enable C0/C1 port BUG=b:160741783 BRANCH=none TEST=Check TBT and USB4 are working at Gen3 speed. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I4e1dd919a0ca35277a95b86eba0ae58db837d31d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2342947 Reviewed-by: Keith Short <keithshort@chromium.org>
* Clean up: set embedded flash clock 48MHz as defaultRuibin Chang2020-08-176-10/+2
| | | | | | | | | | | | | | | | For chip it8xxx2 series and it8320dx, we set embedded flash clock 48MHz as default. BUG=none BRANCH=none TEST=build all Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I100d70fbf80430ae98fa14c557886c4a37d8b93a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355164 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* Karma: Add PANEL_LM_SSM1 panel settings to OZ554Sue Chen2020-08-171-0/+7
| | | | | | | | | | | | | | | | | add panel id 0x06 for PANEL_LM_SSM1. Modified initial setting: offset = 2, data = 0x46 offset = 5, data = 0x87 BUG=b:162909856 BRANCH=kalista TEST=make buildall; PANEL_ID and oz554 setting are correct for the new panel Change-Id: Ia74e3911b05efdf35ada1d2d28484fba5293aa95 Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2346084 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* pompom: Modify standard reference of accel sensorsAlvinCC_Hsu2020-08-171-3/+3
| | | | | | | | | | | | | | | | This patch modify standard reference of base and lid accel sensors BUG=b:160750560 BRANCH=none TEST=execute ectool motionsense to get values Signed-off-by: AlvinCC_Hsu <alvincc_hsu@compal.corp-partner.google.com> Change-Id: I227aa694061f4c77d3d5836a0a8375a682b598a9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2348235 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
* syv682x: Set SYV682X HV_ILIM depend on sink path.David Huang2020-08-171-0/+2
| | | | | | | | | | | | | Set syv682x HV_ILIM when source path enable. BUG=b:161762373 BRANCH=master TEST=Use ppc_dump <port> to check the setting correct. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I3443762654244e1289700d57acff1c646eb5e66f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2316176 Reviewed-by: Keith Short <keithshort@chromium.org>
* Drawcia: Limit C1 current on board version 0Diana Z2020-08-151-0/+8
| | | | | | | | | | | | | | | | | Due to thermal concerns, current on C1 will be limited to 2.0 A on board version 0. BRANCH=None BUG=b:161942987 TEST=on drawcia, plug charger into C1 and verify that the input current limit is set to 2.0 A Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I66ca0cb095f62c05a7e649b018e4b7b72aa36726 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2341650 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* drawcia: Enable OCPCAseda Aboagye2020-08-152-0/+22
| | | | | | | | | | | | | | | | | This commit enables OCPC for the Draw* boards. Default constants and resistances are the same as waddledee. BUG=b:161863872 BRANCH=None TEST=Build and flash on drawlat. Verify that DUT can charge from the sub board. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I6b95fc0e9fdb6c758fda5509c29da9059d75642e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2330818 Reviewed-by: Diana Z <dzigterman@chromium.org> Tested-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* waddledee: Enable OCPCAseda Aboagye2020-08-152-0/+24
| | | | | | | | | | | | | | | | | | This commit enables OCPC for waddledee which allows charging from the sub board port. BUG=b:161898184 BRANCH=None TEST=Build and flash waddledee, verify that DUT can charge from the sub board. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I61fbdfa0f7c06f0c2fb70aa5cbd92bb6b7f76cfd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2330817 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* sm5803: Add support for OCPCAseda Aboagye2020-08-152-11/+158
| | | | | | | | | | | | | | | | | | | | | | | | This commit updates the SM5803 driver to add the required functionality for supporting OCPC. As this part does not have the ability to measure ISYS, one needs to make sure that flag is set in the OCPC chg_flags bitfield. Currently, sourcing out the mainboard port while charging through an auxiliary charger is not working. BUG=b:155224387 BRANCH=None TEST=Enable on waddledee, flash, verify DUT can charge thru the sub board port. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I7b60dec51e503c83a24799d523eb75408f91ce86 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2336175 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Justin TerAvest <teravest@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* task: Change mutex_lock() assertEdward Hill2020-08-155-26/+18
| | | | | | | | | | | | | | | | | | | Instead of asserting that task_start() has not been called, just return without doing any locking. This avoids the need to fix every caller of mutex_lock() to check task_start_called(). BUG=b:164461158 BRANCH=none TEST=Esc+F3+Power enters recovery, does not assert. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ic157d7e7041185a67f257f0f5710fd02e45cd77f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357496 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* tglrvp: Enable early firmware selection EFS2Vijay Hiremath2020-08-153-3/+7
| | | | | | | | | | | BUG=none BRANCH=none TEST=Software sync enabled Coreboot selects EC RW at early stage Change-Id: Ib10a15b8e0b006ea830fe1b07725bf4e8ce4591f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351624 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* fingerprint: Stopgap to repair public buildsCraig Hesling2020-08-152-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This repairs building bloonchipper and dartmonkey builds when private lib is unavailable. There are two issues this remedies: 1) Redefinition of sensor info macros, like FP_SENSOR_RES_X 2) Undefined reference to fp_sensor_maintenance when building bloonchipper/dartmonkey non-private image. All of these issues stem from the way we handle code when HAVE_FP_PRIVATE_DRIVER is set or faked by a test. This is a fundamental issues that needs some thought and refactoring. BRANCH=none BUG=b:164174822,b:163109916, b:163411883 TEST=# With private time make buildall -j TEST=# Without private time make buildall -j TEST=# With private libs # Cherry-pick https://crrev.com/c/2357870 first, then # this patch. ./util/compare_build.sh -b all -o # This confirms that the all output binaries with private-lib # did not change at all Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: If71e3376fb7a904b77f2fc9fc56c8e0daf54db3b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357430 Reviewed-by: Andrew de los Reyes <adlr@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org>
* SM5803: Switch to using charger detect interruptDiana Z2020-08-141-28/+28
| | | | | | | | | | | | | | | | | | | | | | | Charger detect interrupt appears to be more robust at signaling when a non-PD chrager has been inserted than the Vbus levels. This change switches the driver over to that indication and disables the Vbus threshold interrupt. Note there are still some power role swap issues present with this change, but not more than on current ToT. BRANCH=None BUG=b:163136683,b:161566084 TEST=on waddledee, verify: -Suzy-q is detected as a charger on both ports -45W charger is detected as a charger on both ports -HooToo hub is detected as a charger after power role swap Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I85776f4a79413ca1b0eb454e03ccf2a6f8466ca3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2349284 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* endeavour: fix PSE init timingJeff Chase2020-08-141-10/+10
| | | | | | | | | | | | | | | | | | | | The PSE controller is unpowered when the AP is not running so it should be initialized whenever the AP resumes. It can take up to 15ms after coming out of reset to respond to I2C accesses so retry as needed. BRANCH=endeavour BUG=b:162311755 TEST=EC reboot with various options. Cr50 reboot. Shutdown/power on. Change-Id: Ic4df0c2ded2c47b30e6ddea945158f664bb77efb Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2332859 Reviewed-by: Joe Tessler <jrt@chromium.org> (cherry picked from commit 8c5e48f0c7a1d6cd6bf39ab2e6278c6a42e72a4d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355491 Reviewed-by: Jett Rink <jettrink@chromium.org>
* System: Set stay-in-RO reset flag for sysjump and host commandDiana Z2020-08-141-3/+14
| | | | | | | | | | | | | | | | | | With EFS2, the EC can jump itself straight from RO to RW without AP intervention. However, sometimes the AP or a developer may want the EC to remain on RO to perform operations there. In these cases, set the reset flag to say in RO. BRANCH=None BUG=b:161887378 TEST=on waddledee, run "sysjump ro/rw" while the AP is on and confirm the AP remains on. Run "flashrom -p ec -w /tmp/ec.bin" and confirm the operation completes successfully. Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I036bd04514858a55e4e52abfc05eb67896436505 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2354742 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: motion_sense: Add on-body/off-body detectionGwendal Grignou2020-08-142-0/+20
| | | | | | | | | | | | | | | | This CL adds the interface for on-body/off-body detection - state: 1 : on-body, 0 : off-body. When activity is enabled, EC sends an event when the body detection changes. The host can now query the current value of the activity. BRANCH=None BUG=b:123434029 TEST=compile Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I007a5fe6c9030ab5c0c47995db3498751218d9c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2229803
* sysrq: Ignore H1_EC_RECOVERY_BTN_ODLDaisuke Nojiri2020-08-141-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On Puff, there are two signals from the recovery button. One is from the button and the other is from H1. The signal from H1 is masked by the power button and it looks asserted only after the power button is released. This makes the EC start the warm reset timer. If the user doesn't release the recovery button (as instructed) to enter the recovery mode for four seconds, the AP resets and entry to the recovery mode fails. This patch makes the EC ignore H1's signal as sysrq signal. BUG=b:163443447 BRANCH=Puff TEST=Recovery mode can be entered by keeping recovery button pressed on Duffy. TEST=Recovery button triggers sysrq. TEST=Holding recovery button for 4 seconds triggers AP reset. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I8631d5dc0da8c95eed1d740b0683aa5de7848335 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2353890 Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Sam McNally <sammc@chromium.org>
* VIF: add \n to separate two linesRuibin Chang2020-08-141-1/+1
| | | | | | | | | | | | | | | | The generated VIF, USB_PD_Support and PD_Port_Type field stick together, so I add \n to separate two lines. BUG=none BRANCH=none TEST=check USB_PD_Support and PD_Port_Type field are separated. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I43453301751523d0005022d039e640ac06244910 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355633 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Sam Hurst <shurst@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/spi: enable rx valid length interruptDino Li2020-08-143-0/+50
| | | | | | | | | | | | | | | | | | | | | Enable IT83XX_SPI_RX_VALID_INT which can obtain data length field of host requested. When received data to reach, Rx valid interrupt will be fired then start to parse. Instead of waiting for Rx 256 bytes reach interrupt method, this is effectively saving time to complete once transaction. BUG=b:160662061; b:161509047 BRANCH=none TEST=Boot to kernel with it81202 on asurada. No error on the command of get EC protocol info with 1MHz clock frequency. Change-Id: Ib56e3034d3ee39fa64818b95747eb7e9e5821294 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076826 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org>
* Bobba: set SYV682X HV_ILIM to 5.5ADavid Huang2020-08-141-0/+2
| | | | | | | | | | | | | | | Set CONFIG_SYV682X_HV_ILIM to 5.5A on bobba. BUG=b:161762373 BRANCH=master TEST=Use ppc_dump <port> to check the setting correct. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I87f38ddd65f1908e230110f3ba2bc0f4e1a73057 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2315952 Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Marco Chen <marcochen@chromium.org>
* syv682x: set CONFIG_SYV682X_HV_ILIM for set HV_ILIMDavid Huang2020-08-142-1/+7
| | | | | | | | | | | | | | | | Use CONFIG_SYV682X_HV_ILIM for board define default support HV_ILIM value. BUG=b:161762373 BRANCH=master TEST=Use ppc_dump <port> to check the setting correct. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: Ifc37fb273e769e3d3555a04fb1da13946821d19a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2315948 Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Marco Chen <marcochen@chromium.org>
* it83xx/adc: Enable automatic hardware calibrationDino Li2020-08-142-0/+3
| | | | | | | | | | | | | | We missed it when ADC accuracy initialization, let's fix it. BUG=b:164011390 BRANCH=none TEST=ADC accuracy is in +/- 4LSB. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id40adbdc6823fbf3db506681ce4bff6a2f32b843 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355166 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Parker Lin <parkerlin@google.com>
* trogdor: Support AP-control LEDJian-Jia Su2020-08-142-3/+6
| | | | | | | | | | | | | | Respect led_auto_control_is_enabled when setting the LED color. BUG=b:164019439 BRANCH=none TEST=ectool led <led_id> <color>|auto Signed-off-by: Jian-Jia Su <jjsu@chromium.org> Change-Id: Iac11c504c42da489c2d8bf2d970a66e059ed0684 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2352967 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* voxel: Configure unused GPIOs as inputsBen Chen2020-08-141-0/+17
| | | | | | | | | | | | | Configure unused GPIOs as inputs to save power in deep sleep states. BUG=b:162592971 BRANCH=none TEST=make buildall Change-Id: I1cc6330268b269bb9f337913335f055056b3800a Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335526 Reviewed-by: Keith Short <keithshort@chromium.org>
* ps8xxx: support multiple chips in the runtimeMarco Chen2020-08-143-119/+297
| | | | | | | | | | | | BUG=b:159082424 BRANCH=none TEST=verify the same EC image can work on devices with PS8751 or PS8755 for src / snk roles. Signed-off-by: Marco Chen <marcochen@chromium.org> Change-Id: I3a743666a4ccbcae37ecb6f0d6657122cf9c5a69 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2304237 Reviewed-by: Jett Rink <jettrink@chromium.org>
* COIL: change usage of sanityDaisuke Nojiri2020-08-143-10/+8
| | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "sanity" with inclusive alternatives. BUG=b:163885307 BRANCH=None TEST=make -j buildall TEST=grep -ir sanity Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I487a50999d506a0337f1d3fbe173f193e5e4098a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2353516 Reviewed-by: Sam Hurst <shurst@google.com>
* CBI: Make test fail if a tag is missing from unit testDaisuke Nojiri2020-08-141-0/+35
| | | | | | | | | | | | | | This patch adds a check in the unit test which fails if there is a tag missing from test_all_tags. This will force developers to pay attension to the unit test when adding a new tag. BUG=none BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I34d054493e16454c3662b289eaa6d4de362a26f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2354200
* cleanup/usbc: organize all super states togetherJett Rink2020-08-132-34/+35
| | | | | | | | | | | | | | Like other state machine declarations, put all of the super states together to make it more clear when reading states. BRANCH=none BUG=none TEST=build and unit tests Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I1bb776434911d3acdb34abc64e7e8fa5f87154de Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2354193 Reviewed-by: Edward Hill <ecgh@chromium.org>
* usbc: add GEN_NOT_SUPPORTED macro for unsupported statesJett Rink2020-08-135-66/+41
| | | | | | | | | | | | | | | | | | | To enabled use of the IS_ENABLE macro we need to define some of the usb state machine states as extern variables that will never be linked. This allows the compiler to know about a state but will still fail the linking phase if the config option is not defined properly. This is just adding a convenience macro for this paradigm, not creating the paradigm itself. BRANCH=none BUG=none TEST=builds Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: Ia19b5babd43d536f043745314481475cf25f6e01 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2353369 Reviewed-by: Edward Hill <ecgh@chromium.org>
* test: remove no_empty_state testsJett Rink2020-08-137-73/+0
| | | | | | | | | | | | | | | | When we use IS_ENABLED style code we may have empty state machine states that are unused. The linker ensures that we never try to reference these states. This does mean that extra states do cost ~20 bytes each. This cost does seem worth it to keep the value of usb states stable. BRANCH=none BUG=none TEST=buildall Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I44c1454bed91c9e28d89ebd6b75e9df684c41844 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2354192 Reviewed-by: Edward Hill <ecgh@chromium.org>
* tcpmv2: wait before enabling HW auto toggleJett Rink2020-08-135-5/+59
| | | | | | | | | | | | | | | We need to ensure that the previous Rd or Rp has been held long enough before we transition into hardware auto toggle otherwise the first toggle might be too short and violate the DRP timing spec BRANCH=none BUG=b:163095971 TEST=Verify on scope Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I92e9f5ca7dbca2b347e438d774551cc11476195b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2343176 Reviewed-by: Edward Hill <ecgh@chromium.org>
* cbi: add Second Source Factory Cache (SSFC) CBI fieldMarco Chen2020-08-136-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | SSFC field will be leveraged to record what second source is used in the DUT by probing components in the factory or RMA. Firmware code should refer to this field to judge what driver should be configured for a specific component. For example, the board code can arrange what sensor driver should be set into motion_sensors array if there are multiple sources of base or lid sensor. As the definition of FW_CONFIG, it describe which "features" the firmware code should enable or disable. For example, whether lid / base sensors should be enabled or not but not care about what second source is in this DUT. BRANCH=none BUG=b:163285687 TEST=call `cbi-util` to create the cbi image with SSFC and show created content. TEST=`make buildall -j` TEST=`make runhosttests -j` Change-Id: Icb4aa00ae47ab025198e7fd5edd6aab96a4bf53e Signed-off-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2344268 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* ANX3429: Disallow PD 3.0 operationDiana Z2020-08-131-0/+5
| | | | | | | | | | | | | | | The ANX3429 was developed before the PD 3.0 specification and is not PD 3.0 compliant. Disallow building this driver with PD 3.0 enabled. BRANCH=None BUG=b:159253723 TEST=make -j buidall passes; configure eve for PD 3.0 and see it fails Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I1d46d313f2914e98180e9a599b8ccdeb430afdef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2354629 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* casta : change battery voltage maxYongBeum Ha2020-08-131-1/+1
| | | | | | | | | | | | | | | change battery voltage max to 8650mV BUG=b:163453304 BRANCH=master TEST=flash EC and check battery charging. Signed-off-by: YongBeum Ha <ybha@samsung.com> Change-Id: Ie98ec604b5ebca25cff693542e1e65452bcf1e57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2352960 Reviewed-by: Justin TerAvest <teravest@chromium.org> Commit-Queue: Justin TerAvest <teravest@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org>
* SM5803: Disable end of charge detectionDiana Z2020-08-131-2/+5
| | | | | | | | | | | | | | | | | | Since the fuel gague also provides end of charge detection, it's unnecessary for the charger chip to also perform this. Additionally, with the end of charge detection removed the board can now set auto charge bits regardless of whether the battery is connected without browning out. BRANCH=None BUG=b:163163442 TEST=on drawlat, verify booting without a battery does not brown out. Verify that after SW battery cutoff the battery is able to come back from disconnect reasonably quickly (within about 4 seconds post-boot) Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I57e77f5ea1860642ca565cd417ad9f14f7084b39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2352436
* dirinboz: add battery supportZick Wei2020-08-132-65/+154
| | | | | | | | | | | | | This CL add battery support for dirinboz: BUG=b:163713612 BRANCH=none TEST=verify battery can charge/discharge/cut off. Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: If997582dc3d315a3e5ff0273d2992c4f2d504e62 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351731 Reviewed-by: Edward Hill <ecgh@chromium.org>
* init_rom: Add init_rom layerKeith Short2020-08-134-1/+127
| | | | | | | | | | | | | | | | | | | Create a thin init_rom layer for accessing data objects linked into the .init_rom section with the CONFIG_CHIP_INIT_ROM_REGION opton and __init_rom attribute. BUG=b:160330682 BRANCH=none TEST=make buildall TEST=Using the next CL, verify BMI260 config data can be read using both memory mapped and indirect access. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I6cd311637e87cd10ac394ff75c4bfc16bbade3b0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335739 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* npcx: add support for rom resident sectionsKeith Short2020-08-139-3/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC images are copied in full from flash to RAM. When the code RAM size is smaller than 1/2 the flash size, the EC image size is limited to the code RAM size, leaving unused flash space. Create a new linker section .init_rom used to store data objects that are single use in the previously unused flash area. Data objects can be used at runtime by copying into RAM using the flash_read() function. This change is tied to the NPCX flash layout, with asserts to ensure builds fail if the CONFIG_CHIP_INIT_ROM_REGION is not supported by the chip. CLs that enable CONFIG_CHIP_INIT_ROM_REGION should not be merged until the predecessor CL:2325764 is available in CPFE images. BUG=b:160330682 BRANCH=none TEST=make buildall TEST=With debug code, use the _init_rom macro and validate the data can be read using flash_read(). TEST=Using hex editor, verify .init_rom section located at 192K boundary and unused bytes are filled with 0xFF. TEST=compare_build.sh passes when run against waddledoo (npcx, cortex-m) Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ia0785798fd1938ad6a1c254a070b219027ee82a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311268 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* flash: allow programming larger EC imagesKeith Short2020-08-133-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some ECs, the EC image size is limited by the amount of code RAM instead of 1/2 the total flash size. In this instance, there is unused flash that can be used for single use data objects. To support linking data objects into the unused flash area, increase the region size that can be programmed for RW images. Analysis of chips that are impacted by this change: Chip EC image limit New RW size limit mec1701h 188 KiB 256 KiB mec17xx_2E00 188 KiB 256 KiB npcx5m5g 96 KiB 128 KiB npcx5m6g 224 KiB 256 KiB npcx7m6f 192 KiB 256 KiB npcx7m6fb 192 KiB 256 KiB npcx7m6fc 192 KiB 256 KiB npcx7m6g 192 KiB 256 KiB npcx7m7wb 256 KiB 512 KiB npcx7m7wc 252 KiB 256 KiB Boards using other chips verified that CONFIG_RW_SIZE is the same as CONFIG_EC_WRITABLE_STORAGE_SIZE. EC_FLASH_REGION_RO isn't used by depthcharge, only EC_FLASH_REGION_WP_RO which is already set to the correct size. BUG=b:160330682 BRANCH=none TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I84b9dc84568273e1ab1473e301d27ffd2b07ba7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2325764 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* casta : set a charging voltage limitYongBeum Ha2020-08-131-0/+6
| | | | | | | | | | | | | | | limit charging voltage to battery voltage max BUG=b:163453304 BRANCH=master TEST=flash EC and check battery charging. Signed-off-by: YongBeum Ha <ybha@samsung.com> Change-Id: I5f82f71392bfade3a4b5aa288cf5ba19687556f3 Signed-off-by: YongBeum Ha <ybha@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351645 Reviewed-by: Henry Sun <henrysun@google.com> Commit-Queue: Henry Sun <henrysun@google.com>
* dirinboz: update DB settingZick Wei2020-08-133-183/+17
| | | | | | | | | | | | | | This CL remove unuse DB code for dirinboz. BUG=b:159598016 BRANCH=none TEST=verify DB function: DP/USB3.0 can work. Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: Ic6b62a2f2d5428b9b88dc4bd06e099f10e083e03 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2327360 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* baseboard/dedede: Enable AP reset command handlerKarthikeyan Ramasubramanian2020-08-131-0/+6
| | | | | | | | | | | | | | | | | | | | TPMs with old firmware version cannot detect AP initiated reset eg. AP gets reset when CSE Lite SKU jumps from RO to RW. Enable AP reset command handler so that AP can request EC to perform the reset. This will lead to TPM detecting the AP reset. BUG=b:162386991 BRANCH=None TEST=Ensure that the EC handles AP reset command. Ensure that the device boots to OS after the reset. Change-Id: I1e167af89aaa28c731674ee3650904d702efc8df Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2337430 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* voxel: remove ALS motion sensor functionBen Chen2020-08-134-112/+2
| | | | | | | | | | | | | remove light sensor function of TCS3400 BUG=b:162940877 BRANCH=none TEST=make buildall. Change-Id: I8ceeac4084b6b369b19d53f40f15d198c3964816 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2344265 Reviewed-by: Keith Short <keithshort@chromium.org>
* stm32g4: Add I2C supportScott Collyer2020-08-132-11/+472
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the i2c driver for stm32g4 chip family. The i2c block for stm32g4 is very similar to that of stm32l4 chip family. The g4 driver is mostly copied from the L4 version of the i2c driver. However, the driver only currently supports master mode. BUG=b:148493929 BRANCH=None TEST=run i2scan on EC console > i2cscan Scanning 0 usbc................. 0x18. 0x19. 0x1a. 0x1b. 0x1c. 0x1d. 0x1e. 0x1f. 0x20. 0x21. 0x22. 0x23. 0x24. 0x25. 0x26. 0x27........................... 0x42.............................. 0x60....................... Scanning 1 usb_mst. 0x08. 0x09. 0x0a. 0x0b. 0x0c. 0x0d. 0x0e. 0x0f. 0x10. 0x11. 0x12. 0x13. 0x14. 0x15. 0x16. 0x17... 0x1a........................... 0x35............ 0x41......... 0x4a. 0x4b...................... 0x61...................... Scanning 2 eeprom......................................... 0x30................................ 0x50....................................... Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Id8b7472e579bae17360a0122fe2b12a333139cfa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2161580 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Fix max clock freq and flash wait stateScott Collyer2020-08-131-5/+5
| | | | | | | | | | | | | | | | | | | | | The clock frequency macro added in previous CL was missing the '0'. This CL fixes that error and makes a minor change to how the flash wait state value is configured. Previously, setting of the wait state field was disabling instruction/data cache until it was restored in the next instruction. This results in swd debugger not remaining attached. BUG=b:148493929 BRANCH=None TEST=verified console is working and debugger remains attached after setting wait state to the correct value. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I65e3a22e36de0bbf14926e5687a995b7e5717e7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340695 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* kindred: modify power button timeoutben.chen2@quanta.corp-partner.google.com2020-08-131-0/+2
| | | | | | | | | | | | | | | | ensure wake up from MURATA battery takes some seconds, to come back out of its disconnect. Setting CONFIG_POWER_BUTTON_INIT_TIMEOUT to 2 second. BUG=b:146914669 BRANCH=hatch TEST=check power on, plug in AC after battery cutoff Change-Id: I55e1f1957ebbe6800cf01e347e9ed29d57ab1280 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1984153 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* sc7180: Don't neglect the delay in a forced shutdownWai-Hong Tam2020-08-131-3/+3
| | | | | | | | | | | | | | | | In a forced shutdown, it just waits the POWER_GOOD drop to low, but not wait the SYSTEM_POWER_ON_DELAY. If AP requests EC reboot at shutdown, EC reboots immediately right after turns off the switchcap. Better to delay a bit. BRANCH=None BUG=b:156981868, b:163613549 TEST=After switching from normal to dev mode, AP boots normally. Change-Id: Iae300aa03dd0a991f62742159613377fe2388760 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2352440 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* willow: Support new battery AP18C8K/AP18C4KDavid Huang2020-08-132-0/+58
| | | | | | | | | | | | | Add new battery config : AP18C8k/AP18C4K. BUG=b:163283354, b:163283566 BRANCH=master TEST=Check found battery info in console and cutoff work. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I3d03c85414dfb4a26bbb389860bf4ebf512b0e27 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2344267 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
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