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* zephyr: enable sysjump console commandstabilize-13799.B-mainYuval Peress2021-02-182-0/+17
| | | | | | | | | | | | | | | Enables the sysjump console command. With this enabled, it is now possible to run `sysjump RW` and `sysjump RO` in the EC console and jump between images. BRANCH=none BUG=b:167392037 TEST=build/flash volteer, then run `sysjump` commands followed by both `sysinfo` and `version`. Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: If984ca6b78b01f6884f551c8af730632c340828f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2695958
* zephyr: delbin: enable power button moduleJack Rosenthal2021-02-182-1/+5
| | | | | | | | | | | | | | Enable power button code and interrupt. BUG=b:180410072 BRANCH=none TEST=press power button, observe UART prints Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I83d7ab66bd7448d2e87e21dce9281c7b1246ca87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699531 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: implement cortex-m's interrupt_disable()Yuval Peress2021-02-182-10/+13
| | | | | | | | | | | | | | | | | | Add implementation in lieu of Zephyr APIs. Zephyr's support for irq_disable() doesn't disable all interrupts (see Zephyr's include/arch/arm/aarch32/asm_inline_gcc.h for more information). The implementation is done via a #define inside the system.c file, this is done on purpose to avoid leaking the interrupt_disable() functionality outside of sysjump. All other uses of disabling interrupts should be done via irq_lock(). BRANCH=none BUG=b:174481378 TEST=build/flash volteer, run sysjump command Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Idccb93211296f81796ce4ba200c62adc5c19e691 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2695959
* cortex-m0: convert "b" register constraints to "l"Peter Marheine2021-02-181-4/+4
| | | | | | | | | | | | | | | | | | GCC defines the "b" constraint for ARM targets as the union of the stack register and low registers (r0-r7), but that constraint is marked as internal (not intended for general use) and is not supported by Clang. Instead use "l" (the low registers only), which is intended for general use and supported by clang. BUG=b:172221010 TEST=builds BRANCH=None Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I584274b2aa1c68dfdfef80de779191d1f4d0e7b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2695054 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* zephyr: initialize the system codeYuval Peress2021-02-182-0/+7
| | | | | | | | | | | | | | | | | | | | At present the data pointer is not valid and we're not able to store any data between jumps. Fix this by adding a call to system_common_pre_init(). Add an empty test implementation so that tests still pass BRANCH=none BUG=b:167392037 TEST=zmake testall TEST=build/flash volteer, make sure that jdata was set up correctly (it is at the end of the data RAM address). Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I8e948b68484927fa0da9f7d4db00ff339c22bae2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2695957 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: cortex-m: Add software panic supportYuval Peress2021-02-176-2/+98
| | | | | | | | | | | | | | | Software panic implementation is needed to support system.c's system_common_pre_init. For reference, this code was taken from core/cortex-m/panic.c. BRANCH=none BUG=b:167392037 TEST=zmake testall Change-Id: I91232b297c9933d48e3b7c59d7d8befe84cdecc5 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2693687 Reviewed-by: Keith Short <keithshort@chromium.org>
* RT1715: Enable power saving modesEric Herrmann2021-02-172-33/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The RT1715 implements its own low-power mode (LPM) to save power. Switch from using the default I2CIdle LPM to using the RT1715-specific one. Disable the 24MHz oscillator in LPM, and enable the interrupt to wake from LPM. For interrupts, clear the WAKEUP interrupt before checking the TCPCI interrupts. Enable auto-idle to save power with a device connected. Disable when the TCPC is sourcing Vconn. BUG=b:179256608 TEST=On Voxel: while no device attached, make sure both SNK and SRC devices wake up the TCPC from LPM TEST=On Voxel: with no devices connected, measure fake G3 power consuption and make sure it has decreased TEST=On Voxel: with a pass-through hub configured as a sink, check that connecting a charger will prompt Voxel to begin charging TEST=make buildall BRANCH=None Change-Id: Ifb2fa5a7940e5862e217c04c5c1082aae6b43989 Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2676934 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* volteer: disable hostcmd console channelKeith Short2021-02-171-0/+6
| | | | | | | | | | | | | | | | Disable the hostcmd console channel on Zephyr EC builds to match the Chromium EC setting. BUG=b:180421120 BRANCH=none TEST=make buildall TEST=zmake testall TEST=On Volteer, verify "hostcmd" channel is disabled by default Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I049acc6b2f54c14774139151ba032b5582aba368 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698269 Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: add support for disabling console channelsKeith Short2021-02-174-0/+72
| | | | | | | | | | | | | | | | Add support in the device tree for disabling console output channels by default. BUG=b:180421120 BRANCH=none TEST=make buildall TEST=zmake testall TEST=On Volteer, verify "hostcmd" channel is disabled by default Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I9fa1fe78ee3927346ede8e75378260f6061075cd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698268 Reviewed-by: Simon Glass <sjg@chromium.org>
* flash_jlink: Pythonify the ip checkCraig Hesling2021-02-171-1/+1
| | | | | | | | | | | BRANCH=none BUG=none TEST=./util/flash_jlink.py --ip '' --board=nucleo-h743zi --image ./build/nucleo-h743zi/ec.bin Change-Id: Ibe5ec4d64173c83be837bcd08143d57a1d354d15 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2701193 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* flash_jlink: Add nucleosCraig Hesling2021-02-171-0/+3
| | | | | | | | | | | | | BRANCH=none BUG=none TEST=./util/flash_jlink.py --ip '' --board=nucleo-h743zi --image ./build/nucleo-h743zi/ec.bin TEST=./util/flash_jlink.py --ip '' --board=nucleo-dartmonkey --image ./build/nucleo-dartmonkey/ec.bin TEST=Can't test nucleo-f412zg, but confirmed the spelling is correct. Change-Id: I4d09bddb7640c74b8803b48530d243111940d2e1 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2701192 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* zephyr: add a unimplemented GPIOs mechanismJack Rosenthal2021-02-172-11/+11
| | | | | | | | | | | | | | | | | | | | | ECOS allows certain GPIO names to go without an implementation (underlying pin) by using the UNIMPLEMENED(...) macro in gpio.inc. This allows for certain pins to go without an implementation that common code relies on. Reads and writes to these pins are harmless. This adds a GPIO_UNIMPLEMENTED signal that can be used in gpio_map.h to create similarly-functioning unimplemented pins. BUG=b:176559881 BRANCH=none TEST=add unimplemented GPIO_PCH_DSW_PWROK to delbin Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I74884f6a05f9ad30225c6953d3eee748c80cdc00 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699533 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: move select on HAS_TASK_POWERBTN to PLATFORM_EC_POWERSEQ_INTELJack Rosenthal2021-02-172-1/+1
| | | | | | | | | | | | | | | | | | | | | common/power_button.c (enabled by PLATFORM_EC_POWER_BUTTON) does not use or require the POWERBTN task. The POWERBTN task is required by common/power_button_x86.c instead, which is enabled by PLATFORM_EC_POWERSEQ_INTEL. Thus, there should not be a reverse dependency on the POWERBTN task for PLATFORM_EC_POWER_BUTTON, and this select was moved to the correct location. BUG=b:180410072 BRANCH=none TEST=compile for delbin with follow-up CL (enables the power button) Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Icf7c89ad006c2c32cdc1f0f77ecff0c42fa6dab2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699530 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: delbin: enable lid switchJack Rosenthal2021-02-172-1/+5
| | | | | | | | | | | | | | Enable the lid switch and interrupt. BUG=b:180410072 BRANCH=none TEST=open and close lid switch, observe UART prints Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I76455e73a310a6c9ce3e4de8094ca5a2cef516a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699529 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: delbin: enable external power detection via GPIOJack Rosenthal2021-02-172-0/+3
| | | | | | | | | | | | | | | Delbin uses external power detection thru acok_od GPIO. Enable the corresponding module. BUG=b:180410072 BRANCH=none TEST=compile for delbin Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I577f465938625d67d14df4c4afe892b04dc75412 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699528 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: delbin: bring up eSPIJack Rosenthal2021-02-172-1/+4
| | | | | | | | | | | | | | Enable eSPI and host commands. BUG=b:180410072 BRANCH=none TEST=run "hostevent" on delbin Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I2422b02dd8a2ece58793b10beed213ee00c8f418 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699527 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: delbin: implement gpiosJack Rosenthal2021-02-172-6/+291
| | | | | | | | | | | | | | Auto-generated the DTS from boards/delbin/gpio.inc. BUG=b:180410072 BRANCH=none TEST=flash on delbin, run "gpioget" Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id81f285a067d95d07d2de8fde18031001dbd1622 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698786 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: initial delbin bringupJack Rosenthal2021-02-1711-0/+271
| | | | | | | | | | | | | | | | | Initial project files for delbin supporting only basic UART functionality. More features to come! BUG=b:180410072 BRANCH=none TEST=flash to delbin, test basic uart functionality Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I115ef9b976adb50d29170656c39994ab039865c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698267 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* eldrid: modify charger current limit and ACPorchot#Terry Chen2021-02-171-5/+4
| | | | | | | | | | | | | | | | | | Enlarge ACProchot# to prevent prochot keep triggering fan spin max rpm. And set the same current limit when S0 and S5. BUG=b:178869017 BRANCH=firmware-volteer-13672.B-master TEST=make buildall TEST=test pass by power team Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I739b42453e796c3cc04657adbf84e96dc26abeb5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2671261 Tested-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* lindar: change TCPC to RT1715reno.wang2021-02-172-3/+5
| | | | | | | | | | | | | | | Replace the TUSB422 driver/I2C address with the RT1715. BRANCH=firmware-volteer-13672.B BUG=b:177980430 TEST=make buildall -j 1. Test Type-C PD function for AC, dock, usb device, etc. Signed-off-by: reno.wang <reno.wang@lcfc.corp-partner.google.com> Change-Id: Ied94898a50e0be643168031de8b2525b9dd04f15 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2666557 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* extra/util: replace deprecated sys_siglist with strsignalAdrian Ratiu2021-02-173-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Starting with Glibc 2.32: * The deprecated arrays sys_siglist, _sys_siglist, and sys_sigabbrev are no longer available to newly linked binaries, and their declarations have been removed from <string.h>. They are exported solely as compatibility symbols to support old binaries. All programs should use strsignal instead. https://sourceware.org/pipermail/libc-announce/2020/000029.html BUG=chromium:1171287 BRANCH=none TEST=Local builds on x86_64 / eve and arm / kevin. Sent SIGINT to iteflash and verified output. Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.corp-partner.google.com> Change-Id: I8b4deaf8743c806a9610863648b345be3b35e1b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698188 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Manoj Gupta <manojgupta@chromium.org> Tested-by: Manoj Gupta <manojgupta@chromium.org>
* nb7v904m : Add function to control Loss Profile MatchingYongBeum.Ha2021-02-172-0/+39
| | | | | | | | | | | | | | add function to control Loss Profile Matching BUG=b:176862264 BRANCH=None TEST=make -j BOARD=sasuke Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I5b4d0ff444c07c477add101fac05d33694a33982 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2684080 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* metaknight: Remove remnants of 2nd charger ICAseda Aboagye2021-02-173-78/+13
| | | | | | | | | | | | | | | | | This commit cleans up the remnants of a 2nd charger IC as metaknight does not plan to support one. BUG=b:169813211 BRANCH=dedede TEST=`make -j BOARD=metaknight` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I9368cd831cf134f39741a46f2a9ee511bdeeb7cc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698375 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* servo_v4p1: Fix BC1.2 detection pin assignment for REV2Jan Dabros2021-02-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | REV1 of servo_v4p1 uses HOST_CHRG_DET as a GPIO which informs about detecting extended-charge connection available (CDP or DCP). On REV2 BC1.2 detection chip was replaced with another part (PI3USB9201) and this pin is asserted when detection is completed. STM needs to query I2C interface of BC1.2 chip in order to get detailed info about available power. HOST_CHRG_DET on REV2 should be used as a trigger for reading PI3USB9201 detection results. This will be implemented in future. BUG=b:144776402 BRANCH=main TEST=build and flash servo_v4p1. After reboot, connect to console and verify that there is no "BC1.2 charger unplugged" message visible in the log. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I421a82d5496b6e5280f5023878c610d04fae9283 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2697071 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Revert "servo_v4p1: Add driver for power management"Jan Dabros2021-02-178-154/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4f8c2db072fb4a8a99ccdc9fa557f122582f8173. servo_v4p1 uses charge_manager, however currently this is done improperly. Instead of HOST and ALT ports, CHG and DUT ports are registered withing framework, even though they are not used for charging servo platform itself. In order to implement power management, the most convenient (and clean) solution is to use charge_manager API. The plan is to make use of it, however first we need to address charge_manager problem mentioned above. This way we will avoid code duplication and custom drivers which duplicate existing generic implementation. For the time being, revert custom power management. After fix for charge_manager on servo_v4p1 is applied, will get back to this issue and re-apply power management features in new form. BUG=b:144776402 BRANCH=main TEST=build and flash servo_v4p1. After it boots, issue `ina 2` command. By default the Alert limit should be equal to 0, which means that now power restrictions are applied. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I8aea351331dd380fc13c5c6c43ea7dc3a29bd918 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2697070 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: volteer: enable temperature sensorsDawid Niedzwiecki2021-02-172-0/+28
| | | | | | | | | | | | | | | | Configure temperature sensors in Volteer. BUG=b:174851465 BRANCH=none TEST=build Zephyr for Volteer TEST=Run "temps" command, it should return the current temperature measurements Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I30df8432785fef1e5ad84f8f5818fe7920a5ea90 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2687219 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: add shim temperature sensorsDawid Niedzwiecki2021-02-1713-0/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | Add temperature sensors shim. Use platform/ec the temperature sensors drivers. Generate needed global variables/types: enum temp_sensor_id and temp_sensors from dts. Each temperature sensor type has its own compatible property to assign a correct read function in the temp_sensor_t temp_sensors[] array. Themrmisors has also adc property to point an ADC channel connected to the sensor. Enable "temps" console command and EC_CMD_TEMP_SENSOR_GET_INFO host command. BUG=b:174851465 BRANCH=none TEST=build Zephyr TEST=Run "temps" command, it should return the current temperature measurements Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ie680ec0771ea3da598066eb98db80944a93daca5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2687218 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* sasuke : add WA to connect CCDYongBeum.Ha2021-02-172-0/+60
| | | | | | | | | | | | | | add WA to connect CCD BUG=b:179624712 BRANCH=none TEST=make -j BOARD=sasuke Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I402ed1d955c1104a049c2c2e73fa26348a627bca Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2684077 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nb7v904m : add function to control aux channelYongBeum.Ha2021-02-172-0/+11
| | | | | | | | | | | | | Add function to control aux channel BUG=b:179624712 BRANCH=none TEST=make -j BOARD=sasuke Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I0dd474b52ee9058bfed3c7caec07e691d41f84dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699468 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nb7v904m : add config to disable LPMYongBeum.Ha2021-02-173-0/+14
| | | | | | | | | | | | | | Add config to disable LPM BUG=b:179624712 BRANCH=none TEST=make -j BOARD=sasuke Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I6ae0d08709fe0799843b6e225b480ffa617dfe84 Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2684075 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: Add common hpd->dp_atten converterScott Collyer2021-02-174-2/+419
| | | | | | | | | | | | | | | | | | | | | | | This CL adds a new file for UFP_D ports. The inclusion of this file is controlled via a new config option CONFIG_USB_PD_ALT_MODE_UFP. Note that this is not intended to be used with TCPMv1 UFP_D legacy devices. The initial version of this file includes the hpd to usb pd DP_ATTENTION message converter. The implementation follows the spec in terms of both states and hpd event queueing rules. BUG=b:175660576 BRANCH=None TEST=Tested further down the CL stack. But verified that this CL fixes the issue where too many hpd_irq messages are sent with gingerbread which was causing a port part reset for chromebook ports. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I5c7f4a3d226eb7b33553c90f04c69c3d80bd8672 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2598028 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org>
* Magolor: report the numeric pad capability to APBen Chen2021-02-171-0/+45
| | | | | | | | | | | | | | | | Switch fw_config supports the numeric pad, we need to report the KEYBD_CAP_NUMERIC_KEYPAD to the AP. BUG=b:178921361 BRANCH=dedede TEST=numeric pad key event can be recognized by evtest. Change-Id: I4a0aa5ac6420063651cf7e4cfef82e861645ba6e Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2679089 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* magolor and friends: Adjust OCPC PID constantsAseda Aboagye2021-02-175-84/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | Thus far, it seems that boards that use the same OCPC PID constants behave similarly. Therefore, this commit updates the constants that were most recently used on madoo to the other OCPC boards that use the same charger IC such that the behaviour meets the criteria at go/ocpc-testing. - Converges around the target current. - Average steady state error is less than 4% of target. - Current is reduced to target level in less than 5s when load is suddenly released. BUG=None BRANCH=dedede TEST=Build and flash magolor. Verify that battery can charge to 100%. Verify that it meets or exceeds the constraints above. TEST=Verify that DUT can come out of battery cutoff from sub board. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I206854c097c307b941a64547f9b74c8259a7d499 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2691585 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* TCPMv2: Update source Rp if no contract in placeDiana Z2021-02-161-1/+5
| | | | | | | | | | | | | | When no contract is in place, update our source Rp when a new current is selected on a port. BRANCH=None BUG=b:141690755 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie155353a4a6ab28957edff548747c47d96d840a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2692029 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv2: Refactor PD 3.0 check into FRS enableDiana Z2021-02-161-31/+24
| | | | | | | | | | | | | | | To reduce code indenting, add the check for CONFIG_USB_PD_REV30 into the pe_set_frs_enable function. Also move typec current limit setting into the FRS enable function. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Id272c40c447c799f299fb59294c77a1603ccc1c3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2692028 Reviewed-by: Keith Short <keithshort@chromium.org>
* fingerprint: Enable more on-device unit testsTom Hughes2021-02-167-1/+42
| | | | | | | | | | | | | | | | BRANCH=none BUG=b:155235321 TEST=On dragonclaw v0.2 with servo micro and jlink: ./test/run_device_test.py --board bloonchipper => tests pass TEST=On icetower v0.1 with servo micro and jlink: ./test/run_device_test.py --board dartmonkey => tests pass Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I884ee93779235a387ed64bfe02643abee2009243 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2692877 Reviewed-by: Craig Hesling <hesling@chromium.org>
* zephyr: config_chip: undefine few more ECOS specific optionsFabio Baltieri2021-02-161-0/+11
| | | | | | | | | | | | | | These are not used in Zephyr, annotating them so we can keep track of them. BUG=b:177604307 BRANCH=none TEST=zmake buildall Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Change-Id: Id45a8d9ddb92455d1f51d62881549fbcb5432827 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698109 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv2: Allocate FRS ports 3.0 A when neededDiana Z2021-02-165-97/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When there are no PD sinks requiring 3.0 A, any FRS ports which require that much current will have FRS detection enabled. If a PD sink requiring 3.0 A is attached, then FRS detection will be disabled on that port again. FRS port partners which require only USB or 1.5 A of current will always have FRS detection enabled. BRANCH=None BUG=b:141690755 TEST=on volteer-based system, verify: - FRS source partners requiring 1.5 A or less always have FRS detection enabled - FRS detection is disabled on detach - FRS source partner requiring 3.0 A has FRS detection enabled if no PD sink needing 3.0 A is present - Plugging in a 3.0 A PD sink disables FRS detection for the 3.0 A FRS partner - Unplugging a 3.0 A PD sink enables FRS detection for the 3.0 A FRS partner - When FRS occurs on 3.0 A port with detection enabled, partner is offered appropriate starting current in first source caps Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ib067ac7c1c2f4a6e64f36aeffd1b8dde5cb93760 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2676084 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Eric Herrmann <eherrmann@chromium.org> Tested-by: Eric Herrmann <eherrmann@chromium.org>
* guybrush: Don't read memory temp in G3Rob Barnes2021-02-161-1/+9
| | | | | | | | | | | | | Memory thermistor is connected to S5 rail. BUG=b:179065659 BRANCH=None TEST=Build Change-Id: I5c412d6c473defae9088251db50cf23b098e2bc2 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2692868 Reviewed-by: Diana Z <dzigterman@chromium.org>
* octopus: Exclude RV32I panic data from structurePatryk Duda2021-02-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch excludes RV32I core specific data in panic data structure for all octopus devices to keep the same size of the structure in octopus EC RO and ToT EC. This is necessary to prevent panic data corruption and access jump data correctly (see bug in description for more details). All octopus family devices doesn't include RV32I panic data in their EC RO panic data structures (checked include/panic.h on firmware-octopus branch). BUG=b:165773837 BRANCH=none TEST=Run EC ToT on Ampton. Make sure you are in EC RW. Crash EC using 'crash assert'. Make sure that EC RW after sysjump doesn't report unknown reset cause. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ia8c367cc3b4e2b24f21e907f8dafa49aeb7d40e7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
* include/panic: Add config to remove RV32I from panic data structurePatryk Duda2021-02-162-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | RISC-V core specific panic data is bigger than Cortex-M core specific panic data. Including this into union in a panic_data structure causes the whole to grow by 28 bytes. In many boards EC RO is still obtaining pointer to beginning of panic data by subtracting its panic data structure size from the end of RAM. When EC RW saves panic data it will be corrupted by EC RO. Moreover, during next boot EC RW won't be able to find jump data (see b/165773837 for more details). This config allows boards to not include RV32I panic data if their EC RO doesn't include it to keep panic data structure in sync. Default behaviour is that RV32I core specific panic data is included. BUG=b:165773837 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I01efd63ce67b08c6991d4d52a40f0818b0d70a62 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673416 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
* tcpmv2: Only issue SOP' soft reset following PR swapKeith Short2021-02-163-32/+26
| | | | | | | | | | | | | | | | | | | | | | | | Entry to the PE_SNK_Startup and PE_SRC_Startup states resets the protocol layer, and clears the message IDs for all SOP types. These states are entered during initial connect, hard reset, and after a power role swap. The cable should automatically clear it's message IDs on the initial connect (because it didn't have power) and on a hard reset, so modify the PE policy to only send SOP' soft reset after power role swaps. BUG=b:179325862 BRANCH=volteer TEST=Connect TBT loopback device, verify no SOP' soft reset is sent and that TBT entry is successful. TEST=Connect USB+DP monitor when EC starts as SRC/DFP and VCONN source. Verify EC sends SOP' soft reset is sent after power role swap. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I2c133eec0e76c1ecb7b79cea94a541fdb55ee9c1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2691423 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* CBI: Add rework_id fieldstabilize-rust-13795.B-mainThejaswani Puta thejaswani.putta@intel.com2021-02-166-20/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This field will be used to describe all the reworks performed on a board which includes the mandatory, optional and feature reworks. Also modified existing command handlers under ectool and cbi-util tool to support 64 bit length data. Includes build fix for targets where long int is not 64 bits. BUG: b:170385859 BUILD TEST: make BOARD=<BOARD_NAME> -j; make runfuzztests make runhosttests setup_board, cros_workon & emerge-<32-bit target> ec-utils TEST: ./cbi-util create --file ~/cbi_image --board_version 1 --oem_id 2 --sku_id 255 --dram_part_num "01654329efghac" --model_id 15 --rework_id 123456789123456712 --size 256 CBI image is created successfully TEST: ./cbi-util show --file ~/cbi_image CBI image: /home/thejaswani/cbi_image TOTAL_SIZE: 47 Data Field: name: value (hex, tag, size) BOARD_VERSION: 1 (0x1, 0, 1) OEM_ID: 2 (0x2, 1, 1) SKU_ID: 255 (0xff, 2, 1) MODEL_ID: 15 (0xf, 5, 1) REWORK_ID: 123456789123456712 (0x1b69b4bacd05ec8, 9, 8) DRAM_PART_NUM: 01654329efghac (3, 15) Data validated successfully TEST: hexdump -C ~/cbi_image 00000000 43 42 49 1e 00 00 2f 00 00 01 01 01 01 02 02 01 |CBI.../.........| 00000010 ff 05 01 0f 09 08 c8 5e d0 ac 4b 9b b6 01 03 0f |.......^..K.....| 00000020 30 31 36 35 34 33 32 39 65 66 67 68 61 63 00 ff |01654329efghac..| 00000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00000100 TEST: localhost ~ # ectool cbi set 9 98765432 8 localhost ~ # ectool cbi get 9 As uint: 98765432 (0x5e30a78) As binary: 78 0a e3 05 00 00 00 00 localhost ~ # ectool cbi set 9 123456789123456712 8 localhost ~ # ectool cbi get 9 As uint: 123456789123456712 (0x1b69b4bacd05ec8) As binary: c8 5e d0 ac 4b 9b b6 01 localhost ~ # ectool cbi set 9 1234 2 localhost ~ # ectool cbi get 9 As uint: 1234 (0x4d2) As binary: d2 04 TEST: > cbi(from EC Console) 2021-01-19 20:59:56 [80.979692 CBI Reading board info] 2021-01-19 20:59:56 CBI_VERSION: 0x0000 2021-01-19 20:59:56 TOTAL_SIZE: 54 2021-01-19 20:59:56 BOARD_VERSION: 1 (0x1) 2021-01-19 20:59:56 OEM_ID: (Error 1) 2021-01-19 20:59:56 MODEL_ID: (Error 1) 2021-01-19 20:59:56 SKU_ID: 655361 (0xa0001) 2021-01-19 20:59:56 FW_CONFIG: 199683 (0x30c03) 2021-01-19 20:59:56 PCB_SUPPLIER: (Error 1) 2021-01-19 20:59:56 SSFC: (Error 1) 2021-01-19 20:59:56 REWORK_ID: 1234 (0x4d2) 2021-01-19 20:59:56 43 42 49 8c 00 00 36 00 00 01 01 02 04 01 00 0a |CBI...6.........| 2021-01-19 20:59:56 00 06 04 03 0c 03 00 03 19 4d 54 35 33 45 35 31 |.........MT53E51| 2021-01-19 20:59:56 32 4d 36 34 44 34 4e 57 2d 30 34 36 20 57 54 3a |2M64D4NW-046 WT:| 2021-01-19 20:59:56 45 00 09 02 d2 04 ff ff ff ff ff 7f ff ff ff ff |E...............| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2020-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 2021-01-19 20:59:56 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| Signed-off-by: Thejaswani Puta <thejaswani.putta@intel.com> Change-Id: I073a119d43c94cd266503a0fc972a62134b3385f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2693746 Tested-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Commit-Queue: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* brya: Enable chipset supportCaveh Jalali2021-02-163-0/+22
| | | | | | | | | | | | | This enables support for the Alder Lake chipset using the SLG4BD44540 power sequencer. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: I6718bf5500286cee0616024b27939198bcba3b5b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2686980
* common: motion: fix races at shutdownGwendal Grignou2021-02-131-7/+10
| | | | | | | | | | | | | | | | | | | Do not use collection_rate blindly after a function may have slept: the HOOK task could have run suspend() or suspend() call and set it to 0. Fixes 104f5257 ("motion: Control on which task sensor setting functions are running on") [CL:2553347] BUG=b:176918310, b:170703322 BRANCH=kukui TEST=unit test. Change-Id: I9ef13ceca195db4b48866f1e53f9408fb2bbf595 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2616137 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* board: Set Accelerometer range to 4gGwendal Grignou2021-02-1322-27/+27
| | | | | | | | | | | | | | | | | For accelerometer presented to Android, set default range to 4g. Required by Android CDD - Section 7.3.1 - Paragraph C.1.4. mems_setup can correct it, but it is cleaner if the default setting is right. BUG=b:144004449 BRANCH=none TEST=compile Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I781eafc003823e2595d46d7170f717aaee08dc6d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2657956 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* zephyr: volteer: Enable the MPUSimon Glass2021-02-131-0/+1
| | | | | | | | | | | | | | | Enable the Memory-Protection Unit on Volteer. Currently this does not do anything useful. BUG=b:180039888 BRANCH=none TEST=build zephyr volteer Build ECOS for volteer Change-Id: I57168b143c08add878d8ccf9313cc7096795339e Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2691572 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Add support for CONFIG_MPUSimon Glass2021-02-137-0/+156
| | | | | | | | | | | | | | | | | | Add this option so that the Memory-Protection Unit (MPU) can be enabled. The implementation is still to be worked out. Note that CONFIG_PLATFORM_EC_EXTERNAL_STORAGE is not defined, as it should be. That work is ongoing elsewhere. BUG=b:180039888 BRANCH=none TEST=build zephyr volteer Build ECOS for volteer Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ie26e8ba4b3f0b8024930e42fbbb03f0f2a26f3da Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2691566 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: volteer: Enable floating pointSimon Glass2021-02-131-0/+1
| | | | | | | | | | | | | | | | | Enable this option so that floating-point arithmetic can be used. BUG=b:180023514 BRANCH=none TEST=with zephyr SDK, build zephyr volteer with CONFIG_NEWLIB_LIBC and see no warnings Build for volteer Run 'zmake testall' in the chroot (did not run zmake testall with zephyr SDK as it is not supported!) Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ic68f39f1725b328f925c8120dc73c7149ec890fc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2691415 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Add support for CONFIG_FPUSimon Glass2021-02-133-0/+69
| | | | | | | | | | | | | | | | | | | | Allow this to be enabled for Zephyr. Since we are using the minimal C library we need to define our own version of a few functions. Add these for Cortex-M4, taken from the existing ECOS code. It happens that Zephyr uses CONFIG_FPU, the same as ECOS, so there is nothing needed in config_chip.h for this case. If CONFIG_FPU is enabled on a new platform, some work will be needed to make it build. BUG=b:180023514 BRANCH=none TEST=build zephyr volteer with CONFIG_NEWLIB_LIBC and see no warnings Build for volteer Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I91187560b7e699b7f77ccfa5990617606f7fd6fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2691414 Reviewed-by: Keith Short <keithshort@chromium.org>
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