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* brya: Add CBI and FW_CONFIG supportstabilize-13821.B-mainCaveh Jalali2021-02-277-0/+194
| | | | | | | | | | | | | | This adds support for CBI and the first USB DB type field in FW_CONFIG. BUG=b:173575131,b:180434685 BRANCH=none TEST=buildall succeeds Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: If1d27fc100db9b814f90a9378d8dd19530a92bf4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706964 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com>
* brya: tune fan parametersCaveh Jalali2021-02-271-9/+6
| | | | | | | | | | | | | | This tunes the fan parameters for the brya prototype fan. These are temporary parameters until a real fan is available. BRANCH=none BUG=b:173575131,b:180681346 TEST=observed fan speeds using EC CLI Change-Id: I74c1044c56a0ab7374f0fe52a757c33ede2aaa08 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2722553 Reviewed-by: Keith Short <keithshort@chromium.org>
* brya: Enable USB-A port power controlCaveh Jalali2021-02-272-0/+14
| | | | | | | | | | | | | | | This enables power control (i.e. "charging") of the USB-A port located on the USB daughtercard. This is required to power devices connected to the port. BRANCH=none BUG=b:173575131 TEST=USB LED flash light powers on Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Id8bcf07a6632b909e7c28b5800d035f05fea0ef6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717806 Reviewed-by: Keith Short <keithshort@chromium.org>
* docs/fingerprint: Update power numbers for dartmonkeyTom Hughes2021-02-271-2/+23
| | | | | | | | | | | | | | | | https://crrev.com/c/2689101 is needed in order to configure the sleep GPIOs correctly on icetower, so the change was cherry-picked to the release branch to perform the measurement. BRANCH=none BUG=b:180445334 TEST=view in gitiles Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I608a725c6f4c474365814b95a39ed365b2ea1eee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2724876 Commit-Queue: Craig Hesling <hesling@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* zephyr: efs2: Enable EFS2 for volteerYuval Peress2021-02-267-9/+61
| | | | | | | | | | | | | | | | | | | | | | Enable efs2 running at boot for volteer using the CONFIG_PLATFORM_EC_VBOOT flag. When enabled, prior to starting any tasks, the RO image will compute the hash of the RW image and send it to the cr50 for verification. Note that the cr50 verification will fail right now until we update chromeos-bootimage-0.0.3.ebuild's add_ec() function to compute the hash using the zephyr build's output. This final change will be needed because zmake does not produce build/${BOARD}/R(O|W)/ec.R(O|W).flat BRANCH=none BUG=b:164421798 TEST=zmake testall TEST=build volteer, flash, see TX data to cr50 and correct response. Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I2c8b3f726a843297cec3fc08306d8edaaa1999f7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721498 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv2: Reset discovery events on AP resetDiana Z2021-02-264-20/+34
| | | | | | | | | | | | | | | | | | | | When the AP resets, reset the SOP and SOP' discovery events so it knows there is completed discovery information to consume. Additionally, remove the requirement that events only be set from the port's PD task. Since this is just an atomic or of events and the setting of a host event, it should be safe to do from other tasks. BRANCH=None BUG=b:179505381 TEST=on galtic, verify events are reset after reboot with: - Apple 3-in-1 (SOP identity, no SOP') - TBT dock (both SOP and SOP' identity) - Active cable tied to another chromebook (SOP' identity, no SOP) Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ib2c49854fd4269c65e771565210fe88222c6e848 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2708785 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* blipper: Initial EC imagechenzanxi2021-02-268-0/+1410
| | | | | | | | | | | | | | | | | | | | | Create the initial EC image for the blipper variant by copying the waddledee reference board EC files into a new directory named for the variant. (Auto-Generated by create_initial_ec_image.sh version 1.5.0). BUG=b:179648964 BRANCH=None TEST=make BOARD=blipper Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Change-Id: Id5ad16b3bbb2c09c69f8cd7230c22bfed919dc6e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717848 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Henry Sun <henrysun@google.com> Tested-by: Henry Sun <henrysun@google.com>
* zephyr: console: add functions to enable/disable the shellYuval Peress2021-02-262-0/+44
| | | | | | | | | | | | | | | | | | | | | Adds functions that will allow us to temporarily take over the uart from the shell. Note that for platform/ec code without Zephyr, these functions are stubs so they are safe to call from common code, though we'll most likely need other logic (such as turning off the console task). This isn't done in these functions because the Zephyr shell behaves differently from the task and in the example of efs2 needs to be turned off earlier than the platform/ec console task. BRANCH=none BUG=b:164421798 TEST=zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I75fc8fe2ca9214f216561ded97818880dda247d5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2723495 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
* zephyr: gpio: map GPIO_PACKET_MODE_EN for volteerYuval Peress2021-02-261-0/+1
| | | | | | | | | | | | | | | | EFS2 requires the packet mode GPIO in order to wake the cr50. Map the packet-mode-enable GPIO for volteer so it can be used in efs2.c BRANCH=none BUG=b:164421798 TEST=zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I55147fce04795bdb6db950b52c6f06657848f410 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721497 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: implement uart functions getc and clear_inputYuval Peress2021-02-261-0/+26
| | | | | | | | | | | | | | | | | | | These functions are needed to build efs2.c. uart_getc() is the platform/ec equivalent of polling for a single byte. While uart_clear_input() doesn't actually have a Zephyr parallel and isn't really needed to get efs2 working. BRANCH=none BUG=b:164421798 TEST=zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I43c46b7ed0b909565673d442c7f734f0c50f1dc0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721496 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
* zephyr: efs2: Compute the __image_size for efs2 in the linkerYuval Peress2021-02-263-2/+18
| | | | | | | | | | | | | | | | | | | | The __image_size should match used portion of the flash. Note that in Zephyr, different linker scripts have different variables. _flash_used is only available for the verified chips. Other chips may use a different name or may require manual calculation. Compute the size by using the Zephyr sections. This is the parallel to core/cortex-m/ec.lds.S's logic. BRANCH=none BUG=b:164421798 TEST=zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: If91acd5dc2b925ad226f2d1c3feccc77617e04df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721495 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: Update gitlab docsSimon Glass2021-02-261-2/+7
| | | | | | | | | | | | | This is working now, so updates the docs. BUG=b:178731498 BRANCH=none TEST=none Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I4afaa0b3d57e7beae71d91d824c3925df54f3374 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2722852 Reviewed-by: Yuval Peress <peress@chromium.org>
* kracko: Add GPIO_EC_ENTERING_RW2Tommy Chung2021-02-262-0/+16
| | | | | | | | | | | | | | | | This commit syncs with crrev.com/c/2719104 on kracko. BUG=b:181262149 BRANCH=dedede TEST=Build and flash kracko, verify it boots. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: Iaecc91d1cad7f3872b6761ae2ca619c00dfd3b7b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719785 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Devin Lu <Devin.Lu@quantatw.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* lantis: Add GPIO_EC_ENTERING_RW2Tommy Chung2021-02-262-0/+16
| | | | | | | | | | | | | | This commit syncs with crrev.com/c/2719104 on lantis. BUG=b:181085178 BRANCH=dedede TEST=Build and flash lantis, verify it boots. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I33f44dbbe4959b96e5805d7f2833c9fa20984537 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719779 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* docs/fingerprint: Add Chrome OS Project Configuration detailsTom Hughes2021-02-261-1/+16
| | | | | | | | | | | | | | model.yaml files no longer have to be created by hand; instead the Chrome OS Project Configuration tools will generate it. BRANCH=none BUG=b:180410925 TEST=view in gitiles Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Id7eb218b7b908ed77dec33a2b7479bbf5a72fc4c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721139 Reviewed-by: Craig Hesling <hesling@chromium.org>
* retimer: Fix issues in suspending PD task during retimer scanli feng2021-02-261-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When AP scans retimer for firmware update, it requests EC to suspend PD task of NDA (no device attached) PD ports. Then pd_set_suspend() sets suspend flag TC_FLAGS_REQUEST_SUSPEND, and wakes up PD task to check new flag. However in this case, the flow exits early to avoid deadlock when running from task which is going to be suspended. We expect next time PD task runs (after 5ms), it can detect this flag and suspend itself. This is found to be working only when the PD task does not enter low power mode immediately after this flag is set. In cases, where the PD task enters low power mode, PD is not suspended and so AP could not scan the retimer successfully. Move to hook_call to suspend PD task, so pd_set_suspend() can execute all the way to wake up PD task, and process the suspend flag. BUG=b:180573726 BRANCH=none TEST=Tested Voxel DVT, together with coreboot and kernel changes, make sure retimers of NDA ports are in sysfs entries. Coreboot changes are merged. Kernel patches list is: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2670719 Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I98bf2a028ee8fe3623f2e465a02a6edeff1b6e3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2709560 Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* firmware_builder: always create metrics filePaul Fagerburg2021-02-261-5/+7
| | | | | | | | | | | | | | | | | | | | The firmware builder doesn't need to do anything for code coverage, except that it still needs to create a metrics file so that the postsubmit builder can find it. BUG=chromium:1182320 BRANCH=None TEST=firmware-ec-cov-cq succeeds Cq-Include-Tryjobs: chromeos/cq:firmware-ec-cov-cq Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Id1a4ac5cee1ba4bfbfb2f68ce937386658abfa4f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2722554 Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: LaMont Jones <lamontjones@chromium.org> Reviewed-by: Sean McAllister <smcallis@google.com>
* servo_v4p1: Disable USB power in case of faultJan Dabros2021-02-261-3/+9
| | | | | | | | | | | | | | | | | | | | | Previously, the only action in case of overcurrent event on USB ports was to log the information to the user. Actually more important thing is to disable USB power signal, even though load switch should disable VBUS. Additional positive side-effect is that servod controls like 'image_usbkey_pwr' will be in sync with actual state of VBUS signal. BUG=none BRANCH=main TEST=Generate overcurrent event on A0 USB3 port. Verify that A0 pwr signal is off by issuing: `dut-control image_usbkey_pwr` Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I083f68e0a6f02d7de087b125790225fbffc941e0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2718869 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_v4p1: Fix wrong ifdef in cc_dac commandMichał Barnaś2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | Adding io_expander support for servo_v4p1 required moving cc_dac command to RO section only. There was a typo in ifdef which resulted in cc_dac command being unavailable. BUG=b:168385201 BRANCH=main TEST=Build firmware and flash it to servo_v4p1. On servo's console, execute command: help There should be cc_dac command listed Signed-off-by: Michał Barnaś <mb@semihalf.com> Change-Id: Icf211950bd18e4d33173b4cd679df58217069f39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721722 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* firmware_builder: temporary protobuf fixLaMont Jones2021-02-261-1/+3
| | | | | | | | | | | | | | | | firmware_builder should not be importing from chromite.api.gen. This works around the issue while we implement the fix. BRANCH=none BUG=chromium:1181505 TEST=train Signed-off-by: LaMont Jones <lamontjones@chromium.org> Change-Id: Id49847bcd347f26e05eb494f8a6f6362009189ae Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719650 Reviewed-by: Mike Nichols <mikenichols@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Alex Klein <saklein@chromium.org>
* cleanup: rename ite tcpm driverRuibin Chang2021-02-264-7/+9
| | | | | | | | | | | | | | | | Rename it83xx_tcpm_drv to it8xxx2_tcpm_drv for chip it8xxx2 series. BUG=none BRANCH=none TEST=1.make buildall -j 2.on hayato, connecting to adapter and dongle can go to ready state. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I2622e7fe0884d3ae20a63ec48219de00d5537bc6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717430 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* driver/it83xx, it8xxx2: turn on PD BMC PHY for TCPMv1Ruibin Chang2021-02-262-10/+42
| | | | | | | | | | | | | | | | | | | | If explicit contract is set in bbram when EC boot up, then TCPMv1 set soft reset as first state instead of unattached.SNK, so we need to enable BMC PHY for tx module. And same as TCPMv2, we turn on/off BMC PHY and set low power mask when hook_dis/connect is called. BUG=none BRANCH=none TEST=on icarus, the explicit contract is set in bbram when EC boot up, and we can tx soft reset (won't happen tx timeout). Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I3c8d3db240d2290ced17b90aeb0420ac9f20598d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2712213 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* TCPMv1/v2: Add config option to disable TCPC VCONNEric Herrmann2021-02-263-13/+41
| | | | | | | | | | | | | | | | | | | | | Currently we always source VCONN from the TCPC, and also the PPC if present. However the SYV682 can't handle 5V on its host-side CC pins, so we shouldn't source VCONN in that case. For those TCPCs which will trigger OVP if VCONN isn't enabled, this will not happen with the SYV682, since it isolates VCONN from the TCPC CC signals. BUG=b:180973460 TEST=On delbin, make sure the host-side CC pins are <3.3V when sourcing VCONN BRANCH=None Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: I8929a44fc23f93c44559229f1b0d024fd7fbc7db Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721086 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* servo_v4p1: Enable 5A and 20V chargingBrian J. Nemec2021-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables 5A and 20V charging on all Servo_v4p1's. There is a small population of servo_v4p1 devices with 3A cables but these represent about 100 total units between the early builds. The setting was not set as a board id configuration as stress tests show this process will still be safe and the Servo_v4p1's that are current limited are easy to keep within the 3A current limits. The 5A cables are visually distinctive and most chargers and DUTs are limited to 3A. BUG=b:176110980 BRANCH=servo TEST=Validated the Servo_v4p1 can deliver power at 4.5A and 20V using a 90W charger and a resistive load. Verified current using meters and verified Servo_v4p1 does not heat excessively significantly after over 2 hours at the cable or PCB. TEST=Repeated the same test on older Servo_v4p1 devices with the smaller shunt resistors and 3A compliant cable and verified components remain at reasonable temperatures. Signed-off-by: Brian Nemec <bnemec@chromium.org> Change-Id: If9e67081fe4441ca0fe1039c3189e0673eb8f13a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2714031 Reviewed-by: Jan Dąbroś <jsd@semihalf.com> Reviewed-by: Matthew Blecker <matthewb@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* docs/fingerprint: Add information on fingerprint SKUsTom Hughes2021-02-261-0/+12
| | | | | | | | | | | | BRANCH=none BUG=none TEST=view in gitiles Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ib9c7ec288c9efabb454580c6bf6028ee6a0a1373 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721087 Commit-Queue: Craig Hesling <hesling@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* driver: tcs3400: Check for device status only onceGwendal Grignou2021-02-251-28/+31
| | | | | | | | | | | | | | | | | | Since ASIEN (interrupt on ALS saturation) and ALS threshold interrupts are disabled, we can only get interrupt on RBGC cycle read. Therefore, when using the interrupt, not need to check if RGB data is ready in post_events(). Only check while in force mode. Remove recheck when accounting for saturation. BUG=b:177860358 BRANCH=kukui,hatch,puff,volteer TEST=compile Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I7fc419a98828b9b188849e04a15cfefaf9e96c8a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2572739 Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* driver: icm426xx: discard first data instead of sleepingJean-Baptiste Maneyrol2021-02-253-22/+98
| | | | | | | | | | | | | | | | | | | | Sleeping when turning a sensor on/off is problematic when the other sensor is running. Replace sleeping by discarding first events until sensor is stabilized. BUG=chromium:1175757 BRANCH=hatch,nami,kukui,dedede,grunt,zork,octopus,volteer TEST=turn sensor on/off when the other is running using cros-ec iio devices Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I61801970b12f9fbdcc2cd96cb4df1edae5ed521f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2682715 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org>
* driver: icm426xx: change accel oscillator to RC clockJean-Baptiste Maneyrol2021-02-252-1/+11
| | | | | | | | | | | | | | | | | | | When using accel low-power with WakeUp oscillator, turning gyro on switch directly to PLL mode and provokes glitch on ODR. Use RC clock oscillator for accel low-power to avoid this glitch. BUG=chromium:1175757 BRANCH=hatch,nami,kukui,dedede,grunt,zork,octopus,volteer TEST=turn gyro on when accel is running using cros-ec iio devices and check that odr stays consistent. Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I51435eb9533a1fa16bf695e468854156c16d3296 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2679700 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org>
* driver: icm426xx: update odr before turning sensor onJean-Baptiste Maneyrol2021-02-251-10/+10
| | | | | | | | | | | | | | | Prevent to have the first event in 1 ODR and the second in another. BUG=chromium:1175757 BRANCH=hatch,nami,kukui,dedede,grunt,zork,octopus,volteer TEST=turn sensor on/off and change odr using cros-ec iio devices Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I501bf14e70fd7180c7e68385ef4afb5934d7d37a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2679699 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org>
* genvif: Trigger OverCurrent Protection by CONFIG_USBC_OCPDenis Brockus2021-02-251-2/+2
| | | | | | | | | | | | | | | BUG=b:181194535 BRANCH=none TEST=make buildall TEST=Check base VIF output Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Ic1d9415137570e0d52cd8393c36df572e515deef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2716158 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* baseboard/kukui: enable TCPMv2 on it81202 based boardDino Li2021-02-251-2/+9
| | | | | | | | | | | BUG=b:180668427 BRANCH=none TEST=On icarus, EC negotiates to 15V and starts charging. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ibd37b86303a03ce4b2e5b394d38c6b53bcf307e5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717434 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* zephyr: add Vivaldi keyboard supportFabio Baltieri2021-02-253-0/+20
| | | | | | | | | | | | | | Add support for building common/keyboard_vivaldi.c. This is enabled by default in ECOS as long as CONFIG_KEYBOARD_PROTOCOL_8042 is enabled too. BRANCH=none BUG=b:177604307 TEST=build and verified that the map is set and HC command is received Change-Id: I881cdfc0a14432a97ced27be757b4c30daf002b8 Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2712967 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: enable md & rw console commandWealian Liao2021-02-253-0/+56
| | | | | | | | | | | | | | | | | | | This enables the memory accessing console command (e.g., md, rw) in Zephyr. The commands are used to access the ec memory space for driver developing & bug investigating. BUG=b:177604307 BRANCH=None. TEST=read the npcx firmware header by 'rw 0x64000000' & get the following 'read 0x64000000 = 0x2a3b4d5e' Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I560be52fb1e09a3e72c8619ee9cdf0c1b9dcbcf9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2714723 Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* common: Add new shared PD interrupt handlerCaveh Jalali2021-02-251-43/+130
| | | | | | | | | | | | | | | | | This adds a new TCPC interrupt handler task that knows how to deal with TCPCs that share a single interrupt line. ec.tasklist for this handler takes a port mask instead of a port number as a task startup argument. The main quirk of shared interrupts is that interrupts must be serviced on multiple devcies in order to clear the interrupt into the EC. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: I6f9f0ce471092741274d8a1542510d92100f6698 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2700314
* sasuke : define CONFIG_CHARGE_RAMP_HWYongBeum.Ha2021-02-251-0/+1
| | | | | | | | | | | | | | define CONFIG_CHARGE_RAMP_HW BUG=b:180166404 BRANCH=None TEST=make -j BOARD=sasuke flash EC, connect DCP charger and check if input current is 1.5A Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I9b8ec06c4851741c574f6b1b9f831072b6efda7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717160 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* baseboard/kukui: separate configs for stm32 and ite chips.Dino Li2021-02-251-37/+40
| | | | | | | | | | | | | | | | | This change pulls stm32 chip-specific options into VARIANT_KUKUI_EC_STM32F098 (include save flash space operations), and enable it83xx chip-specific options for it81202. BUG=none BRANCH=none TEST=-buildall. -boot to kernel on juniper. -boot to manual recovery on icarus. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I81fb318960bf24780c164d9abe631ef70a360bf9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717344 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* system: Fix ENTERING_RW GPIO name.Aseda Aboagye2021-02-251-2/+2
| | | | | | | | | | | | | | | In haste, I misspelled the ENTERING_RW GPIO name. This fixes it. (sorry) BUG=b:180965428,b:181051734,b:181085178 BRANCH=dedede TEST=make -j buildall Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I0d2f3dece2dcf44a0e16923f500d68216bbadf33 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719106 Reviewed-by: Diana Z <dzigterman@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: Get SNK Caps after PR_Swap in SNK startupEric Herrmann2021-02-251-3/+9
| | | | | | | | | | | | | | | | | | | | If we support FRS, we should query the SRC sink_capabilities on entry to SNK_Ready. Currently we queue up this when we enter snk_startup, but only when it isn't due to a power role swap. Some devices will change their sink capabilities depending on what their current status is, so we should check again following a power role swap. BUG=b:181156774 TEST=make buildall TEST=Check that get_sink_capabilities message is sent following a SRC->SNK power role swap BRANCH=none Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: I5f1cbe2b300e8c29bef16336bd7ddfa8f7a8b2c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2718495 Reviewed-by: Nathan Kolluru <nkolluru@google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* draw*: Add GPIO_EC_ENTERING_RW2Aseda Aboagye2021-02-252-0/+16
| | | | | | | | | | | | | | | | | | | This commit adds a new GPIO, GPIO_EC_ENTERING_RW2 which does the same thing as GPIO_EC_ENTERING_RW. However, it's on a pin that's more well behaved around init time. This commit also overrides the board_pulse_ec_entering_rw() function such that both lines can be pulsed. BUG=b:180965428,b:181051734,b:181085178 BRANCH=dedede TEST=Build and flash draw*, verify it boots. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ia9cfba97b8fcad5975e412523686a7ba53ea7399 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719104 Reviewed-by: Diana Z <dzigterman@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* system: Add board_pulse_entering_rw()Aseda Aboagye2021-02-252-3/+17
| | | | | | | | | | | | | | | | | | | This commit adds an overridable function for pulsing the EC_ENTERING_RW signal. This function should only be overridden in very rare circumstances! The default implementation is unchanged. EC_ENTERING_RW is pulsed for 1ms. BUG=b:180965428,b:181051734,b:181085178 BRANCH=dedede TEST=`make -j buildall` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ie04bc0b0d20473be1b3d5f46fa1a986ab6e59953 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719103 Reviewed-by: Diana Z <dzigterman@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* brya: Add FRS and OC GPIOsCaveh Jalali2021-02-241-2/+9
| | | | | | | | | | | | | | | This adds the USB FRS and OC control signals to the GPIO expander located on the NCT 3808 TCPC. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: Id6e29541b266638ed5b11571ae5cdc2598e40f35 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2704032 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* brya: Enable AP throttlingCaveh Jalali2021-02-244-14/+57
| | | | | | | | | | | | | | | | This enables AP throttling based on thermal conditions. Brya has two thermistors - one near the SoC and one near the charger that can be used for deciding when to throttle. BRANCH=none BUG=b:173575131,b:180681346 TEST=buildall passes Change-Id: Ieaa6959ff9fc7ee5e505c13cff2150ad70a04e3b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2686981 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* common: Add board_is_usb_pd_port_present functionCaveh Jalali2021-02-242-0/+21
| | | | | | | | | | | | | | | | | | This adds a new overridable function to check if a USB PD port exists on a system. This is preferred over using board_get_usb_pd_port_count() or CONFIG_USB_PD_PORT_MAX_COUNT because it handles sparse port numbering. The "missing" port no longer needs to be the highest numbered port and call sites no longer need to implement the special checks for this case. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: I3f74eddd99c6901b42ce05bab6f2bdd545127d1a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2700313 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* brya: set up non-vivaldi keyboard layoutCaveh Jalali2021-02-242-0/+17
| | | | | | | | | | | | | | | This configures the brya keyboard layout support to match early boards. These boards set up for a non-vivaldi layout. BRANCH=none BUG=b:180973324 TEST=tested all keys Change-Id: I856c87c34db3dfda647de88577655b865f97ab93 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2713939 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* brya: Add thermistor supportCaveh Jalali2021-02-243-1/+65
| | | | | | | | | | | | | | This adds support for the two thermistors on brya. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: I198e1ce72910d1798c51cf5c99c9f1f0601f3c31 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706263 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* RAA489000: Rearrange inits to sink Vbus fasterDiana Z2021-02-241-35/+37
| | | | | | | | | | | | | | | | | | | | | In order to more quickly detect and sink Vbus, move up the priority on enabling the Vbus ADC and checking our Vbus status to enable sinking. Additionally, gate this enablement on the battery not being capable of supporting the board to prevent premature Vbus sinking in normal use-cases. BRANCH=None BUG=b:178981107,b:178728138 TEST=on storo and sasukette, confirm board can boot with no battery and TCPC works as expected On galtic, confirm sinking is enabled on a no-battery boot but not automatically enabled with a charged battery attached Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I26eec09c2fa50d2425c5d6b0ef7b8847bd570da7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2715596 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Revert "pd_alt_mode_dfp: Default to 4 lanes of DP"Aseda Aboagye2021-02-241-22/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7991e4d1f705c84966b382219f194804380b79ab. Reason for revert: Maintaining status quo until Chrome OS UI has the ability for a user to report if this change works well for them. Original change's description: > pd_alt_mode_dfp: Default to 4 lanes of DP > > Currently our default PD policy states that if dock that supports DP > alt mode also advertises Multi-function preferred, we configure the > superspeed muxes to use 2 lanes for DisplayPort and 2 lanes for > SuperSpeed USB. However, this is done without regard as to what the > actual usage of the SuperSpeed ports may be. > > We've historically made this trade off, but it results in degraded > display performance. Users may be better served if we prioritize > display performance over SuperSpeed USB. > > The ideal solution involves adding additional plumbing such that we > can configure the chosen pin configuration from the AP based upon > other heuristics. > > BUG=b:178635286 > BRANCH=as many as feasible? > TEST=Build and flash DUT, plug in a dock with SuperSpeed USB ports, > verify that 4 lanes of DP are configured. > > Signed-off-by: Aseda Aboagye <aaboagye@google.com> > Change-Id: Ie2d47588012aceb7f13312b6947b885f8f7034a8 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2653315 > Tested-by: Aseda Aboagye <aaboagye@chromium.org> > Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> > Reviewed-by: Rob Barnes <robbarnes@google.com> > Reviewed-by: Diana Z <dzigterman@chromium.org> > Commit-Queue: Diana Z <dzigterman@chromium.org> Bug: b:178635286 Change-Id: I94f107a43a58d512070a0507ebe2529eaedf473e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2718274 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
* EC: After SRC_HARD_RESET_RECOVER set CHECK_XX_ROLEJeremy Bettis2021-02-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | Just before moving from state PD_STATE_SRC_DISCONNECTED_DEBOUNCE to PD_STATE_SRC_STARTUP we set the PD_FLAGS_CHECK_PR_ROLE and PD_FLAGS_CHECK_DR_ROLE. However when we move from PD_STATE_SRC_HARD_RESET_RECOVER to PD_STATE_SRC_STARTUP we do not set those flags. This cl corrects that and sets the flags in both cases. This will allow the servo to get back into the correct dr_role after a hard reset. BUG=b:179532434, b:178417455, b:180051107 TEST=Flashed servo, cc srcdts, pd 1 hard BRANCH=None Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I42d5807ab87d3bc001f80ca709a2e72d9e89fe63 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2716862 Tested-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
* TCPMv2: VOLTEER: Correctly set ID Header VDOSam Hurst2021-02-241-2/+2
| | | | | | | | | | | | | | | | When responding to a DiscId message, return the ID Header VDO with the USB Communications Capable as a USB Device bit to zero and the Product Type(UFP) bits to 000b. BUG=b:173028252 BRANCH=none TEST=Passes TD.PD.VNDI.E1 VDM Identity Signed-off-by: Sam Hurst <shurst@google.org> Change-Id: I57a62db92eee0f63e081bdb9b6d49e6e3206a41c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2707252 Commit-Queue: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* zephyr: volteer: add thermal configsDawid Niedzwiecki2021-02-241-0/+20
| | | | | | | | | | | | | | | | | Add thermal thresholds for Volteer in the dts file. BUG=b:179886912 BRANCH=none TEST=build Zephyr for Volteer TEST=Run "thermalget" command to check current thresholds. Change the thresholds with "thermalset" to verify if AP throttling is requested. Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: If0b860271c57adf3fa1543de0ff68ec5b48e5b8c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2712951 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
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