summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* Boten: Reroute EC_ENTERING_RW to GPC7stabilize-rust-13836.B-mainstabilize-13836.B-mainreno.wang2021-03-062-1/+16
| | | | | | | | | | | | | | | Refer CL-2719104, adds a new gpio, EC_ENTERING_RW2 for boten. BUG=b:181801177 BRANCH=dedede TEST=make buildall Signed-off-by: reno.wang <reno.wang@lcfc.corp-partner.google.com> Change-Id: I1330525eae0e39ae84689b6e487b63bb34f80e18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2734058 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Henry Sun <henrysun@google.com>
* Trogdor: Change for rev-2 boardWai-Hong Tam2021-03-052-3/+8
| | | | | | | | | | | | | | | Change the EC chip variant from NPCX7M7WB to NPCX7M6FC. This is an incompatible change. It breaks the earlier rev-0 and rev-1 boards. So block building their images. BRANCH=Trogdor BUG=None TEST=Build the Trogdor image. Change-Id: I844848e6747c1eca331a597302244fbca8349854 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738527 Reviewed-by: Douglas Anderson <dianders@chromium.org>
* zephyr: volteer: gpio: add CONFIG_TEMP_SENSOR_POWER_GPIOYuval Peress2021-03-051-0/+1
| | | | | | | | | | | | | | | | | | | | Adding this config value makes sure that we check that the temp sensor is powered prior to trying to read it. Sample output: 21-03-05 12:03:45.732 uart:~$ temps 21-03-05 12:06:18.033 TEMP_SENSOR_CHARGER : Not powered 21-03-05 12:06:18.036 TEMP_SENSOR_PP3300_REGULATOR: Not powered 21-03-05 12:06:18.040 TEMP_SENSOR_DDR_SOC : Not powered 21-03-05 12:06:18.044 TEMP_SENSOR_FAN : Not powered BRANCH=none BUG=none TEST=build/flash volteer and run `temps` command Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ic9eb310815eb9733911a4580a8d5a63d7bdfaac9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2739709 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: adc: add error check for adc_read()Yuval Peress2021-03-051-2/+5
| | | | | | | | | | | | | | | adc_read() shouldn't ignore the return value. It is possible that calling adc_raw_to_millivolts() is invalid if the read command failed. BRANCH=none BUG=none TEST=build/flash volteer and run adc command Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Id668811f0f00e1f3d59a084354171c938ae6751e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2739708 Reviewed-by: Keith Short <keithshort@chromium.org>
* common: adc: Add units to the ADC reading outputYuval Peress2021-03-051-1/+1
| | | | | | | | | | | | | Improved readability for people newly looking at these values. BRANCH=none BUG=none TEST=build/flash volteer and run adc command. Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Idb90ac07d74f067c38ac7825a7c6e7f1d2ec94ba Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2739707 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Require new CONFIG options to be in Kconfig tooSimon Glass2021-03-054-0/+1515
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a script to help deal with new ad-hoc CONFIG options being added to ECOS. This works by maintaining a list of allowed ad-hoc CONFIG options and refusing to allow a build to succeed if it adds new ones. This is easier to implement than a pre-submit and more useful, since we can check the actual CONFIG file produced by a board. For example, adding a new CONFIG to board/volteer/board.h will cause the volteer build to break, but not kukui. That seems important to avoid frustration. Add the base list of allowed ad-hoc CONFIGs, which should never grow. As new Kconfig options are added for existing CONFIG options, or obsolete CONFIG options are removed, the list should eventually shrink to zero. BUG=b:181253613 BRANCH=none TEST=manually test that adding a new '#define CONFIG' causes an error to be generated, and adding a new Kconfig option with the same name causes the error to go away. Also check that the script suggests updating the list when a Kconfig is added for an existing CONFIG option. Finally, manually check that ALLOW_CONFIG=1 does as intended. (that's quite a few manual tests; possibly it is worth automating them) Change-Id: Id11b8d859fd07c2db73324cbb9e425182710ab3d Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2718533 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Revert "brya: Enable AP throttling"Furquan Shaikh2021-03-051-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e4eb9d80a7ea176df7d4fa423b47ee5da9d41200. Reason for revert: Redefinition of same configs. Original change's description: > brya: Enable AP throttling > > This enables the AP throttling feature. > > BRANCH=none > BUG=b:173575131 > TEST=buildall passes > > Signed-off-by: Caveh Jalali <caveh@chromium.org> > Change-Id: I5907b1fd3b3638212985c2e89ef99979c02d8c05 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738396 > Reviewed-by: Furquan Shaikh <furquan@chromium.org> Bug=b:173575131 BRANCH=None TEST=None Change-Id: I19fc7a6f63c55553c853c91225b275c2b315fd95 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2739856 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Auto-Submit: Furquan Shaikh <furquan@chromium.org>
* brya: Enable physical volume buttonsCaveh Jalali2021-03-053-8/+5
| | | | | | | | | | | | | | | This enables the config option for using physical volume up/down buttons. BRANCH=none BUG=b:173575131 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Ib3bb088a88073bd80742e35d0b8a819100163351 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738398 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* cherry: code cleanupTing Shen2021-03-057-169/+73
| | | | | | | | | | | | | | | | | | | | - remove duplicate headers in baseboard.c - remove references to asurada / hayato - replace cherry/led.c by asurada/led_hayato.c, which should be more close to cherry's design BUG=b:181838424 TEST=1) `ag '(asurada|hayato)' -i baseboard/cherry board/cherry` returns empty result 2) make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Id9afd90d323395f38787e452b02b8da65fd15286 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2734168 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* brya: Enable RTC resetCaveh Jalali2021-03-052-0/+3
| | | | | | | | | | | | | This enables the RTC reset feature of the SoC. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: I29f7599fea831dd5751c5609b4e974059a8be2e7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738918 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* brya: Enable power buttonCaveh Jalali2021-03-054-14/+6
| | | | | | | | | | | | | This enables the power button feature form the EC to the SoC. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: Ife5eaa37d269ab4fa5a72be4fec1dec7c4536749 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738917 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* brya: Enable AP throttlingCaveh Jalali2021-03-051-0/+5
| | | | | | | | | | | | | This enables the AP throttling feature. BRANCH=none BUG=b:173575131 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I5907b1fd3b3638212985c2e89ef99979c02d8c05 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738396 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* brya: Configure chipset supportCaveh Jalali2021-03-051-2/+7
| | | | | | | | | | | | | This enables additional chipset configurations for brya. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: Ie8c090ceea14e20d005ddd9a5451d7bcbddc9947 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738916 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* brya: Remove duplicate keyboard support definesCaveh Jalali2021-03-051-12/+0
| | | | | | | | | | | | | | This removes some duplicate keyboard defines that crept in from splitting larger patches and merging. sorry. BRANCH=none BUG=b:173575131 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I541da5ea29477fbaaacb7467fdb98156670e1ec3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738915 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* hammer: Add don boardShou-Chieh Hsu2021-03-053-2/+14
| | | | | | | | | | | | | | | | A close hammer derivative. BRANCH=kukui BUG=b:176570185 TEST=make BOARD=don Signed-off-by: Shou-Chieh Hsu <shouchieh@google.com> Change-Id: I8e3005ac07df1bb2dc6ef519a806fb093a1f7656 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2735214 Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Shou-Chieh Hsu <shouchieh@chromium.org> Tested-by: Shou-Chieh Hsu <shouchieh@chromium.org>
* mt8192_scp/clock: Use ULPOSC1 when AP suspendWeiyi Lu2021-03-052-0/+18
| | | | | | | | | | | | | | | Uses ULPOSC1(260/2MHz) when AP suspend(0.575V <= Vcore <= 0.6V) TEST=suspend/resume ok BUG=b:176317491 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I6fa604f1663539dc108e3c52775054ecc64a8021 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2671264 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
* host_sleep: Fix a race condition on resume from S0ixKeith Short2021-03-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | When resuming for S0ix, the CHIPSET task transitions to the POWER_S0ixS0 state and sets a timer to ensure the AP sends HOST_SLEEP_EVENT_S0IX_RESUME. However, the APs resume message can sometimes arrive before the CHIPSET task transitions to POWER_S0ixS0. This sequence causes the EC to generate a false EC_HOST_EVENT_HANG_DETECT event during resume. BUG=b:180592353 BRANCH=volteer TEST=Repeatedly run "powerd_dbus_suspend" from AP and resume using built-in keyboard. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I550daaaf5411c31f17d608cc341f86da9b934a84 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2737552 Tested-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* magolor: fix gyroscope translation matrixBen Chen2021-03-051-2/+2
| | | | | | | | | | | | | | | CTS tests are failing because sensor values from axis 1 and 2 are negated. When the test expects 360 degrees, -360 degrees gets reported. Set the standard base translation matrix to resolve this. BUG=b:155944359, b:155944129 TEST=Try CTS BRANCH=None Change-Id: I60aa29b8983d7ab11b42496e4d91b9636dffe163 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2734070 Reviewed-by: Diana Z <dzigterman@chromium.org>
* brya: Add keyboard supportCaveh Jalali2021-03-055-1/+42
| | | | | | | | | | | | | | This adds keyboard support. Brya uses a non-vivaldi style keyboard. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: I6b703f37a773990d81530d4d99b76711efa238e0 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2737548 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* Galtic: Correct active charge port selectionDiana Z2021-03-051-1/+1
| | | | | | | | | | | | | | | | | | During active charge port selection, any port which is not the new active port should have sinking disabled. The current code could leave sinking enabled on C0 when a better charger is inserted into C1, and also shuts off C1 when it is selected with no battery. BRANCH=None BUG=b:176214112 TEST=on galtic, sysjump with no battery and a charger in C1. Observe no brown outs Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ic07a9c5ab35a9edd29717beb7acc9e1c51159b04 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738055 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* OCPC: Skip voltage init with no batteryDiana Z2021-03-051-1/+1
| | | | | | | | | | | | | | | | On systems with no battery present (or a battery which has not yet reported a voltage), skip setting Vsys to the battery voltage. BRANCH=None BUG=b:176214112 TEST=on galtic, sysjump with a charger in C1 and verify initial Vsys is not set to 0 Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I790cd69ec948d4f2ccaad8c7963d8a4883564e1c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738054 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: extend the shim documentation with go/zephyr-shim-how-toJack Rosenthal2021-03-041-0/+166
| | | | | | | | | | | | | | | | | | Revised go/zephyr-shim-how-to, and added in Markdown form to our existing shim documentation. Large documentation CL... hoping to non-minor concerns in follow-up CLs if possible. BUG=b:181253613 BRANCH=none TEST=view in gitiles Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ife666bf06ef76b05b4d3d877049d160706441514 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2737245 Commit-Queue: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* brya: Use fixed fan speedsCaveh Jalali2021-03-043-7/+48
| | | | | | | | | | | | | | | | | | This sets the fan speed based on SoC power state. If the AP is off, run the fan at 33%. If the AP is on, run the fan at 100%. Our sensors are not yet calibrated and we don't have confirmed thermal thresholds for the SoC, so just keep the fan running at full speed when the AP is running. BRANCH=none BUG=b:179975706,b:180681346,b:181271666 TEST=fan is slow before AP boots, then speeds up as soon as AP starts Change-Id: Id10e1510496d94bd3cc8ea70e4661c52d15fe9ed Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2722552 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com>
* byra: Update POW-TECH battery device nameCaveh Jalali2021-03-041-1/+1
| | | | | | | | | | | | | | | | This removes the battery device name so that only the manufacturer name is used to distinguish batteries. There is some uncertainty in how these batteries identify themselves and we can avoid it as we can identify batteries by manufacturer name. BRANCH=none BUG=b:177971846,b:180784200 TEST=EC console reports battery is found Change-Id: Idd65a0dc9f5a00d61358ed1da2c876243095fdc1 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2722551 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* stm32g4: Add support for stm32g473xc variantScott Collyer2021-03-043-6/+67
| | | | | | | | | | | | | | | | | | This CL adds the stm32g473xc variant to the STM32G4 family. The primary change is that the internal flash is increased from 128 to 256kB. In addition, the stm32g431xb flash size is set back to its actual value of 128kB. BUG=b:167462264 BRANCH=None TEST=make -j BOARD=quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I163b6044d48425c70f9e6c5d7e352d5c1dd7df72 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2682783 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Add USB endpoint supportScott Collyer2021-03-045-4/+56
| | | | | | | | | | | | | | | | | | | This CL enables USB-EP for the STM32G4 family. It also fixes backup domain register access issues which are required for fw updates via USB. BUG=b:148493929 BRANCH=None TEST=Verified on quiche that STM32G4 enumerates as an USB endpoint and can be used successfully with fwupd. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I75e6b6e70e9ca2589ace76f0aa0facadd9e94142 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2268139 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* galtic: Enable AP throttlingJacky Wang2021-03-041-0/+1
| | | | | | | | | | | | | | | | | | Add the CONFIG_THROTTLE_AP define to compile common code for throttling the CPU based on the temp sensors. BUG=b:177628854 BRANCH=firmware-dedede-13606.B TEST=make BOARD=galtic 1. Use "watch ectool temps all" to check temperature. 2. Verified pass with EE team. Signed-off-by: Jacky Wang <jacky5_wang@pegatron.corp-partner.google.com> Change-Id: I1e79a38f16afeb54791260e6ad2d486164ebadaf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2734064 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* drobit: Enable AP-driven alt mode entryAbe Levkoy2021-03-041-0/+2
| | | | | | | | | | | | | | | Wait for the AP to direct the EC to enter USB PD alternate modes. BUG=b:150611251,b:181144682 TEST=make buildall; observe alt mode entry BRANCH=firmware-volteer-13672.B-main Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Ia83043e30495861ebd4f0d2c8250d3755b61b851 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2727839 Tested-by: Prashant Malani <pmalani@chromium.org> Tested-by: Eric Herrmann <eherrmann@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* RAA489000: Clear debug accessory state on initDiana Z2021-03-041-0/+15
| | | | | | | | | | | | | | | | | | | | | | During our first boot, clear out any residual state left from past debug accessory connections. In most cases, the TC state machine or PD task init can set open in order to ensure the TCPC doesn't get wedged. However, there is still a lingering corner case when the EC is reset through the security chip on ITE platforms. Always set open during init if we have the power to survive it to catch this case. BRANCH=None BUG=b:177870522 TEST=on galtic, run refresh+power resets with servo_v4 sink plugged in and verify the port does not become stuck. Also run refresh+power resets with a charger and hub plugged in to verify they connect fine after the reset. Also verify battery-less boot still works Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ia25959cae4d42163ac03280a319d785193e29422 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2733916 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* copano,drobit,elemi,lindar,voema: add CONFIG_BYPASS_CBI_EEPROM_WP_CHECKZhuohao Lee2021-03-045-0/+5
| | | | | | | | | | | | | | | In order to bypass the cbi eeprom write protection, we add the config CONFIG_BYPASS_CBI_EEPROM_WP_CHECK to bypass the write protection gpio check. BUG=b:169034911 BRANCH=volteer TEST=`ectool cbi set` is working Change-Id: Ibd1e8af4eb8f7ead506999c4ce3803fa0e341c10 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719725 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* spherion: Reconfig LED conftol, and update Led behaviorBen Chen2021-03-043-61/+21
| | | | | | | | | | | | | | | | | | | | | | CONFIG GPIOA0, GPIOA1, GPIOA2 to INPUT type Supports the LED control Behavior as below Charge: Amber on (S0/S3/S5) Full: Blue on (S0/S3/S5) Discharge in s0: Blue on Discharge in s3: Amber on 1 sec off 3 sec Discharge in s5: off Error: Amber on 1 sec off 1 sec Factory mode: Blue on 2 sec Amber on 2 sec BUG=b:181799732 BRANCH=none TEST=make buildall PASS Change-Id: Ia54bc078cd26b80d8ca44517d72663b1482d0378 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2734062 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* zephyr: Add chargen command supportFabio Baltieri2021-03-045-0/+29
| | | | | | | | | | | | | | | | This adds support for the chargen command. The command is used to test the console output to verify that no data has been lost. To do that, it uses the low level UART APIs, so the normal shell operation is temporarily suspended while the command is running. BRANCH=none BUG=b:177604307 TEST=tested the command in both zerphyr and ECOS builds Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Change-Id: I7e41902ab7d841ebb7b9e14c52337ad18e10ad7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2707104 Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: console_buffer: define uart_buffer_fullFabio Baltieri2021-03-041-0/+6
| | | | | | | | | | | | | | | Define uart_buffer_full in the shimmed console_buffer.c, this is used by chargen, but we can just return false since we don't have buffering in Zephyr for the low level putc/getc functions. BRANCH=none BUG=none TEST=used in chargen Change-Id: If612c63389480d488a92d1c203d4927b54b39896 Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2732021 Reviewed-by: Yuval Peress <peress@chromium.org>
* panicinfo: fix panicinfo double reportEric Yilun Lin2021-03-043-5/+25
| | | | | | | | | | | | | | | | | | | | | | Panicinfo is double report due to the panic flags is reset whenever a hard-reset triggered. This makes AP thinks there is a new panic happened, and reports it to the crashmon. We've seen a lot of crash reports due to the false alarms. The solution is recording the panic flags across hard-reset so we won't keep alarming the old panicinfo. BUG=b:181108236 TEST=1)test that on juniper with new EC RO/RW, and AP reboot won't cause the EC alarming a new panicinfo. 2)test that on juniper with soft-sync RW, and old RO, and AP reboot won't cause the EC alarm a new panicinfo BRANCH=kukui Change-Id: I6e0c33a1fcf210d9aa03ebd1cd79b84a7744c386 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721327 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* cbi: Add CONFIG_BYPASS_CBI_EEPROM_WP_CHECKZhuohao Lee2021-03-042-2/+16
| | | | | | | | | | | | | | | | | | | | | | | In some projects, we modify the cbi eeprom write protection via the hardware design. So, the gpio pin GPIO_WP is decoupled from the cbi eeprom write protection status. With this change, we can update the cbi eeprom data on the fly for the dogfood device during the development. In order to bypass the cbi eeprom write protection check, we add a CONFIG_BYPASS_CBI_EEPROM_WP_CHECK to skip the gpio value. Since this modification is only for the developing device, we add the CONFIG_SYSTEM_UNLOCKED check to avoid someone mis-use this config. BUG=b:169034911 BRANCH=volteer TEST=`ectool cbi set` is working in drobit/copano Change-Id: I3f35159883f75965b1009c45c25ac2cd1c6e7c0d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719724 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* galtic: Fine tune tusb544 EQ settingJacky Wang2021-03-041-0/+103
| | | | | | | | | | | | | | | | Modify strength value setting of tusb544. BUG=b:179224587 BRANCH=firmware-dedede-13606.B TEST=make BOARD=galtic 1. Verified pass by EE. 2. Use "ectool i2cread" to check setting value. Signed-off-by: Jacky Wang <jacky5_wang@pegatron.corp-partner.google.com> Change-Id: I06849c9d94584e484a58cc5e614ce7d4fb60fce6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2726784 Reviewed-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* bb_retimer: Fix port bounds checkCaveh Jalali2021-03-041-1/+1
| | | | | | | | | | | | | This fixes a bounds check in the 'bb' command argument parsing. BRANCH=none BUG=none TEST=EC no longer resets when triggering the off-by-one error Change-Id: I4ff459781c047b3899150485b7fd3fe6363bdec3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2730521 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* charger: Add support for the TI BQ25720Caveh Jalali2021-03-043-6/+40
| | | | | | | | | | | | | | | | This adds support for the BQ25720 charger using the BQ25710 driver. The only significant difference between the two chips is that the VBUS voltage register encoding has changed. The scale changed from 64mV to 96mV and there is no DC offset. BRANCH=none BUG=b:180980490 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I9ab6e066a4dec93a0ede0c22ff21b240a5021cbf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717805 Reviewed-by: Diana Z <dzigterman@chromium.org>
* shuboz/jelboz/jelboz360: Increase power button init timeoutMichael5 Chen12021-03-041-1/+6
| | | | | | | | | | | | | | | | | | Jelboz's battery takes serval seconds to come back from the cutoff state. Recorded about ~4 seconds, so dump the timeout up to 5 second for some margin as well. BUG=b:181736787 BRANCH=zork TEST=Verify DUT will boot up from cutoff a few seconds after AC power is pluning in. Signed-off-by: Michael5 Chen1 <michael5_chen1@pegatron.corp-partner.google.com> Change-Id: I340a9c0df38428b8990123f6bb0d7777d4224980 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2731174 Reviewed-by: Jacky Wang <jacky5_wang@pegatron.corp-partner.google.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* burnet: Add 2nd lid/base accel sourceDevin Lu2021-03-043-4/+129
| | | | | | | | | | | | | | | | This patch add one more source for lid/base accel. lid accel - kx022 base accel - icm-40608 BUG=b:181627606, b:173647487 BRANCH=firmware-kukui-12573.B TEST=ectool motionsense Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I069f1898c7454805e4475e7637432c4a8423103c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2730948 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* TCPMv1/v2: Move SOP' enabling to tcpm_set_vconnEric Herrmann2021-03-045-11/+29
| | | | | | | | | | | | | | | | | Currently SOP' enabling is done as part of the TCPCI driver when vconn is set - however if we aren't using VCONN from the TCPC, we need to enable SOP' separately. So, instead of enabling it in the TCPCI driver, enable it in the general TCPM set VCONN function. BUG=b:181692098,b:181691263,b:173459141 TEST=Make sure cable discovery works TEST=make buildall BRANCH=None Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: Iecc06760f2b8af588c427b9565c6aa31ee719edf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2733574 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* TCPMv2: Change PD_T_PS_SOURCE_OFF valueEric Herrmann2021-03-031-1/+1
| | | | | | | | | | | | | | | | | | | PD_T_PS_SOURCE_OFF is 750 to 920 ms, currently it is set to the maximum value. But, we need to detect the state and take the exit action within this maximum time, which leaves no room for overhead if this is set to the maximum value. Instead, set to the midpoint value of 835ms. BUG=b:181055620 TEST=TD.PD.FRSISNK3.E5 on Voxel BRANCH=None Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: I4b2b75332774ca0fb8e0913053739da6d58d428a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2730631 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* mchp: Disable BGPO on pin used in GPIO listScott Worley2021-03-034-0/+65
| | | | | | | | | | | | | | | | | | | | | Microchip MEC parts have a small number of GPIO pins that default to a mode controlled by VBAT powered logic. When configured for VBAT operation the GPIO control register is bypassed. This change switches any of these pins in the GPIO list back to GPIO control. BRANCH=none BUG=none TEST=Manually check pins are no longer controlled by VBAT logic. Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I2d78365b61616ccce568810aecd81fe882e90200 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717742 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Poornima Tom <poornima.tom@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: fix AP power cycling on sysjumpYuval Peress2021-03-033-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | When running the sysjump, the AP was power cycling. This was caused by the jdata address no longer being correct since the swap to Zephyr 2.5. Previously, the sram0 device tree entry defined a register size of 0x10000, which needed to have 0x800 bytes removed as part of the boot ram size. This can be seen in https://github.com/zephyrproject-rtos/zephyr/blob/v2.4-branch/dts/arm/nuvoton/npcx7m6fb.dtsi#L35 In Zephyr 2.5, the sram0 size was corrected to 62k to account for the boot ram size. As can be seen in https://github.com/zephyrproject-rtos/zephyr/blob/master/dts/arm/nuvoton/npcx7m6fb.dtsi#L21 This is also true for npcx7m6fc and npcx7m7fc. BRANCH=none BUG=b:181599787 TEST=build and falsh volteer, see correct value returned for system_jumped_to_this_image() Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Icf063ec220d17ebe6a012506e4626702bdf9e149 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2732935 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Octopus: Re-enable VCONN sourcing from TCPCEric Herrmann2021-03-036-1/+15
| | | | | | | | | | | | | | | | | | | The SYV682 shouldn't have VCONN supplied to its host side CC pins, but on Octopus these pins aren't used and the TCPC must provide VCONN. Since this is a non-standard configuration, make an exception for these Octopus boards by defining a new SYV682 flag to indicate that it does not pass through CC. BUG=b:180973460 TEST=make buildall BRANCH=None Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: I043b6025abbeeaaf9e261d2721da3aed5483e177 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721234 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Marco Chen <marcochen@chromium.org>
* TCPMv2: Don't cflush in CC_OPEN with batteryEric Herrmann2021-03-031-2/+8
| | | | | | | | | | | | | | | | | | | | | | In the TC state machine, on entry to CC_OPEN we disable vbus/vconn, print a message, flush the console, then disable CC. But this takes too long to meet the tProtErrHardReset, which causes some compliance failures. The main culprit is the console flush. The justification for the console flush is that we may brown out, so this isn't necessary when we have a battery. Only do the console flush on entry to CC_OPEN when we don't have a battery. BUG=b:181053528 TEST=Compliance test TD.PD.FRSISNK3.E3 on Voxel BRANCH=None Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: Ia056f3c3010737e18c02a7a80659da201cfe5f92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2730630 Reviewed-by: Diana Z <dzigterman@chromium.org>
* mancomb: Create mancomb baseboard and variantRob Barnes2021-03-0311-0/+1606
| | | | | | | | | | | | | | | This is a full copy paste of guybrush just with guybrush replaced with mancomb. Follow up CLs will make required changes so it's clear what changed between guybrush and mancomb. BUG=b:174424094, b:181510382 TEST=Build BRANCH=None Change-Id: I16f00e2749ab466e619b77925b25b275aca67a6c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2727634 Reviewed-by: Diana Z <dzigterman@chromium.org>
* eldrid: only logged when the fan speed level is changedScott Chao2021-03-031-3/+10
| | | | | | | | | | | | BUG=b:181695381 BRANCH=firmware-volteer-13672.B-master TEST=make buildall Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Id16c9cef804a5d14ab35500e5fa18172c474710f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2731167 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: Fix version commandYuval Peress2021-03-031-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current config_chip used by Zephyr defaulted to setting the RO header size and offset to 0 if the header was turned off. This isn't correct as the CONFIG_PLATFORM_EC_RO_HEADER just tells us whether or not to generate the header, whereas the _SIZE and _OFFSET values should still be there even in the RW image. Now running `version` from both the RO and RW image shows: 21-03-02 21:28:21.455 Chip: chromeos emu 21-03-02 21:28:21.460 Board: 1 21-03-02 21:28:21.486 RO: _v2.0.7727+3f8b76fa7 21-03-02 21:28:21.496 RW: _v2.0.7727+3f8b76fa7 21-03-02 21:28:21.497 Build: _v2.0.7727+3f8b76fa7 21-03-02 21:28:21.500 2021-03-02 21:01:09 BRANCH=none BUG=b:181599007 TEST=built/flashed volteer and ran `version` from both RO and RW images Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I435f224fc2b3b3a5ca54d3335ea8cd50e9ab5a2e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2731287 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* baseboard/kukui: enable hibernation on it81202 based boardsDino Li2021-03-031-1/+1
| | | | | | | | | | | | | | | | With this change, system is able to enter hibernate to reduce EC power number to lowest. BUG=b:180668427 BRANCH=none TEST=On icarus, power down system to G3 with battery only. Run "hibernate" command to let system enter hibernate. EC's power number is reduced to about 0.7mw. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I3ae258810e239b870afa5096cb573952101e6702 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2731175 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
View Lorry Controller Status