| Commit message (Collapse) | Author | Age | Files | Lines |
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There is 0.1V leakage from Charger to Vbus
when a charger is removed in S5.
Control ASGATE state to prevent the leakage.
This commit uses the charger side registers to
control the ASGATE when selecting our active charge port.
This is done in addition to the existing implementation
which uses the TCPCI registers to control ASGATE.
BUG=b:189299803
BRANCH=dedede
TEST=Build and flash Cret, the leakage has been improved
from 0.1V to 0.001V
Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com>
Change-Id: Ib81ca651b0708149fae7b4df27f66107b47f8490
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2948604
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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This CL implements vivald function row config for magister
keyboard by board version. Magister board version define >= 5,
and other was reserved.
Switch keyboard_mask_refresh values ROW value by keyboard ID pin.
BUG=b:184615827
BRANCH=dedede
TEST=verify keycode is correct in `evtest
Change-Id: Id680947b641a8a571d2ab9dd9981b33426eced9f
Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2940330
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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add overridable function, it can use the share EC image
where different keyboard layout with respect to the keyboard
row on which the refresh key lives.
BUG=b:184615827
BRANCH=dedede
TEST=make buildall PASS
Change-Id: I0dd82c619e09947dd00bef75e352c6266cb1182d
Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2952284
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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change volume up/down of ADC thresholds value.
BUG=b:167319238
BRANCH=master
TEST=Press Vol+- button function work.
Change-Id: Iddb688832ca5bd343c9e6b577cd129c0895fd7dc
Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2952283
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Affected boards (only STM32H7):
- nocturne_fp (dartmonkey)
- nucleo-h743zi
This fixes problem with jumping to RW when reboot to RO was requested.
Log from reproduction on dartmonkey (only relevant parts):
--- UART initialized after reboot ---
[Image: RO, dartmonkey_v2.0.8961+9a30ce07ee]
[Reset cause: reset-pin power-on soft ap-off]
...
[1.045743 Jumping to image RW]
*** We are in RW. Jump data are initialized and contains correct
*** set of reset flags. Reset flags from backup RAM are cleared.
reset flags from chip: unknown
reset flags from jump data: reset-pin power-on soft sysjump ap-off
[1.056198 UART initialized after sysjump]
[Image: RW, dartmonkey_v2.0.8961+9a30ce07ee]
[Reset cause: reset-pin power-on soft sysjump ap-off]
...
>
> reboot ro
reboot ro
Rebooting!
*** Now we are in RO. RW saved reset cause in backup RAM (with
*** stay-in-ro). Please note that RO also finds jump data and
*** report that was sysjump!
reset flags from chip: reset-pin power-on soft ap-off stay-in-ro
reset flags from jump data: reset-pin power-on soft sysjump ap-off
[1.056198 UART initialized after sysjump]
[Image: RO, dartmonkey_v2.0.8961+9a30ce07ee]
[Reset cause: reset-pin power-on soft sysjump ap-off]
When RO is doing sysjump to RW, jump data structure is created in
jump_to_image() function. The structure contains information about
reset flags. When RW finds jump data in system_common_pre_init() magic
field of the structure is set to zero to prevent detecting sysjump
accidentally. Nevertheless, when reboot to RO is requested, RO is able
to find the structure. As a result, correct reset flags from backup RAM
are overwritten by incorrect reset flags from jump data.
This happens because we are not flushing D-cache before reboot.
All changes in RW which lives in cache (not saved in RAM) will be lost
after reboot because cache is always disabled (even if it was
previously enabled and we didn't turned it off). To enable cache we need
to invalidate it first (see cpu_enable_caches()).
Issue reproduces also with debugger connected, except situation when
watchpoint is set on jump data magic field.
BUG=b:170432597 b:188934337
BRANCH=none
TEST=Compile dartmonkey firmware and run it on eg. icetower.
In RW, issue 'reboot ro'. Make sure that jump to RO is not
performed.
TEST=Run flash_write_protect hardware unit test on icetower board
using `./test/run_device_tests.py --board dartmonkey \
--tests flash_write_protect`
Make sure that after reboot to RO, 'stay-in-ro' reset cause is
printed
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: If56153a1a3ac7ae05700eac9ca60e398cf35f182
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922145
Reviewed-by: Craig Hesling <hesling@chromium.org>
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This CL reset and re-initialize SPI module after AP jumped to BL.
So EC will have a good state to start receiving AP's commands.
BRANCH=icarus
BUG=b:184702635
TEST=on cozmo, confirm that EC doesn't miss the first command from
AP after booting.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ib7cf0e9cb70a67950d53d3abc7df42969c9b4dc2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947422
Tested-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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The code coverage plugin requires that the paths are relative to the
repo, so we need to strip off the path above the repo's top level.
BRANCH=None
BUG=b:156895937
TEST=`make coverage ; grep SF: build/coverage/lcov.info` and observe
that the source paths are now relative to the repo, instead of
starting with /mnt/source
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iba86badeefd7359b72cb7e04cf97b0e51eed6789
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2950569
Tested-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
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This patch enables the uart command, chargen by default. It generates
a series of alphanumeric chractecters, and is useful in testing UART
related modules with a stress workload.
This patch occupies 400 bytes or so in flash memory of RW image.
BUG=b:158477297
BRANCH=all
TEST=ran it on Atlas, Puff, and Volteer.
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Cq-Depend: chromium:1679710,chromium:1554198,chromium:2080933,chromium:2217112
Change-Id: I3c0407e7a4a6d3bb8d998e3e5618be5769192a8c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2951863
Reviewed-by: Craig Hesling <hesling@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This patch excludes CONFIG_CMD_CHARGEN from stm32f4 build config set
explicitly. stm32f4 has its own USB console implementation, which
chargen doesn't support yet. The affected boards are polyberry,
sweetberry and stm32f446e-eval.
BUG=none
BRANCH=all
TEST=buildall
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: I0f3dadd55fa2c197fff32afbe3fecb773491003e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2951862
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The led behavior define as following:
Power Led behaiver:
1.S0, Green (soild on)
2.S3, Orange (1s on 3s off)
3.S5, off
Battery Led behaiver:
1.Red on S0/S3/S5, battery capa < 5%
2.Orange on S0/S3/S5, 5% < battery capa < 97%
3.Green on S0/S3/S5, battery capa > 97%
4.Battery error: Red on 1sec off 1sec
5.Factory test: Red on 2sec, Green on 2sec
BUG=b:187539586
TEST=make -j BOARD=homestar
Verify build on EVT board
Make sure ectool led battery red/green/amber/off/auto work correctly.
BRANCH=Trogdo
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Change-Id: I0ace830d9b728cbd43ed53592d5091a579197b0b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2949629
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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BUG=b:190459738
BRANCH=none
TEST=make buildall
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Ic78bb80ee647e8cab5b97e344882c9671a886fdc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939174
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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BUG=b:190567710
BRANCH=None
TEST=make BOARD=primus
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I2d430eb20689ffd8df5e370d0ff810da2669efea
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939162
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Primus only support clamshell form factor.
And also remove ALS sensor support since Primus don't have it.
BUG=b:190518316
BRANCH=None
TEST=make -j BOARD=primus
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: If134c28dfdba30f5d7373899a4ca5a040476c553
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939171
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
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Some port partners may offer a very low initial source capbility (ex. 5V
at 100mA) and then very quickly follow with full source capabilities.
When this happens, cancel any queued PR swap requests since we now wish
to charge from this port partner.
BRANCH=None
BUG=b:190506779
TEST=on guybrush, ensure Apple 3-in-1 connects without any unnecessary
PR swaps
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ia51efc8e17d950a0abb818b7da0f99d598affbe3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947622
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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Affected boards (only STM32H7):
- nocturne_fp (dartmonkey)
- nucleo-h743zi
This fixes problem with RO reporting 'sysjump' reset cause, but not
'watchdog' after issuing 'crash watchdog' command. Also, problem with
missing task ID and PC in saved panic data was fixed too.
These problems come from not flushing cache before reset occurs.
When cache is enabled, it's not guaranteed that all memory changes
will be saved in RAM. After reboot, cache is invalidated, so some
of memory changes will be lost. In this case, 'magic' field from
jump_data structure was not zeroed and part of panic data was missing.
It caused RO to report sysjump after watchdog was triggered, and
missing 'watchdog' reset cause (RO used reset cause from jump data).
BUG=b:170432597
BRANCH=none
TEST=Compile dartmonkey firmware and run it on eg. icetower.
In RW, issue 'crash watchdog'. Make sure that RO reports 'watchdog'
reset cause. After sysjump to RW check panic data using 'panicinfo'
command. Especially the following:
- R4 register (crash reason) should be set to 0xdead6664 (watchdog)
- R5 register (info) should be set to PC
- PROCESS EXCEPTION value should be set to task ID
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: Ie8d861e5a07b58140445aeaa191cc0098618401b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923504
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Affected boards (only STM32H7):
- nocturne_fp (dartmonkey)
- nucleo-h743zi
After writing panic information it is good to flush cache to make sure
that all changes are in RAM. Without this, 'panicinfo' will report
incorrect values after reboot.
BUG=b:170432597
BRANCH=none
TEST=Compile dartmonkey firmware and run it on eg. icetower.
In RW, use 'crash' command to trigger panic (do not use
'crash watchdog' it uses different path). Make sure that after
sysjump to RW panic data contains correct information.
Panic data can be dumped using 'panicinfo' command.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: Iabe2b1de00683d95f55a3124b46dfa600f8ac0bf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923503
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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We stuffed an external pull-up resistor on the GPIO HIBERNATE_L for
fixing the CCD bugs, like b/173828265, b/177611071.
The GPIO can be used as open drain.
BRANCH=Trogdor
BUG=b:189184814
TEST=Tested on Lazor; CCD connection still worked under EC hibernate.
Change-Id: I50d832f1619f976a4cb682fa1b666add96563222
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2950925
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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Enable watchdog config on board it8xxx2_evb and hayato.
BUG=b:187190711
BRANCH=none
TEST=on it8xxx2_evb,
1.console cmd "waitms 1500": print message and not reset
21-05-20 13:38:06.302 --- UART initialized after reboot ---
21-05-20 13:38:06.315 [Image: RO, it8xxx2_evb_zephyr_v2.0.8855-5b
2021-05-20 13]
21-05-20 13:38:06.333 [Reset cause: unknown]
21-05-20 13:38:06.340 ec wdt init
21-05-20 13:38:07.453 Watchdog deadline is close!
21-05-20 13:38:07.851 [1.569641 event set 0x0000000000002000]
21-05-20 13:38:07.869 [1.581176 hostcmd init 0x0000000000002000]
21-05-20 13:38:07.954 uart:~$
2.console cmd "waitms 1601": print message and reset
21-05-20 13:41:33.908 --- UART initialized after reboot ---
21-05-20 13:41:33.919 [Image: RO, it8xxx2_evb_zephyr_v2.0.8855+5b
2021-05-20 13]
21-05-20 13:41:33.935 [Reset cause: unknown]
21-05-20 13:41:33.942 ec wdt init
21-05-20 13:41:35.055 Watchdog deadline is close!
21-05-20 13:41:35.560 *** Booting Zephyr OS build zephyr
-v2.5.0-87-ga0c36e043cf*
Cq-Depend: chromium:2936162
Change-Id: Ia465951d71043a469ed78d4089dfb6af30c5999e
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905171
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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We need to add a condition for vbusmv to avoid that
when the vbus_mv value is small but not zero vbus_mv,
it is still considered as an adapter and open asgate.
BUG=b:189090988
BRANCH=dedede
TEST=make BOARD=storo
Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
Change-Id: Ic046e65ed69f8616d6bc7d8ca28fc27cf894ed07
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2949627
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Add the I2C ports used by USB-C, so we can support charging.
BUG=b:189855648
BRANCH=none
TEST=with other CLs, build asurada for Zephyr
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I59ce2ad3b9158cf01dac7d89ab56c46c668a07e4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941813
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
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Suppress warning for -EINVAL on k_delayed_work_submit. It indicates that
the work is already pending or executing, which is normally harmless.
Verified it for charge_manager_refresh.
BRANCH=none
BUG=b:190214907
TEST=build and run on volteer
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I7048ad15bbb99fc43b663b4f2c6624166a05f0dd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2949054
Reviewed-by: Yuval Peress <peress@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Yuval Peress <peress@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Replacing usleep() with udelay() fixes problem with Forced Hard Fault
during rollback_entropy hardware unit test (more precisely, when
rollback entropy is added).
Function rollback_update() calls unlock_rollback() before erasing
rollback region. Surprisingly, unlock_rollback() also disables
interrupts to "minimize time protection is left open". Next
flash_erase() is called and then flash_physical_erase().
If erase operation is not finished, we will call usleep() to yield
CPU to some other task. It sounds good, but remember that interrupts
are still disabled. To switch context we need to use SVCall exception
(see svc_handler()) which is masked when interrupts are disabled.
Sometimes sector was erased before we checked, so no usleep() was
called. That's why it was not reproducing always.
Why Forced Hard Fault occurs when calling SVC with disabled interrupts?
First of all, we need to know that some exceptions have configurable
priority, SVCall belongs to this group (full list can be found at
2.4.2 Exception types PM0253 Rev 5 p.40). Next thing is that we are
using 'CPSID I' instruction to disable interrutps. The instruction
actually sets PRIMASK register (3.12.2 CPS PM0253 Rev 5 p.176). When
PRIMASK register is set it prevents activation of all exceptions with
configurable priority (PM0253 Rev 5 p.25), so SVCall is masked too.
OK! But why we get Forced Hard Fault?
Hard Fault is 'Forced' when some other fault was escalated to Hard Fault
(FORCED bit is set in HFSR register). 2.5.2 Fault escalation and hard
faults PM0253 Rev 5 p.48 provides us information when escalation to Hard
Fault occurs, among others it can occur when "A fault occurs and the
handler for that fault is not enabled".
BUG=b:170432597, b:180761547
BRANCH=none
TEST=Connect icetower using microservo.
sudo servod --board icetower
./test/run_device_tests.py --board dartmonkey
--test rollback_entropy
Make sure that test is passed and no Hard Fault occur.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I0dc1dae899b81574456a127db9c5e7a498a6f69e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939676
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Add battery information so we can support charging.
BUG=b:189855648
BRANCH=none
TEST=with other CLs, build asurada for Zephyr
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I638c5789a2a494bdf811c13f66d5b892f4ebded2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941812
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
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The current cros,kb-raw-npcx driver relies on the label cros_kb_raw
instead of the compatible string like it should. Since currently, it
doesn't make sense for there to be more than one instance of the
driver, a new BUILD_ASSERT check is added to make sure that if the
driver is added via Kconfig, it is also used exactly once. Further,
the creation of the driver via DEVICE_DEFINE is now using
DT_DRV_COMPAT to create the instance.
BRANCH=none
BUG=b:190457512
TEST=build brya, volteer, and lazor
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I242c0f2f20a6d89cad7ab4269fc4c854aa29554b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2944624
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Dawid Niedzwiecki <dawidn@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Branch=none
Bug=b:190523663
Test=build ec image and test on adlrvp. cbi set/get works OK
Change-Id: I51cae596a389a3859dccbb893495bb9b25172098
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947901
Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
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Fixed a couple of post-merge Kconfig requests.
BUG=b:180980668,b:189857004
BRANCH=none
TEST=make buildall
TEST=zmake configure -b $PROJ_HAYATO
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: Ie891450909196cae10b4f6bdf2009f0338bb988e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947227
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
Auto-Submit: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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For the ITE chip, use CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS instead
of CONFIG_PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS.
BUG=b:187190711
BRANCH=none
TEST=zmake -lDEBUG configure -B zephyr/build
-b zephyr/projects/it8xxx2_evb
zmake -lDEBUG configure -B zephyr/build
-b zephyr/projects/asurada/hayato
Cq-Depend: chromium:2936162
Change-Id: If4d61d72763de9326a3056b6848f0ca90f27746c
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914711
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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The names conflict when enabling both Zephyr's flash driver and
CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h
BUG=b:187192628
BRANCH=none
TEST=make buildall -j4
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Enable the I2C_PASSTHRU_RESTRICTED config for Lazor.
Define board_allow_i2c_passthru function in platform-specific code.
BUG=b:188885798
BRANCH=none
TEST=Verify that I2C_PASSTHRU command works properly e.g. DUT displays
the battery level correctly.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: Icf8a13f1c3aaecc660322a2153654c70c1accd7b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939675
Reviewed-by: Yuval Peress <peress@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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BUG=b:190577105
TEST=make
BRANCH=trogdor
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I1804aecd01459f9cb45dfba8fc99dab950a0db58
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2948111
Tested-by: Ting Shen <phoenixshen@chromium.org>
Auto-Submit: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
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A few of these are missing. Update them so we can use the full ADC
capabilities, needed for Zephyr.
BUG=b:189855648
BRANCH=none
TEST=with other CLs, build asurada for Zephyr
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I9d52404086b3aa8dda847a015a264d1fcfd805f9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941811
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
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Add a separate public header for this chip so we can include it from
Zephyr.
Drop the #ifdef since the linker will give an error if the function is
missing.
BUG=b:189855648
BRANCH=none
TEST=make BOARD=hayato -j30
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ic4c755da2b576d6cd3465cfd803dfb0e4ad0fbef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941810
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
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Add a separate public header for this chip so we can include it from
Zephyr.
BUG=b:189855648
BRANCH=none
TEST=make BOARD=hayato -j30
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ieefe30bbacac0fea2132355c88626525fa37c3d2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941809
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
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Add a separate public header for this chip so we can include it from
Zephyr.
BUG=b:189855648
BRANCH=none
TEST=make BOARD=hayato -j30
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Idf2cfbf31e32880ca8cb7d5e72ba0d844cda31b9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941808
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
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Kconfig generates an autoconf.h header from the various Kconfig files.
These values (such as CONFIG_FLASH_SIZE) may not be obvious to find.
This is especially true since some Kconfig values are passed in from
zmake while others reside in Kconfig files.
Add a utility to get the #define value from the autoconf.h that's
generated during the build.
BRANCH=none
BUG=b:190435084
TEST=Added unit tests
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: Id2c1f05a809e17f67a435209e35606ffd7245174
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2948168
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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In CQ some tests that require file access may take a long time.
Update the deadline for the tests to 1 minute which matches the
deadline of tests in test_util.py.
BRANCH=none
BUG=b:188492664
TEST=run pytest (but the real test will be in CQ)
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I00b15667bf4bdbbfe8101b21a58aefdce6d4ec91
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2948164
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Disable the host command debugging by default. This matches the
Chromium-EC configuration and lessens the amount of console spam.
BUG=none
BRANCH=none
TEST=Build zephyr for lazor, verify hostcmd console channel is disabled.
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I5420a6fcb4f71c71f0c00e2de8c087b87925b3f1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947581
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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Remove config entries CONFIG_I2C_VIRTUAL_BATTERY (fixed) and
CONFIG_SPI_MASTER (obsolete) from the config_allowed.txt list.
BUG=none
BRANCH=none
TEST=zmake testall
TEST=make BOARD=volteer
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I660fd460ff0c95b6de911d1d2324bff004660984
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2946965
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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Add a KConfig option to enable/disable the CONFIG_CONSOLE_CHANNEL
option. Enabled by default, but can be turned off to save code space.
BUG=b:180421120
BRANCH=none
TEST=zmake testall
TEST=Boot lazor, verify 'chan' command is present or not based on this
config.
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I9f5f10582ef6161a38bb2f5f7f48bae631ba9cf6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2946964
Commit-Queue: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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Update the motion_sense.h address macros to reflect our current i2c
terms, and also to specify that these are used exclusively in the
accelerometer code.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ibad287df2ba1ecd0b6f3061599476636ac7a5354
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2946316
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BRANCH=none
BUG=b:188605676
TEST=`ksstate on` in EC console, observe keyboard matrix in real time
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I1b0d26b4ade8298bc91dec2df274d9a159e9bc39
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932462
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Add the I2C_PASSTHRU_RESTRICTED config to Zephyr.
BUG=b:188885798
BRANCH=none
TEST=zmake testall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: I8338921da350cbe0a24f12686aa6ff06de57eca6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939674
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Add a separate public header for this chip so we can include it from
Zephyr.
BUG=b:189855648
BRANCH=none
TEST=make BOARD=hayato -j30
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Iaf93bf7f0f7336b17d06bd5c5691624a3877a43b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941807
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
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BUG=none
TEST=no "Not enough power to boot (-1 %, 7500 mW)" spamming in S5
BRANCH=main
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Ie6a4d85455f440430286aedb658a7e6cea8554ef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2948110
Tested-by: Ting Shen <phoenixshen@chromium.org>
Auto-Submit: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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Remove the Try.SRC configuration, as it more closely matches the
behaviors of most released PD DRP products and should represent
an improvement to interoperability.
BRANCH=None
BUG=b:189862847
TEST=on guybrush, successfully connect TBT dock, powered Woohubs,
and powered HooToo
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Iac7cd0dec612d5c9090562eea5a0422ceeba01e8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947497
Reviewed-by: Rob Barnes <robbarnes@google.com>
Commit-Queue: Rob Barnes <robbarnes@google.com>
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The TMP112 sensors will be tied to S5 rails, so init them as we
power transition on boards past version 1.
BRANCH=None
BUG=b:188539950
TEST=on guybrush version 1, power on and verify no errors are present
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I74efb7e360329f05b33c845d556c0557d89668f9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2940575
Reviewed-by: Rob Barnes <robbarnes@google.com>
Commit-Queue: Rob Barnes <robbarnes@google.com>
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modify voltage range of ADC button
Before: After:
^
| No pressed
-------2.7v -> 2.78v
|
-------2.69v -> 2.74v
| V-
-------2.6v
|
-------2.49v -> 2.54v
| V+
-------2.4v
|
-------2.29v -> 2.3v
| V+ and V-
v
BUG=b:190330515
BRANCH=dedede
TEST=factory check 4 fail device pass
Signed-off-by: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com>
Change-Id: Ibee2977086b57818588e60ff5d35291ddc2e5827
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2940335
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Add HDMI enable/disable condition(by FW_Conifg).
BUG=b:189415302
BRANCH=dedede
TEST=make BOARD=cret
Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com>
Change-Id: Ie7d844cb0b5f626cfdba21bc11ed5cb2af266353
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2942527
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Add the 17th bit of fw-config to judge whether
it supports HDMI feature.
BUG=b:189415302 b:183301456
BRANCH=dedede
TEST=make BOARD=cret
Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com>
Change-Id: I4f1ee675a0be75173a720632d99c102327d33aa3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939175
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Add this file so that it doesn't complain for people who want to use
ctags.
BUG=none
BRANCH=none
TEST=see that 'git status' doesn't show 'ctags' anymore
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ia0e532d277c80243aed9fa834193ed9137078466
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941806
Reviewed-by: Yuval Peress <peress@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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