| Commit message (Collapse) | Author | Age | Files | Lines |
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Copy guybrush baseboard code for charging and port to Zephyr.
BRANCH=None
BUG=b:195137794
TEST=PD negotiation works on both ports
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I4712d3e1422a41c34d3009eb3bfff4d1c79dc971
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3238145
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Increase AC prochot limit to 5A. Actual limit is 5120 mA because it must
be a multiple of 128 mA. Without this change 100W chargers will cause
prochot to be asserted.
BUG=b:204440270,b:204386852,b:202754460
TEST=Boot with 90W charger, prochot not asserted
BRANCH=None
Change-Id: If006f631d7fdd3ba25e90a0647e2e0bf461be11a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3254020
Reviewed-by: Diana Z <dzigterman@chromium.org>
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This adds a new config option to enable the PSYS monitoring feature on
the BQ25710, BQ25720 chargers. The register definition for configuring
PSYS on the BQ25720 is expanded to 2 bits, giving more control to meaure
battery and AC separately. We keep it simple and include both when
measurement is enabled.
BRANCH=none
BUG=b:195615830
TEST=with rest of patch series, psys values reported by
dump_intel_rapl_consumption look reasonable
Change-Id: I0f299c6a24d20ef5bdcda13de74b30ba0c2d5d3c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3253076
Reviewed-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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The timestamp_t and get_time() utilities are defined in timer.h.
BRANCH=None
BUG=b:195137794
TEST=zmake testall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ib53714d30af7e2bf6b97e0b6fdd4acab228dfbde
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252342
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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There was already a CONFIG option for this retimer, but the config
option should translate into building it as well.
BRANCH=None
BUG=b:195137794
TEST=zmake testall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I68c4d7511b0e83d5aae5fd33d5504d112ba9e06f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252341
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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CONFIG_USB_MUX_RUNTIME_CONFIG should be independent of whether a board
is setting up runtime TCPCs. Since
CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG is default of y, this means
some boards now need to set it to n explicitly.
BRANCH=None
BUG=b:195137794
TEST=zmake testall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I12bbb5ab1bf00dd3d56c0c960881df0774b381fe
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252340
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Mfgacc_support will write OperationStatus(0x0054)
to MANUFACTURER_ACCESS(0x00), and then read
back from ALT_MANUFACTURER_ACCESS(0x44).
However, batteries for cret, need to write ALT_MANUFACTURER_ACCESS
instead of MANUFACTURER_ACCESS.
Cret should read status directly from MANUFACTURER_ACCESS.
This CL remove mfgacc_support, and modify D-FET mask bit.
BUG=b:204285159
BRANCH=dedede
TEST=Test on Cret, can boot up from battery cutoff, ec reboot via dc and
ac+dc, charge and discharge.
Signed-off-by: elmo_lan <elmo_lan@compal.corp-partner.google.com>
Change-Id: Iaeb32fcecf851a1241ff2ea82e52cef3ecfdd9c0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3251216
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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This enables TCPC based VCONN control for port C1 (ps8815).
BRANCH=none
BUG=b:204102039
TEST=with reset of patch stack, external monitor links up using active
TBT4 cable
Change-Id: I60482dfff657b53f533b6e72507776b3657a5ff5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252411
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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This adds a port flag to indicate that its TCPC needs to control VCONN.
We have a global compile time flag (CONFIG_USB_PD_TCPC_VCONN) to enable
TCPC control of VCONN. However, on some device architectures, such a
global setting is not suitable for all ports in the system. So, add a
port flag to enable VCONN control where it would otherwise be disabled.
BRANCH=none
BUG=b:204102039
TEST=with reset of patch stack, external monitor links up using active
TBT4 cable
Change-Id: I9028f65a8b10b2f8eb5b614a256d90e05064b4c3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252410
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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clang warns:
power/common.c:118:28: error: implicit conversion from enumeration type 'enum
gpio_signal' to different enumeration type 'enum espi_vw_signal'
[-Werror,-Wenum-conversion]
return espi_vw_get_wire(signal);
~~~~~~~~~~~~~~~~ ^~~~~~
power/common.c:128:36: error: implicit conversion from enumeration type 'enum
gpio_signal' to different enumeration type 'enum espi_vw_signal'
[-Werror,-Wenum-conversion]
return espi_vw_disable_wire_int(signal);
~~~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~
power/common.c:138:35: error: implicit conversion from enumeration type 'enum
gpio_signal' to different enumeration type 'enum espi_vw_signal'
[-Werror,-Wenum-conversion]
return espi_vw_enable_wire_int(signal);
The conversion appears to be intentional, so add an explicit cast.
BRANCH=none
BUG=b:172020503
TEST=make CC=arm-none-eabi-clang BOARD=elm -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ide2abc115957385097f6ed938b0a15139cbf3d83
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3197755
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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"-Oz" is like "-Os" (and thus "-O2"), but reduces code size further.
dartmonkey, clang, -Os:
RO: 733500 flash remaining
RW: 979488 flash remaining
dartmonkey, clang, -Oz:
RO: 737980 flash remaining
RW: 984776 flash remaining
BRANCH=none
BUG=b:172020503
TEST=make buildall
TEST=CC=clang make BOARD=dartmonkey
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ia787845ffdeff26134162007a621b902bbc0d051
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3199737
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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When building metaknight with clang, it warns:
driver/accelgyro_lsm6dsm.c:193:5: error: array index 2 is past the end
of the array (which contains 2 elements) [-Werror,-Warray-bounds]
decimators[FIFO_DEV_MAG]);
^ ~~~~~~~~~~~~
driver/accelgyro_lsm6dsm.c:133:2: note: array 'decimators' declared here
uint8_t decimators[FIFO_DEV_NUM] = { 0 };
^
In the case of metaknight, IS_ENABLED(CONFIG_LSM6DSM_SEC_I2C) should
evaluate to false and we will never hit this issue. Adding an ASSERT
makes clang happy.
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=metaknight
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Id81f51fccb256f281dd5de0c52d0c0008e2a6787
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3197754
Reviewed-by: Keith Short <keithshort@chromium.org>
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Without a text section clang/lld will create one and put it at an
address it selects. Even though the section it creates is empty, if the
LMA is beyond the end of the flash, ec.bin will be too large since the
empty space is filled with 0xFF.
For example, before this change servo_micro's ec.bin is 131075 bytes
instead of 131072 (0x20000) bytes.
Examining the sections, we see the LMA is 0x08020003, which is three
bytes beyond the flash size (0x08000000 + 0x20000 + 0x3):
arm-none-eabi-objdump -h build/servo_micro/ec.obj
Sections:
Idx Name Size VMA LMA File off Algn
...
3 .text 00000000 08014b90 08020003 00024b90 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
...
After this change, servo_micro's ec.bin is the correct size: 131072
(0x20000) bytes.
Now the .text section is at the beginning of flash:
arm-none-eabi-objdump -h build/servo_micro/ec.obj
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000000 08000000 08000000 000000f4 2**2
ALLOC, READONLY, CODE
...
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I48f8019fe6b77f880de0d1a0a4a176b3506f3579
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3248887
Reviewed-by: Keith Short <keithshort@chromium.org>
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It seems that the logical condition of an ifdef had been accidentally
negated. Furthermore, in cases where full duplex support is present,
the control flow should reach the final else branch of the if
statement, which it previously would not when a full duplex
transaction was requested. These two mistakes makes it such that SPI
full duplex forwarding from USB cannot work on e.g. servo v4 (and on
the future HyperDebug board that I am working on.) I have tested this
change as part of my HyperDebug code under development, as well as
tested that the change compiles on servo_micro. I have not attempted
full duplex transactions on servo micro, as I do not currently have a
setup that I can use to easily verify. Looking at the code, one can
convince oneself that behavior can only change in cases where the code
would previously either reject a transaction explicitly, or silently
drop it resulting in USB timeout.
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
BUG=b:192262089
BRANCH=None
TEST=make BOARD=servo_micro
Change-Id: I5767d91c5b1ada4e54eec7ecd0512345448288e7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3253432
Commit-Queue: Jes Klinke <jbk@chromium.org>
Commit-Queue: Brian J. Nemec <bnemec@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
Auto-Submit: Jes Klinke <jbk@chromium.org>
Reviewed-by: Brian J. Nemec <bnemec@chromium.org>
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These are all empty now, drop the files and just include pwm/pwm.h
instead.
BRANCH=none
BUG=none
TEST=zmake testall
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: Id055cc8fc7c1eae85cd55c583ad89cdfd910ea9b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3246010
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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PWM_CH_WITH_DSLEEP_FLAG does not seem to be used right now in the Zephyr
port. Dropping the define in the map file, if we need it in the future
we can use a device tree label directly.
BRANCH=none
BUG=none
TEST=zmake configure -b -B ~/build-it8xxx2_evb/ zephyr/projects/it8xxx2_evb
Change-Id: Idadad0656aa172292574857ad59cc863007de836
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3245509
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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This drops the PWM_CH_DISPLIGHT define from the individual board pwm_map,
and replaces with a single reference to a named pwm labeled displight.
BRANCH=none
BUG=none
TEST=zmake testall
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I17ca620097a4b0fd6907672e340415d1963740a7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3245507
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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This drops the PWM_CH_KBLIGHT define from the individual board pwm_map,
and replaces with a single reference to a named pwm labeled kblight.
BRANCH=none
BUG=b:177452529
TEST=zmake testall
TEST=build and run volteer
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: Ie474267b8f5d16cad7b8db2d202a5e971e417c1b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3245506
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Compiles the less detailed but more memory efficient
version of EC command `pd <port> srccaps`,
to save scarlet memory. Only applies to RO segment.
This is for a feature to make the EC power delivery
command more verbose: c/3248345.
BRANCH=None
BUG=b:194402616
TEST=Built all boards (make -j buildall)
Signed-off-by: Nehemiah Dureus <ndureus@google.com>
Cq-Depend: chromium:3248345
Change-Id: Idcca6b200268d2f1a1eab7d92c138b1d544d334b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252413
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Compiles the less detailed but more memory efficient
version of EC command `pd <port> srccaps`,
to save elm memory.
This is for a feature to make the EC power delivery
command more verbose: c/3248345.
BRANCH=None
BUG=b:194402616
TEST=Built all boards (make -j buildall)
Signed-off-by: Nehemiah Dureus <ndureus@google.com>
Cq-Depend: chromium:3248345
Change-Id: I1776c917759f3b7db006b856b209631131c4062c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252409
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Compiles the less detailed but more memory efficient
version of EC command `pd <port> srccaps`,
to save burnet memory.
This is for a feature to make the EC power delivery
command more verbose: c/3248345.
BRANCH=None
BUG=b:194402616
TEST=Built all boards (make -j buildall)
Signed-off-by: Nehemiah Dureus <ndureus@google.com>
Cq-Depend: chromium:3248345
Change-Id: I121b82cc936a2eaa2a6db31a366fabe974842bf2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3248344
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Compiles the less detailed but more memory efficient
version of EC command `pd <port> srccaps`,
to save kodama memory.
This is for a feature to make the EC power delivery
command more verbose: c/3248345.
BRANCH=None
BUG=b:194402616
TEST=Built all boards (make -j buildall)
Signed-off-by: Nehemiah Dureus <ndureus@google.com>
Cq-Depend: chromium:3248345
Change-Id: I1cb602f122bb7bc74f2d2c05f8bd0a7f0f8648bf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3248343
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Compiles the less detailed but more memory efficient
version of EC command `pd <port> srccaps`,
to save kukui memory. Only applies to RO segment.
This is for a feature to make the EC power delivery
command more verbose: c/3248345.
BRANCH=None
BUG=b:194402616
TEST=Built all boards (make -j buildall)
Signed-off-by: Nehemiah Dureus <ndureus@google.com>
Cq-Depend: chromium:3248345
Change-Id: I6b9229862dd7a1212e5864bda1a94068b740b400
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3248342
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Compiles the less detailed but more memory efficient
version of EC command `pd <port> srccaps`,
to save servo_v4 memory.
This is for a feature to make the EC power delivery
command more verbose: c/3248345.
BRANCH=None
BUG=b:194402616
TEST=Built all boards (make -j buildall)
Signed-off-by: Nehemiah Dureus <ndureus@google.com>
Cq-Depend: chromium:3248345
Change-Id: If3ddb94513d08e829a4bdfa16f49ded40d084afe
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3248341
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Added more detailed output for `pd <port> srccaps` for
debugging convenience.
For boards that have large enough memory, the output of srccaps
will be formatted showing pdo flags, pdo type, etc.:
Src 0: (Fixed) 5000mV/3000mA DRP UP USB DRD
Src 1: (Aug3.0) 5000mV-2000mV/3000mA DRP UP USB DRD
...
For boards that don't have enough memory to support this,
defining CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE will default
to displaying the old way of printing out srccaps, shown below:
0: 5000mV/3000mA
1: 5000mV-2000mV/3000mA
...
BRANCH=None
BUG=b:194402616
TEST=On Delbin, connected with ServoV4, execute `pd <port> srccaps`,
Built all boards (make -j buildall)
Signed-off-by: Nehemiah Dureus <ndureus@google.com>
Cq-Depend: chromium:3248341, chromium:3248342, chromium:3248343, chromium:3248344, chromium:3252409, chromium:3252413
Change-Id: I146f619c5baaf28b56a603c3b0a96fc9efbfb26a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3248345
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Make missing braces an error in chroot, like it is in the gitlab build.
crrev/c/3219472 broke the gitlab build, but wasn't caught in CQ.
BRANCH=None
BUG=b:184856083
TEST=zmake configure -b zephyr/test/drivers/
Cq-Depend: chromium:3253430
Change-Id: Ie20e82bc7211bc971f838fff6258c81e8a97bdd3
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3253429
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
Tested-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Aaron Massey <aaronmassey@google.com>
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Missing braces causes gitlab and now soon zmake to fail.
Properly initialize the .time_to_mock field in the
test_ln9310_cfly_precharge_timesout with curly braces.
BRANCH=none
BUG=b:184856083
TEST=zmake configure --test zephyr/test/drivers with new clang flags
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Change-Id: Icc773f71901d5f99779382f62aae324782f4dfac
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3253430
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
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This updates the TCPC1 and PPC1 (ps8815 daughterboard) I2C buses to
operate at 1 MHz instead of 400 kHz. Boards before board ID 2 were not
tuned for 1 MHz operation, so they will continue to operate at 400 kHz.
BRANCH=none
BUG=b:186189039,b:187764571,b:187764202
TEST=updated TCPC1 firmware using window scheme and FIFO scheme.
TEST=verified I2C bus 4, 7 speed is 1000 on board ID 2 and at 400 when
BOARD_ID_FAST_PLUS_CAPABLE is set to 9.
Change-Id: I182cb6bc0d1be24d512ef14d16e2cb4347b7eb02
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181512
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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This reverts commit 3f50a1e35e093d3989dc27f340b4ce5fb7fca5ee.
Reason for revert: The kukui-arc-r-postsubmit builder started failing after this change landed:
https://buganizer.corp.google.com/issues/204520684
https://ci.chromium.org/p/chromeos/builders/postsubmit/kukui-arc-r-postsubmit
The error is that the kodama board wasn't found.
chromeos-ec-0.0.2-r11157: Makefile:25: *** unable to locate BOARD kodama. Stop.
chromeos-ec-0.0.2-r11157: * ERROR: chromeos-base/chromeos-ec-0.0.2-r11157::chromiumos failed (compile phase):
Original change's description:
> kodama: drop kodama board
>
> Kodama is the tightest space board in kukui family, and we
> have to constanly disable configs to free up space.
> Since we don't really need the board in main branch as the
> firmware branch has been created for a long time, just drop
> this board on main branch.
>
> BUG=none
> TEST=makd buildall
> BRANCH=main
>
> Change-Id: I7f958ad7b97c191a8433d82987f8876add8c5dc3
> Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252605
> Tested-by: Eric Yilun Lin <yllin@google.com>
> Auto-Submit: Eric Yilun Lin <yllin@google.com>
> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Bug: none
Change-Id: I4d9b29a1c80b753a48763ee7cae42d3f6f25dccc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3250679
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Commit-Queue: Alexander Hartl <alexanderhartl@google.com>
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The power consumption criteria of SCP in S3 stage cannot be meet by
low speed ULPOSC clock. Change it to 26M which will be closed by SPM, so
that SCP core will stop running at S3 stage and meet the criteria.
BRANCH=None
BUG=b:199444513
TEST=scp console stops response in S3, and resume when leave S3.
Change-Id: If2adbf85c0096e98a6ad5d8ff9772aad04192bca
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3247735
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Since cherry SCP has to reduce power consumption in S3 state, cherry SCP
is going to stop running under S3 state. However, SCP WDT is default
using 32k clock and cannot change it by design. SCP has to support
disable/enable WDT to meet the S3 plan.
BRANCH=None
BUG=b:199444513
TEST=test enable/disable WDT ok
Change-Id: I6c1de9718ec558a5cd8495adc0c7b3f59d2846d7
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3247734
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Reason for revert:
SCP still encounters WDT timeout after doing more
test. This patch doesn't solve the issue.
Original change's description:
> chip/mt_scp: disable uart irq in S3 state
>
> According to the latched PC/LR in a S3 watchdog timeout case,
> SCP is handling UART IRQ when watchdog timeout.
> Before find out the reason of triggering UART IRQ, disable UART IRQ in
> S3 state to prevent handling it. UART IRQ is enabled when resumed.
>
> BRANCH=None
> BUG=b:199444513
> TEST=SR test >4000 times on 5 devices.
>
> Change-Id: I06a4c31ecb9a82978bee8deb04315a11778253f0
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> Reviewed-on:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3235729
> Tested-by: TingHan Shen
<tinghan.shen@mediatek.corp-partner.google.com>
> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
BRANCH=None
BUG=b:199444513
TEST=make BOARD=cherry pass
Change-Id: Iffeb88dc21567dff82604d156d575a28df262d02
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3247733
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Save the panic information on DRAM to keep it available at next reboot.
This requires a new non-cacheable DRAM MPU with RW permission.
Besides panic information, also checks the WDT latch registers that will
latch PC/SP/LR when triggered SCP WDT timeout.
BRANCH=None
BUG=b:199444513
BUG=b:189356151
TEST=see exception log at /var/log/cros_scp.log on tomato board
Change-Id: Ief9db8ec8b5b83805c21370d6be8ff49a8bb98df
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3250076
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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The panic information currently dumps by debug_print API which
implemented on SCP UART. This implies that the panic information
can only be observed on SCP UART. We cannot have any information
about crashed SCP on non-development environment.
Add a new panic API to dump information on console channel, so that
panic information can be transmitted to kernel side via host command.
BRANCH=None
BUG=b:199444513
BUG=b:189356151
TEST=build pass
Change-Id: I2167d16a709fa2814f3b0a208411ae5e7f51f70b
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3225807
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Enlage vdec/venc/dmp stack size in case of open debug log fail.
BRANCH=none
BUG=b:184793035
TEST=make BOARD=cherry_scp
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Change-Id: I0ca61a7b00dc535f69fb6f37d9798795ac1636e6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2928123
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
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Move some functions which is likely to be use by zephyr ec outside of
board/baseboard.c.
BUG=b:202808130
TEST=1) make BOARD=krabby
2) zmake -D -l DEBUG configure -b zephyr/projects/corsola/krabby/
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I6ac4519bd9070cb8c54bce812dd62eaf8af21dfb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3246994
Auto-Submit: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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it83xx_pd.h uses uint8_t, add the appropriate header for type
declaration.
BUG=none
TEST=make
BRANCH=main
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Iad30f525297835c6041d8bc95bb2b751c10a09ed
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3249323
Auto-Submit: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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Initialize the vivaldi keyboard.
BUG=b:200692807
BRANCH=main
TEST=manual
1. Scan all key.
2. Check action key function.
3. Check ALT + Volup + H.
4. Check ALT + Volup + R.
5. Check Refresh (F2) + powerbutton (EC reboot).
6. Check ESC + Refresh + powerbutton.
Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com>
Change-Id: I8b373bce021de2ef0f4a3b2d146f28d6b6be846f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3244681
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Commit-Queue: Boris Mittelberg <bmbm@google.com>
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Kodama is the tightest space board in kukui family, and we
have to constanly disable configs to free up space.
Since we don't really need the board in main branch as the
firmware branch has been created for a long time, just drop
this board on main branch.
BUG=none
TEST=makd buildall
BRANCH=main
Change-Id: I7f958ad7b97c191a8433d82987f8876add8c5dc3
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252605
Tested-by: Eric Yilun Lin <yllin@google.com>
Auto-Submit: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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This adds a de-assertion ratio for the total power consumption to
compare when adapter wattage greater or equal to 60W and the battery
is not present(or the battery energy is less than 10%).
BUG=b:198689488 b:198722634
BRANCH=none
TEST=make -j BOARD=gimble
Signed-off-by: Will Tsai <will_tsai@wistron.corp-partner.google.com>
Change-Id: Ie7d6ffa8f30a1f0b0aec24055e8d823d1d3395b0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3251823
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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Since each variant may have different prochot assertion/de-assertion
configuration, the prochot assertion/de-assertion ratio setting will
be moved from baseboard to variant.
BUG=b:198689488 b:198722634
BRANCH=none
TEST=make -j BOARD=gimble
Signed-off-by: Will Tsai <will_tsai@wistron.corp-partner.google.com>
Change-Id: I140e74e85fbec24e0e1759526d9c3b24152b68c6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3247740
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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TASK_PROFILING takes 800 bytes.
BUG=none
TEST=make BOARD=kodama
BRANCH=main
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Ib2ba0f10463d5d598fb577aca99878a412c2a0cb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3250333
Tested-by: Ting Shen <phoenixshen@chromium.org>
Auto-Submit: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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This adjusts the task stack sizes on brya and variants. Many task stacks
had to be increased, only CONSOLE could be reduced.
Task stack size constants are added at the baseboard level for several
tasks that tend to behave very similarly among variants.
before:
Task: CHARGER, Max size: 932, Allocated size: 928
Task: CHG_RAMP, Max size: 900, Allocated size: 672
Task: CHIPSET, Max size: 988, Allocated size: 928
Task: CONSOLE, Max size: 612, Allocated size: 928
Task: HOOKS, Max size: 580, Allocated size: 800
Task: HOSTCMD, Max size: 612, Allocated size: 800
Task: KEYPROTO, Max size: 660, Allocated size: 672
Task: KEYSCAN, Max size: 708, Allocated size: 672
Task: MOTIONSENSE, Max size: 796, Allocated size: 928
Task: PD_C0, Max size: 1052, Allocated size: 1056
Task: PD_C1, Max size: 1052, Allocated size: 1056
Task: PD_C2, Max size: 1052, Allocated size: 1056
Task: PD_INT_C0, Max size: 644, Allocated size: 672
Task: PD_INT_C1, Max size: 644, Allocated size: 672
Task: POWERBTN, Max size: 964, Allocated size: 800
Task: USB_CHG_P0, Max size: 508, Allocated size: 672
Task: USB_CHG_P1, Max size: 508, Allocated size: 672
Task: USB_CHG_P2, Max size: 508, Allocated size: 672
after:
Task: CHARGER, Max size: 932, Allocated size: 1088
Task: CHG_RAMP, Max size: 900, Allocated size: 1088
Task: CHIPSET, Max size: 988, Allocated size: 1152
Task: CONSOLE, Max size: 612, Allocated size: 800
Task: HOOKS, Max size: 580, Allocated size: 800
Task: HOSTCMD, Max size: 612, Allocated size: 800
Task: KEYPROTO, Max size: 660, Allocated size: 800
Task: KEYSCAN, Max size: 708, Allocated size: 928
Task: MOTIONSENSE, Max size: 796, Allocated size: 928
Task: PD_C0, Max size: 1052, Allocated size: 1216
Task: PD_C1, Max size: 1052, Allocated size: 1216
Task: PD_C2, Max size: 1052, Allocated size: 1216
Task: PD_INT_C0, Max size: 644, Allocated size: 800
Task: PD_INT_C1, Max size: 644, Allocated size: 800
Task: POWERBTN, Max size: 964, Allocated size: 1088
Task: USB_CHG_P0, Max size: 508, Allocated size: 672
Task: USB_CHG_P1, Max size: 508, Allocated size: 672
Task: USB_CHG_P2, Max size: 508, Allocated size: 672
BRANCH=none
BUG=b:204362187,b:204102039,b:204280744
TEST=brya EC no longer reboots due to stack overflow in PD task
TEST=task command now reports 200 bytes of stack headroom for chipset
TEST=boots on brya
Change-Id: I081228da6d850bf69b431475b81025045c1c521d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3248976
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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When linking with clang (lld), it complains that it can't find the
"_start" symbol:
ld.lld: warning: cannot find entry symbol _start; defaulting to
0x8000000
"_start" is used by the linker to fill in the entry point address in the
ELF header ("e_entry":
https://refspecs.linuxbase.org/elf/elf.pdf#page=19):
arm-none-eabi-readelf -e ./build/servo_micro/ec.obj
ELF Header:
...
Entry point address: 0x8000000
...
Add an explicit "_start" symbol at the beginning of the firmware image
(entry point) to satisfy the linker.
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Id077013cb54869b92d18cea2f74be25135bc4e42
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3249156
Reviewed-by: Keith Short <keithshort@chromium.org>
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ADC6 (GPIO34) is connected to temp sensor.
Enable ADC6 to read temperature.
BUG=none
BRANCH=trogdor
TEST=EC console "temps" can read temperature.
Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com>
Change-Id: I9600ea0442a5643ca65a9a484117f2ed47cdc17d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3246876
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Commit-Queue: Bob Moragues <moragues@chromium.org>
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Changes enable drivers to support BQ25720 charger chip for ADL-N.
ADLRVP variants uses ISL9241 drivers too. Hence both the driver
files needs to be compiled. At boot time, depending on the board id
read, right drivers are executed for the platform.
BRANCH=none
TEST=Battery charging verified on ADL-N board.
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
Change-Id: I952a3b7d23f52ec512f90a843db1f4db2fe0e95d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3204652
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
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Test that the LN9310 driver appropriately handles a failure to read
the system status register when handling interrupts.
BRANCH=none
BUG=b:184856083
TEST=zmake configure --test zephyr/test/drivers
Signed-off-by: Aaron Massey <aaronmassey@chromium.org>
Change-Id: Ib30674eee7d465707f71f6acb701f156c821fafc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3221778
Commit-Queue: Aaron Massey <aaronmassey@google.com>
Tested-by: Aaron Massey <aaronmassey@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Test ln9310 driver appropriately handles failures to read the INT1
interrupt register.
BRANCH=none
BUG=b:184856083
TEST=zmake configure --test zephyr/test/drivers
Signed-off-by: Aaron Massey <aaronmassey@chromium.org>
Change-Id: I2049fbd40050322391b372d96cd35da648e82899
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3221777
Commit-Queue: Aaron Massey <aaronmassey@google.com>
Tested-by: Aaron Massey <aaronmassey@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
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Test that during the cfly precharge startup workaround
required for older chip revisions of the ln9310, setting the
standby_en pin to 0 timeout is handled appropriately.
BRANCH=none
BUG=b:184856083
TEST=zmake configure --test zephyr/test/drivers
Signed-off-by: Aaron Massey <aaronmassey@chromium.org>
Change-Id: I86f130311668e8676fbc55f50d2853c73b43b3f4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219472
Commit-Queue: Aaron Massey <aaronmassey@google.com>
Tested-by: Aaron Massey <aaronmassey@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
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Some driver code paths require control of the return value of
get_time in order to be properly tested.
Now get_time can be mocked during tests.
BRANCH=none
BUG=b:184856083
TEST=zmake testall and make runhosttests
Signed-off-by: Aaron Massey <aaronmassey@chromium.org>
Change-Id: I7f66542aaef015263af66d872978c40746a77292
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219471
Commit-Queue: Aaron Massey <aaronmassey@google.com>
Tested-by: Aaron Massey <aaronmassey@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
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