summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* Typec: Add disconnected status eventDiana Z2021-07-011-0/+1
| | | | | | | | | | | | | | Add an event bit to represent that the port has been disconnected. BRANCH=None BUG=b:188330043 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ia0975cae66d81a3ef066e62632d8cd0b453b9a3a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2983991 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Prashant Malani <pmalani@chromium.org>
* zephyr: npcx: Remove PLL setting for NPCX chipWealian Liao2021-07-012-20/+2
| | | | | | | | | | | | | | | | | | | UPSTREAM PR(https://github.com/zephyrproject-rtos/zephyr/pull/36217) moves clock setting from Kconfig to devicetree. This CL removes the Kconfig setting for clock configuration. BUG=none BRANCH=none TEST=zmake testall TEST=Check timer by 'timerinfo' on volteer with zephyr v2.5 & v2.6 Cq-Depend: chromium:2994365, chromium:2994237 Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I8fd60a715a6b81ad0afe56f46c752ae42a619ea5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994230 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Fabio Baltieri <fabiobaltieri@google.com>
* zephyr: shim: compile out pm_policy_low_power_devices for v2.6Fabio Baltieri2021-07-011-18/+2
| | | | | | | | | | | | | | | The function call has been removed in v2.6, changing the version condition to exclude it entirely so it's clear that it can be dropped once we drop support for v2.5. BRANCH=none BUG=b:186651036 TEST=build tested Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Change-Id: Icbf4d06e6d7e8f4910dde66b89dceadc4b6f39ba Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3000246 Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr/drivers: npcx: reorganizes the flash driver(3)Tim Lin2021-07-015-59/+195
| | | | | | | | | | | | | | | | | | | | | Move NPCX specific code crec_flash_physical_get_protect(), crec_flash_physical_get_protect_flags(), crec_flash_physical_protect_at_boot(), and crec_flash_physical_protect_now() from shim/flash.c to cros_flash/cros_flash_npcx.c. BUG=b:187192628 BRANCH=none TEST=zmake -lDEBUG configure -b -B zephyr/build_volteer \ zephyr/projects/volteer/volteer/ Cq-Depend: chromium:2994430 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: Id6ed382ad4578969838339c9eb874b323390c485 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2891674 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* zephyr/drivers: npcx: reorganizes the flash driver(2)Tim Lin2021-07-012-172/+186
| | | | | | | | | | | | | | | | | | Move NPCX specific code flash_dev_init(), crec_flash_physical_write() and crec_flash_physical_erase() from shim/flash.c to cros_flash/cros_flash_npcx.c. BUG=b:187192628 BRANCH=none TEST=none Cq-Depend: chromium:2994429 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: I094e26c5b670402872a665ba4d24a6594f7ca77e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994430 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr/drivers: npcx: reorganizes the flash driver(1)Tim Lin2021-07-013-335/+186
| | | | | | | | | | | | | | | | | | | Move the flash protection routines flash_get_status1() through flash_write_prot_reg() from shim/flash.c to cros_flash/cros_flash_npcx.c. BUG=b:187192628 BRANCH=none TEST=none Cq-Depend: chromium:2891674 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: Iaca3a32cfb35a77df10b87745bdabc1ed1cd3c40 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994429 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* stm32: add stm32l431 ec in chip/stm32 : flashBossen WU2021-07-012-7/+44
| | | | | | | | | | | | | | | stm32l431 related driver: flash-stm32g4-l4.c system.c The stm32l476g-eval is the only board which would be possibly impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I273954c75651b20de58db53eba7e7d0e4553763d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2978652 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : adcBossen WU2021-07-012-1/+258
| | | | | | | | | | | | | | stm32l431 related driver: adc-stm32l4.c adc_chip.h The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I0ce73ee9ab02e1cfd20a178628d935d24a1907ce Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975521 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* cherry: add tomato boardTing Shen2021-07-011-0/+1
| | | | | | | | | | | | | | BUG=none TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Id064491071a013c4edebbfc022c7287d1205e643 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999410 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* cherry: disable unused pwm pinsTing Shen2021-07-011-1/+6
| | | | | | | | | | | | | | | | Set unused pwm pins (PWM 3,6,7) to input BUG=b:192320391 TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I0e6983fe45a0ac35bfed2e7da7a9213cccfe9b58 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2991988 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* redrix: Remove board ID 1 supportDevin Lu2021-07-013-108/+6
| | | | | | | | | | | | | Redrix is now p2 schematic. Remove unused board ID configuration. BUG=none BRANCH=none TEST=make BOARD=redrix Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: Iea2d824641ae35c135b45742fe1e34dd99931f42 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2995899 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* redrix: Remove tune mp2964 settingsDevin Lu2021-07-013-52/+3
| | | | | | | | | | | BUG=none BRANCH=none TEST=make BOARD=redrix Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I10488f2e3228512359a0784459063c74fcbff82c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2995238 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* redrix: Merge generated-gpio.incDevin Lu2021-07-012-136/+119
| | | | | | | | | | | | | | Redrix does not auto-generate their GPIO definitions. Merge generated-gpio.inc to gpio.inc to customize in future. BUG=none BRANCH=none TEST=make BOARD=redrix Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: Icea3dd5237c0fca4bae96163cd2b2d20c74b34f3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2995232 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* redrix: Include-what-you-use scrubDevin Lu2021-07-0111-7/+33
| | | | | | | | | | | | | | | | | [Synchronize with CL:2987159 to Redrix] This updates the list of header files included by brya board files to match what is actually used. BUG=none BRANCH=none TEST=make BOARD=redrix Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I7f9cc8ef363279a763f540d9fecb0a1fe733a097 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2995237 Reviewed-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* stm32: add stm32l431 ec in chip/stm32 : dmaBossen WU2021-07-011-6/+29
| | | | | | | | | | | | | | stm32l431 related driver: dma The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: Ia513875963c2c65f6b63605fc113f139656a4028 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975520 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : i2cBossen WU2021-07-011-19/+25
| | | | | | | | | | | | | | | stm32l431 related driver: i2c-stm32l4 The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: If6187e6f3c2f82ab118524444c1849108bb82f82 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975519 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* mrbland: Initial EC imageSiyu Qin2021-07-019-0/+1589
| | | | | | | | | | | | | | | | | Create the initial EC image for the mrbland variant by copying the homestar reference board EC files into a new directory named for the variant. (Auto-Generated by create_initial_ec_image.sh version 1.5.0). BUG=b:192304588 BRANCH=trogdor TEST=make BOARD=mrbland Signed-off-by: Siyu Qin <qinsiyu@huaqin.corp-partner.google.com> Change-Id: Ibf5c02c3483e8768acfbfd889b038ef65071cb61 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993958 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* trogdor: Allow TCPC ports to I2C pass-throughWai-Hong Tam2021-07-011-1/+3
| | | | | | | | | | | | | | | | | Otherwise, the TCPC ports are blocked when the device is locked (WP-enabled). The TCPC firmware update fails and triggers the recovery mode. We have another protection to block the TCPC ports when AP issues the EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS host command, b/192503665. BRANCH=Trogdor BUG=b:192208082 TEST=Built the image and booted. Change-Id: Icd30ed3cfabd024674265a646cfe6256fce4025d Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999216 Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* battery: Set host's low battery shutdown SoC to 4%Daisuke Nojiri2021-07-011-4/+4
| | | | | | | | | | | | | | | Currently, the host's low battery shutdown SoC is 3% by default but most boards are configured to 4%. This patch changes the default value to 4% so that we require only minority boards to customize it. BUG=b:191837893, b:189737806 BRANCH=None TEST=Storo using battfake EC command. Change-Id: I69ed5d8cc8c0d1e321d79c5eae26a9c21624a4ea Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2998509 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Add MEC1727 MECC board: adlrvpp_mchp1727martin yan2021-06-307-1/+575
| | | | | | | | | | | | | | | | | | | | | | | | | Add new board, adlrvpp_mchp1727 using MEC1727-SZ with integrated 512KB SPI flash and based upon the intelrvp baseboard. BRANCH=none BUG=b:190638460 TEST=Build MEC1727SZ MECC and ADL-P board. Tested basic functions: 1: Power on sequence: G3->S5->S3->S0 2: ESPI enumeration / VW / FC 3: Temperature measurements 4: Smart battery information acquisition 5: Type C Port 0 and 1 - enter ALT mode 6: UART console 7: Sleep / wake / hibernate - woken by powerbtn 8: Powerbtn override Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Ib474e1134a47a6fa219d741fc5c094cf2f4a560c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2891908 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Correct assigning I2C controller to a portVijay Hiremath2021-06-302-3/+15
| | | | | | | | | | | | | | | | | | Corrected default assignment of controller to I2C port based on the number of I2C ports being used rather than the port in use. This avoids overlapping of I2C controller assignment when the I2C ports used are not greater than MCHP_I2C_CTRL_MAX. BUG=none BRANCH=none TEST=Tested on ADLRVP, default I2C controller assignment is correct. Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Change-Id: I875b0f7e94162f923325e9ed07e7549cc760fdf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2980432 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Move I2C_CONTROLLER_COUNT and I2C_PORT_COUNT to chipmartin yan2021-06-306-47/+8
| | | | | | | | | | | | | | | | | | Move I2C_CONTROLLER_COUNT and I2C_PORT_COUNT to registers-mec172x.h and registers-mec152x.h from board.h, both are chip specific BRANCH=none BUG=none TEST=Tested adlrvpp_mchp1727 and sklrvp_mchp1723 adlrvpp_mchp1521 and sklrvp_mchp Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Icd91e9877e0053c83c1a73d10470ffefedd90a01 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2982390 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* blipper: disable charger ADC function at Z-stateMike Lee2021-06-301-9/+21
| | | | | | | | | | | | | | | | | | In order to reduce the power consumption of Z-state, we need disable charger ADC function at Z-state, and we use HW solution to solve AC cannot wake up Z-state issue. BUG=b:186717219 BRANCH=dedede TEST=EE verify the power consumption ok,and AC can wakeup Z-state at rework duts Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: I674f0b73d0b593ea88973aa5b8b3447bd34b81ed Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994881 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: Fix duplicate ec consoleYuval Peress2021-06-301-10/+17
| | | | | | | | | | | | | | | | Logs in /var/log/cros_ec.log contained many duplicate entries. This was caused by not moving the actual head pointer when reading from the buffer. BRANCH=none BUG=b:180423400 TEST=Flash lazor and observe /var/log/cros_ec.log Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I7951d2fc3e6f13a5d6aebcf0b347238bcb790973 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2995713 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: Add pi3usb9201 emulator and testEdward Hill2021-06-3010-1/+572
| | | | | | | | | | | | BUG=b:184852906 BRANCH=none TEST=zmake configure --test zephyr/test/drivers Change-Id: Ie554b6957269c638357d82d6f5dcc2ceda08caab Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2961272 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* jelboz360: gyro sensor add 2nd source icm-40608Michael5 Chen12021-06-303-2/+74
| | | | | | | | | | | | | | | | | | | | gyro sensor add 2nd source icm-40608 BUG=b:191687030 BRANCH=zork TEST=make BOARD=shuboz 1. Set CBI SSFC 0x03 and using command "watch ectool motionsense lid_angle" for sensor icm-40608. 2. Using command "watch ectool motionsense lid_angle" for BMI160. Signed-off-by: Michael5 Chen1 <michael5_chen1@pegatron.corp-partner.google.com> Change-Id: I2d57245e82f36eef684f483fbb4edb0e7cd56c93 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993791 Reviewed-by: Jacky Wang <jacky5_wang@pegatron.corp-partner.google.com> Reviewed-by: Isaac Lee <isaaclee@google.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* zephyr: asurada: make USB-C config changesDenis Brockus2021-06-301-4/+13
| | | | | | | | | | | | | | | | | Include more battery and charger configs. Move the USB-A out of the USB-C configs. BUG=b:189855648 BRANCH=none TEST=see that battery is detected Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I2eedfbf71a596238623e737d14f572b9a2ba8259 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994751 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: asurada: add board_allow_i2c_passthruDenis Brockus2021-06-302-0/+20
| | | | | | | | | | | | | | BUG=b:189855648 BRANCH=none TEST=zmake configure -b $PROJ_HAYATO Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I9146fe2d7aee9d7320ea012c744efe4a275eb81b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994750 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: implement ro/rw packing for hayatoJack Rosenthal2021-06-303-12/+48
| | | | | | | | | | | | | | | | | | | | | | | The "npcx" packer in zmake was hard-coded for Nuvoton devices. Restructure into a new packer, BinmanPacker, which makes no Nuvoton assumptions, and subclass it for the NpcxPacker. Note: there's some file size check here which was coded for Nuvoton only. I think it's not actually necessary since binman already checks to see if the region overflowed, and will error if it did. The best thing to do here is to keep the existing behavior and evaluate if that Nuvoton-only size check can just be removed from zmake. BUG=b:192401039 BRANCH=none TEST=zmake testall TEST=inspected fmap of hayato image, note I don't have a device to test on right now Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ic45a030d0dd02451834161305f048487f7b273e4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2995602 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: drivers: add accele_bma2x2 test suiteTomasz Michalec2021-06-304-0/+934
| | | | | | | | | | | | | | BMA2x2 driver is tested using BMA255 emulator. All functions exposed in accelgyro_drv are tested. BUG=b:184855546 BRANCH=none TEST=run zmake drivers test Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: I20a2849b7b11b2a2c152bd07d748cb073cfd86b0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2933303 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* driver: Add argument check in BMA2x2 driverTomasz Michalec2021-06-302-4/+20
| | | | | | | | | | | | | | set_range and set_data_rate functions of BMA2x2 driver should check input values to not set values outside of range supported by device. BUG=none BRANCH=none TEST=makeall Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: Ie9650975e00a99e86a5229ee200dab24be536076 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953222 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* motion: check console task when availableTomasz Michalec2021-06-301-0/+4
| | | | | | | | | | | | | | | | motion_sense_init() checks if it was called in hooks task or console task context. In Zephyr console task is not available so TASK_ID_CONSOLE is not defined. Because of that HAS_TASK_CONSOLE is used to choose if check for hooks and console task or only for hooks task. BUG=none TEST=makeall BRANCH=none Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: Ie51b043209d5228c074bbc9a693bf7b98cf2a598 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2933302 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: tasks: fix task id for deferred callsTomasz Michalec2021-06-302-0/+9
| | | | | | | | | | | | | | | In Zephyr deferred calls are run in k_sys_work_queue context instead of thread running hook_task(). Because of that shimmed task_get_current() is modfied to return TASK_ID_HOOKS if run from k_sys_work_queue context. BUG=b:190727776 TEST=make hosttest BRANCH=none Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: I9e15627df8dce6b0829ad872150cbe2318330f28 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953225 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Add BMA255 emulatorTomasz Michalec2021-06-306-0/+1618
| | | | | | | | | | | | | | | | | Add BMA255 emulator which is emulated device on i2c bus. Emulated accelerometer properties are defined through device tree, but they can be changed in runtime through BMA255 emulator API. It allows to set custom handlers for write and read messages to emulate more complex scenarios or malfunctioning device. BUG=b:184855546 BRANCH=none TEST=none Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: I4def7fcc54edbf9cb346fda0f21f647a5ad5f8d5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2933301 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* stm32: add stm32l431 ec in chip/stm32 : uartBossen WU2021-06-301-4/+28
| | | | | | | | | | | | | | | stm32l431 related driver: uart The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I861d1cf38430d6b1b5d7c09bd565d727961a4128 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975168 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : watchdogBossen WU2021-06-301-1/+30
| | | | | | | | | | | | | | stm32l431 related driver: watchdog. The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I8488a3bfad31dadedc65078d29c117cfb2308f77 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975160 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : system / clock / timerBossen WU2021-06-307-498/+2575
| | | | | | | | | | | | | | stm32l431 related driver: system / clock / timer. The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: Idf335005d8188f6959835aa40179a6bd771c5114 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905165 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* Lazor: support factory keyboard test.Sue Chen2021-06-302-0/+23
| | | | | | | | | | | | | | | | | | | | connector-to-GPIO map: {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, BUG=b:191897023 BRANCH=trogdor TEST=`ectool kbfactorytest` PASS. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: If03b232cd0dae293005b199ed90faa4701345818 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2929063 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* Ezkinil: support factory keyboard test.Sue Chen2021-06-302-0/+22
| | | | | | | | | | | | | | | | | | | | connector-to-GPIO map: {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},{2, 2}, {3, 0}, {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, {-1, -1}, BUG=b:191931746 BRANCH=zork TEST=`ectool kbfactorytest` PASS. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I0354835b8b606fe735b1cef433e6e07bba658249 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2929062 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
* sasukette: disable charger ADC function at Z-stateMike Lee2021-06-301-1/+13
| | | | | | | | | | | | | | | | | In order to reduce the power consumption of Z-state, we need disable charger ADC function at Z-state, and we use HW solution to solve AC cannot wake up Z-state issue. BUG=b:186335659 BRANCH=dedede TEST=EE verify the power consumption ok,and AC can wakeup Z-state at rework duts Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: I50d30ee88407cbd255816247b16440ea50bf4a2d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994653 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: npcx: Fix NPCX_PWDWN_CTL redefine warningWealian Liao2021-06-301-19/+3
| | | | | | | | | | | | | | | UPSTREAM has NPCX_PWDWN_CTL definition. This CL transfers to use UPSTREAM NPCX_PWDWN_CTL macro to fix the redefine warning. BRANCH=none BUG=none TEST=build byra without warning TEST='sysjump RW' is correct Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Ib92f2263f3e10cae5d8b0ebd4f3b274c8c7359a0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994229 Reviewed-by: Yuval Peress <peress@chromium.org>
* Battery: Apply fake SoC to display chargeDaisuke Nojiri2021-06-292-6/+7
| | | | | | | | | | | | | | | | This patch makes the battfake command apply the fake SoC to the display SoC as well as the raw battery SoC. This patch also cleans up battery_compensate_params. BUG=None BRANCH=None TEST=Atlas Change-Id: Ifbdaa81204d27501df8a4f5e025c19a79d62feff Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994748 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* battery: Set host's low battery shutdown SoC to 3%Daisuke Nojiri2021-06-292-5/+8
| | | | | | | | | | | | | | | | | | | | | | | Currently, the host's low battery shutdown SoC is 2%. This is the same as EC's low battery shutdown threshold. The EC waits for 30 secs before it triggers the low battery shutdown and powerd reads the SoC every 30 secs. Thus, in most cases powerd can shut down the system gracefully but these delays can be configured differently and the system may be too busy to process all shutdown tasks within 30 secs. This patch increases the host's shutdown SoC to 3%. This will further guarantee that powerd will be given enough time to do everything for a proper shutdown. It also avoids deeply discharging the battery, which is bad for the battery health. BUG=b:191837893 BRANCH=None TEST=Altas using battfake EC command. Change-Id: I3ab23205b400a1a326a60b8f9501611c027183b2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994747 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_mux: Remove disconnect latch flagAyushee Shah2021-06-292-70/+1
| | | | | | | | | | | | | | With dark resume enabled, disconnect latch flag is obsolete BUG=None BRANCH=None TEST=Swapping Type C devices in s0ix works Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: Ica1b55f820f5b3fff5b7dabf88ca57ac0993f246 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2846417 Reviewed-by: Madhusudanarao Amara <madhusudanarao.amara@intel.corp-partner.google.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* storo: change icm-42607 sensor configMike Lee2021-06-291-14/+17
| | | | | | | | | | | | | | | change icm-42607 sensor location from lid to base BUG=b:192334282 BRANCH=dedede TEST=make BOARD=storo pass, and use 'ectool motionsense info 1' can show correct location. Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: Ie733f6b08fb28599bd31a81cd071437862350324 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994744 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* brya: Remove USB_C1_RT_INT_ODL as interrupt sourceCaveh Jalali2021-06-291-1/+1
| | | | | | | | | | | | | | | This disables interrupts on USB_C1_RT_INT_ODL. We do not use this pin with the current selection of USB DBs. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: I423d5c1c3ef6e86f393fc9ce35230f1c6ab62607 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987914 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Config USB_C0_C2_TCPC_RST_ODL as ODRCaveh Jalali2021-06-291-2/+2
| | | | | | | | | | | | | | | This configures USB_C0_C2_TCPC_RST_ODL as ODR_LOW instead of driven low since this signal has a board level pull-up. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: Ib199a88349242489481896cfbe8fcbdb303810b9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977474 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Enable PCH_WAKE GPIO for board ID 2Caveh Jalali2021-06-291-1/+1
| | | | | | | | | | | | | | | We originally intended to eliminate PCH_WAKE on board ID 2, but we will use it after all. So, configure it to ODR_HIGH. BRANCH=none BUG=b:188735747 TEST=boots on board ID 1 Change-Id: Ia0fbd373fd5f9cdc37a6eaa59abf09362d4184e7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993548 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* Guybrush: Set up custom Vbus source detectionDiana Z2021-06-292-0/+8
| | | | | | | | | | | | | | | | | | In the USB common code, PPCs will always be given priority over TCPCs for detecting whether sourcing is enabled. However, with FRS enabled the PPC cached flags no longer accurately reflect whether we're sourcing. Therefore, set up a custom board function which may query the most appropriate chip, though for now set it up for the same component used by the Vbus discharge code. BRANCH=None BUG=b:183586640 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I4acf65930e944990e7770252de4ff47c671382a6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987596 Reviewed-by: Rob Barnes <robbarnes@google.com>
* zephyr: dts: npcx: move SHI node to npcx.dtsiJun Lin2021-06-292-10/+10
| | | | | | | | | | | | | | | | | | SHI is supported in all npcx family chips. Its dts node should be declared in the common location (i.e. npcx.dtsi.) BRANCH=none BUG=b:192295048 TEST=build lazor TEST=with CL:2993220, build herobrine_npcx7 and herobrine_npcx9 with CONFIG_CROS_SHI_NPCX enabled Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I6b6d9ba9a666d86a0993fa59c3cb7ff8249b7595 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993926 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
View Lorry Controller Status