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* zephyr: lazor: enable Virtual Battery driverDawid Niedzwiecki2021-05-312-0/+3
| | | | | | | | | | | | | | | | Enable I2C_VIRTUAL_BATTERY config for lazor. This is one of a few steps to fix getting data about the battery by the host. Also, set I2C_PORT_VIRTUAL_BATTERY to I2C_PORT_BATTERY, but it might be changed in the future. BUG=b:188885798 BRANCH=none TEST=zmake testall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I12da1b57b6e2cf0b98822c71243ccd1667d73506 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919907 Reviewed-by: Yuval Peress <peress@chromium.org>
* brya: Limit IMVP9 tuning to board ID 1Caveh Jalali2021-05-271-0/+3
| | | | | | | | | | | | | | | | We introduced tuning values for the IMVP9 PMIC for board ID 1 to improve stability. More recent boards should have the desired values pre-programmed, so we do not need to apply tuning parameters. BRANCH=none BUG=b:188945301,b:185275955 TEST=boots on board ID 1 Change-Id: I9b6967a43f6d5c8b37bc3a7344347c278bdf698a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922002 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* util: Make a start on writing a Python-based CONFIG checkerSimon Glass2021-05-272-0/+363
| | | | | | | | | | | | | | | | | | Add a new class which can handle the operations required to check that new ad-hoc CONFIGs are not added to the source tree. More work is needed in future CLs: - building the list of allowed CONFIGs - plumbing it into the build and removing the existing shell scripts BUG=b:181323955 BRANCH=none TEST=python3 util/test_kconfig_check.py Change-Id: Icec295effc4bf3c7b644f671b0cb83dcb0c97b68 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2864428 Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: add I2C_VIRTUAL_BATTERY configDawid Niedzwiecki2021-05-273-1/+16
| | | | | | | | | | | | | | Add I2C_VIRTUAL_BATTERY config to use virtual battery driver. BUG=b:188885798 BRANCH=none TEST=zmake testall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I6d1a4bfd8c950aa569ee836d9d22e438eeaef67b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919906 Reviewed-by: Yuval Peress <peress@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org>
* zephyr: asurada: move options to be board level choicesDenis Brockus2021-05-272-53/+54
| | | | | | | | | | | | | | | | | | Until there is a variant that needs to have a CONFIG_ option as a different value, they should stay in the top level board configuration. BUG=b:180980668 BRANCH=none TEST=zmake configure -b $PROJ_ASURADA Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I78890978489be5a90656d283c6489a92060305c1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2920626 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org>
* chip/npcx: Fix comment white spaceCaveh Jalali2021-05-271-1/+1
| | | | | | | | | | | | | | This fixes a missing white space in a comment. BUG=none BRANCH=none TEST=buildall passes Change-Id: Ifde65ab45be7fa6881195ecf723d999d9991f2aa Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921289 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* Test: Make host calls for power supply mockableDiana Z2021-05-271-2/+2
| | | | | | | | | | | | | | Add test_mockable for power supply ready and reset so tests may detect when Vbus is applied and removed. BRANCH=None BUG=b:153071799 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I43d8d3cc5107b4e94338850fa807ae0eedc6d4b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921282 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* TCPMv2: Exit Attached.SRC on open even during swapDiana Z2021-05-271-2/+1
| | | | | | | | | | | | | | | | | | | | | | If a port doesn't clear the PR swap in progress flag while switching from a source to a sink, the port can end up permanently stuck in Attached.SRC even when the port partner is unplugged. This removes the check to the PR swap in progress flag when Open is detected on the CC lines. This follows the type-c spec's exit conditions, and we would not expect to see CC open during a PR swap since the source sets Rd before the new source will set Rp. BRANCH=None BUG=b:158613480 TEST=on mancomb, unplugging after failed PR swap with dock allows port to go unattached again. Normal PR swap process is able to complete with dock plus servo_v4 and Apple 3-in-1 Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Idc4c193597c6b4a791d18e38bc5111d0342e512c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2256465 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* brya: Set hibernate wake sources polarityCaveh Jalali2021-05-271-5/+6
| | | | | | | | | | | | | | | | | This sets the wake source polarity on GPIOs we use as wake sources. LID_OPEN and ACOK are active high while the GSC_EC_PWR_BTN_ODL is active low. BRANCH=none BUG=b:183452273 TEST=booted on brya board ID 1 Change-Id: I13fded03bbe3f40ed9699f6e8c32e7532c87bc41 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921292 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* TCPCI: Move debug accessory control set to NCT38xx driverDiana Z2021-05-272-12/+13
| | | | | | | | | | | | | | | | | | | This debug accessory control setting was initially added to the TCPCI driver to support the NCT3807, but now should move into the NCT driver since it will need to be conditional on specific register conditions. Note that NCT is the only driver currently implementing the debug_accessory driver field, so it's not expected to affect other TCPCs. BRANCH=None BUG=b:186799392 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Id5832c474378a3f8735c6c72c5535ddb5d9229d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919940 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: drivers: add temp_sensor test suiteTomasz Michalec2021-05-272-0/+134
| | | | | | | | | | | | | | | | | | Temperature sensors are accessed through temp_sensor_read() for which this test suite is created. Tested functionalities are: - Error code from underlying driver is returned. - Unknown temperature sensor id is rejected. - Temperature from underlying driver is returned. Value is not extensively tested, because it is done in thermistor test suite. BUG=b:184857072 BRANCH=none TEST=run zmake drivers test Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: I6c2df39a70e8ac57325aa9e1f49e7a9bd2340fae Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2886889 Reviewed-by: Simon Glass <sjg@chromium.org>
* base_state: implement basestate host commandTing Shen2021-05-2711-27/+89
| | | | | | | | | | | | | | | | | | | | | This CL introduces an unified method to force base attach/detach, to deprecate the hard-coded gpio pin name table in hammerd/hammertests/common.py. Also modifies base_force_state to use the same parameter type as host command. BUG=b:188625010 TEST=manually, run `ectool basestate attach|detach|reset` on coachz BRANCH=trogdor,kukui Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I5235661727cbbd15015c49d588ec70605e4a33e8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2910472 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* stm32g4: ucpd: Clear tx interrupts before enableScott Collyer2021-05-271-26/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ucpd driver enables, then disables tx interrupts before and after each message is sent. This CL fixes an issue where tx interrupts weren't guaranteed to be cleared prior to enabling. This was leading to instances where the tx data byte interrupt wasn't firing when expected. The failure was exposed following a VCONN swap when VCONN is turned on. The UCPD driver will remove Rp from the CC line which has VCONN. The following PS_Rdy message would fail. Debugging this issue also led to observe that when Rp is removed for VCONN active CC lines, Rp would be applied again when Rp is adjusted by TCPM as part of collision avoidance. BUG=b:189293176 BRANCH=quiche TEST=Tested on quiche against kohaku host machine. Repro case was very consistent. Verified that failures were present without the fix in this CL. Then verified that after fixing interrupt issue, there were no hard reset/soft reset events follwoing VCONN swaps. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I289b5b5a60bbe7e880ff6b7f6fd9e5b0182f67a0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2917643 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: PE: Don't set AMS flag unless custom VDM has a replyScott Collyer2021-05-271-4/+6
| | | | | | | | | | | | | | | | | | | | This CL fixes an issue related to PE_FLAGS_INTERRUPTIBLE_AMS which was being set in pe_handle_custom_vdm_request_entry whether the custom VDM request is supported or not. This would result in PE_FLAGS_INTERRUPTIBLE_AMS remaining set and ignoring of subsequent VDM messages, which in turn prevents ALT-DP entry for UFP case. BUG=b:189293176 BRANCH=quiche TEST=Verfied that with this fix, ALT-DP mode is entered consistently. Without this CL, ALT-DP mode is not entered correctly. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I7a52a6028ea656d9a1970fea0b42f582f1aaff5c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2677707 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* adlrvp: Add dual retimer configurationPoornima Tom2021-05-272-0/+42
| | | | | | | | | | | | | | | | DDR5 based sku has dual retimer based topology for port0 & port1. Identify DDR5 board & reconfigure usbmux at run time to support dual retimer topology. BUG=b:189190982 BRANCH=none TEST=Able to configure the retimers and TBT is detected. Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I0ff859f7770a6c55931d413b2ea366d4f6aafe84 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2712214 Reviewed-by: caveh jalali <caveh@chromium.org>
* chip/mt8192_scp: disalbe video hardware 4k capabilityYunfei Dong2021-05-272-1/+2
| | | | | | | | | | | | | | | | | | | Disables 4K capability because the platform doesn't support it temporarily. BRANCH=asurada BUG=b:187896757 BUG=b:168868411 BUG=b:185977882 TEST=VDAtest passes on Asurada Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Change-Id: I18211671fdfe13378affe28f201ca1ef67f4c36e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921691 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* volteer: Remove console help commandAbe Levkoy2021-05-271-0/+3
| | | | | | | | | | | | | | Save 5268 B of flash on volteer_apmodeentry and 5268 B on volteer. BUG=b:189363246 TEST=make buildall BRANCH=firmware-volteer-13672.B-main Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I30a21260f7692be3288712b02625acd968994c60 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2920636 Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* flash_fp_mcu: Add warnings for conflicting processesCraig Hesling2021-05-271-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:188985272 b:181635081 TEST=# Run with biod start on helios scp util/flash_fp_mcu root@${DUT}:/usr/local/bin/flash_fp_mcu flash_fp_mcu --hello # Ensure warning triggered. stop biod stop timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log flash_fp_mcu --hello # Ensure no warnings are shown echo spi-PRP0001:02 >/sys/bus/spi/drivers/cros-ec-spi/unbind flash_fp_mcu --hello # Ensure the warning about cros-ec driver not being bound was # emitted # Bind raw driver and hold it open echo spi-PRP0001:02 >/sys/bus/spi/drivers/cros-ec-spi/unbind echo spidev >/sys/bus/spi/devices/spi-PRP0001\:02/driver_override echo spi-PRP0001:02 >/sys/bus/spi/drivers/spidev/bind exec 10<>/dev/spidev1.1 flash_fp_mcu --hello # Ensure warnings about cros-ec bound + raw bound + raw file open # are emitted. Change-Id: I1dded083ad158307ec54866952cf3ed59f30caf5 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912371
* cret: add Power LED behaviorjohnwc_yeh2021-05-274-77/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Battery control for Cret. Power LED: System S0: White System S0ix: Blinking white (1 sec on, 1 sec off) System S5/G3: Off. Battery LED: DC mode: System S0: off. System S5/G3: Off. System battery low: Blinking Amber (1 sec on, 1 sec off). AC mode: Charging: Amber. Full charged: White. Battery low or AC only: Blinking Amber (1 sec on, 1 sec off). BUG=b:188900681 BRANCH=dedede TEST=test on cret ，battery 、 Power LEDs are work. Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com> Change-Id: I184753a738576772e37baa37e0484e9cd9834b7b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919152 Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* npcx9: fix the workaround for unexpected JTAG selectionJun Lin2021-05-275-12/+43
| | | | | | | | | | | | | | | | | | | | | There is a workaround to disable the JTAG selection when the JTAG is enabled unexpectedly by the strap pin. In npcx9, the register to control the JTAG selection is different. This CL uses the correct register to let the workaround work correctly. BRANCH=none BUG=b:165777478 TEST=pass "make buildall"; check the register is correctly configured; check JTAG can be disabled when "CONFIG_ENABLE_JTAG_SELECTION" is not defined and JEN strap pin is pulled down on npcx9_evb. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: Ic7a8a7d99335610cbacfb1de285cdd8fbda70848 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867125 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* stm32g4: flash: Add DBANK support to option bytes WRPScott Collyer2021-05-273-60/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds support for the option bytes for dual-bank (DBANK) mode in category 3 devices. The MCU being used on honeybuns, is a category 3 flash device and DBANK mode is enalbed in the option bytes by default. When DBANK mode is enabled, then more than 1 WRP register is needed to protect the RW image. In this mode, WRP register can only protect 64 flash pages in one flash bank. BUG=b:183686750 BRANCH=quiche TEST= Case 1: HW WP active and code executing in RW > flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 0, end = 31 flash-phy: WRP_RW: start = 32, end = 127 Flags: wp_gpio_asserted ro_at_boot ro_now all_now Protected now: YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY Case 2: HW WP active active and code executing in RO flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 0, end = 31 flash-phy: WRP_RW: start = 127, end = 0 Flags: wp_gpio_asserted ro_at_boot ro_now Protected now: YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ Case 3: HW WP disabled > flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 127, end = 0 flash-phy: WRP_RW: start = 127, end = 0 Flags: ro_at_boot Protected now: ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I72c03029b0231ee864afc967905c50acba4ba5de Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911738 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* brya: Board ID 1: Handle BATT_PRES reassignmentCaveh Jalali2021-05-272-6/+27
| | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the battery presence detect GPIO has moved to the previous keyboard backlight enable pin. BRANCH=none BUG=b:183452273 TEST=booted on brya board ID 1, check battery present status on ID_1_EC_BATT_PRES_ODL. Cq-Depend: chromium:2914207 Change-Id: Ibae2a5e1f43c83360535e0d60c2a343bf9ef2421 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2916413
* brya: Board ID 1: Handle TCPC_RST reassignmentCaveh Jalali2021-05-273-3/+43
| | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the TCPC C0/C2 reset GPIO has moved to a previously unused pin. The original pin is now an ADC input pin. BRANCH=none BUG=b:183452273 TEST=verified TCPC C0/C2 can be reset on board ID 1 using ID_1_USB_C0_C2_TCPC_RST_ODL. Change-Id: I52d8044ed10379346ae36d4f5d6cbe7446867182 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914209 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Board ID 1: Handle KB_BL_EN reassignmentCaveh Jalali2021-05-272-2/+26
| | | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the keyboard backlight enable GPIO has moved to a previously unused pin and its polarity is inverted. The original pin is now an ADC input pin. BRANCH=none BUG=b:183452273 TEST=verified keyboard backlight function with "kblight" EC console command Change-Id: I86a1b09c9aaab8f6275a65cd1331f135b152f538 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914208 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Board ID 2: Update generated-gpio.inc from spreadsheetCaveh Jalali2021-05-271-6/+6
| | | | | | | | | | | | | | | This updates the byra GPIO definitions to match the board ID 2 schematics. BRANCH=none BUG=b:183452273 TEST=booted on board ID 1 with following patches Change-Id: I55f1f926f7adbd113c8e8a4dcdff9ec2ae667ab6 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914207 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* TCPMv2: Enable logging of CCD line stateudaykiran2021-05-271-0/+17
| | | | | | | | | | | | | | This CL logs the CCD line state of CCD_MODE_ODL upon DP-Altmode entry. BUG=b:170895220 BRANCH=none TEST=make buildall -j and verify that images build successfully. Signed-off-by: udaykiran <udaykiran@google.com> Change-Id: Iabee1a16e2497fd4ada2c2c06b65bef9d5ab1593 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2915756 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* honeybuns: Move configs for MP release to board.hScott Collyer2021-05-264-3/+20
| | | | | | | | | | | | | | | | | This CL moves the configs that are needed to be changed for an MP release to the board.h files from baseboard.h. BUG=b:183686750 BRANCH=quiche TEST=make BOARD=quiche/gingerbread/baklava Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I7c602ecb2f2af02638be080613bb83dee568c332 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911737 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* CCGXXF: Enable Auto Discharge DisconnectIurii Berezhanskyi2021-05-261-0/+2
| | | | | | | | | | | | | | | | | | Enable Auto Discharge functionality in TCPM driver by hooking tcpci_tcpc_enable_auto_discharge_disconnect() wrapper into tcpci_tcpm_drv structure. BUG=none BRANCH=none TEST=Tested on ADLRVP, USB4 with TCPCI works as expected Change-Id: I87af20b031ce58e74f9fa7e9b4a8b5eee0002d72 Signed-off-by: Iurii Berezhanskyi <iurii.berezhanskyi@infineon.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914973 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
* oak: Disable AMON BMON console command to save spaceVijay Hiremath2021-05-261-1/+0
| | | | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make BOARD=oak -j Before: 24 bytes in flash and 11760 bytes in RAM still available on oak RO 12716 bytes in flash and 11760 bytes in RAM still available on oak RW After: 408 bytes in flash and 11760 bytes in RAM still available on oak RO 13052 bytes in flash and 11760 bytes in RAM still available on oak RW Change-Id: Ib14376020e06e54b679ba5b6af853b219b0c0c3d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2920792 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Revert "brya: reduce TCPC debug level to unblock testing"Boris Mittelberg2021-05-261-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7275ced0eadbf0adfe307f2e3c49f830e488f89a. Reason for revert: PD State names are required for FAFT to work Original change's description: > brya: reduce TCPC debug level to unblock testing > > Important EC log messages are getting overlapped by TCPC/PD messages. The > default level is now set to 0. > > BRANCH=none > BUG=b:186707521 > TEST=running FAFT PD with `pd dump 0` works > > Signed-off-by: Boris Mittelberg <bmbm@google.com> > Change-Id: Ia3415c878e49bae01460f5e2acb6b8ce736b9986 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2904553 > Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> > Reviewed-by: caveh jalali <caveh@chromium.org> Bug: b:186707521 Change-Id: Ied5f926f87d75917295e36b4f6bd70fd6318d7d1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2920799 Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: caveh jalali <caveh@chromium.org>
* stm32/system: Wait for RVU bit clear before updating IWDG_RLRPatryk Duda2021-05-262-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC is not waiting for IWDG_RLR value to be updated in watchdog_init() function. It's intended behaviour because updating value can take much time (even 48ms) which is not desired during initialization. It's also allowed by documentation too: RM0433 Rev 7 Section 45.4.4 Page 1920 https://www.st.com/resource/en/reference_manual/dm00314099.pdf If several reload, prescaler, or window values are used by the application, it is mandatory to wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset before changing the prescaler value, and to wait until WVU bit is reset before changing the window value. However, after updating the prescaler and/or the reload/window value it is not necessary to wait until RVU or PVU or WVU is reset before continuing code execution except in case of low-power mode entry. Documentation clearly states that before next Reload Register update we are obligated to wait until RVU bit in IWDG_SR register is cleared. Setting IWDG_RLR register when RVU bit is set causes new value to be ignored. This is exactly the behaviour observed while running flash_write_protect hardware unit test. Time of Step 2 execution is short enough to perform hard reboot (all reboots between test steps are hard) when RVU bit is set. As a result setting IWDG_RLR to 1 is ignored and watchdog is reloaded with old value. This is why it takes very long to perform hard reset and watchdog trace is printed. Platforms affected by this change: STM32H7: nocturne_fp (dartmonkey) nucleo-h743zi STM32F4: hatch_fp (bloonchipper) nucleo-f411re nucleo-f412zg polyberry sweetberry stm32f446e-eval BUG=b:170432597 BRANCH=none TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that test passes and no watchdog traces appear. TEST=Run flash_write_protect hardware unit test on dragonclaw 0.2 board using `./test/run_device_tests.py --board bloonchipper \ --tests flash_write_protect` Make sure that test passes and no watchdog traces appear. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I2585dcbf3cb1a14107c7ae674c51999f082e3df7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2917115 Reviewed-by: Craig Hesling <hesling@chromium.org>
* Zephyr: brya: add basic template for brya boardYuval Peress2021-05-2611-0/+268
| | | | | | | | | | | | | Verify that npcx9 configuration and drivers work. BRANCH=none BUG=b:188605676 TEST=flash brya, check that LEDs work and console turns on Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I334ffc504da81ee6a6bb11b245b01a364ea05c6a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2909754 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: Change default values for PD_TCPC_VCONNMichał Barnaś2021-05-261-0/+2
| | | | | | | | | | | | | | | | There were no ITxxx drivers and SYV682X_NO_CC Kconfig, so default value for PD_TCPC_VCONN was different in Zephyr and CrOS. This commit adds default values for different configs. BUG=b:182500469 BRANCH=none TEST=Compare Kconfig.usbc with config.h Signed-off-by: Michał Barnaś <mb@semihalf.com> Change-Id: I2992fcd02c80957ed736b378dee2849dff03a315 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919911 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: Add PLATFORM_EC_USBC_PPC_SYV682X_NO_CC to KconfigMichał Barnaś2021-05-262-0/+13
| | | | | | | | | | | | | | | | | | There was no option to compile zephyr with flag SYV682X_NO_CC This commit adds this to Kconfig as PLATFORM_EC_USBC_PPC_SYV682X_NO_CC This config changes default value of PLATFORM_EC_USB_PD_TCPC_VCONN BUG=b:182500469 BRANCH=none TEST=Add CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_NO_CC=y to any prj.conf Execute zmake configure and build. Verify that this flag is set in outputted .config in build directory Signed-off-by: Michał Barnaś <mb@semihalf.com> Change-Id: Ic6bcdb9f3560813ba30149d9581b161eebb5c581 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919910 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: Add IT8XXX drivers to KconfigMichał Barnaś2021-05-264-4/+34
| | | | | | | | | | | | | | | | | | | | There was no possibility to use ITE_ON_CHIP in zephyr. This commit adds possibility to use it as TCPM. It adds also Kconfigs for IT8XXX2 and IT83XX drivers BUG=b:182500469 BRANCH=none TEST=Manipulate prj.conf to check if drivers are compiled: PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX=y PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y Try building with different options. Eg. enabling drivers without using ITE_ON_CHIP should change nothing in build. Signed-off-by: Michał Barnaś <mb@semihalf.com> Change-Id: I31a9a6899123b855ed82d92b46f023db77714b5a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919909 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* it8xxx: Improve ifdef expression for IT8XXX driversMichał Barnaś2021-05-261-3/+5
| | | | | | | | | | | | | | | | | | IT83XX and IT8XXX2 drivers are not compiled if the flag CONFIG_USB_PD_TCPM_ITE_ON_CHIP is not defined. So instead of the first two flags, the ITE_ON_CHIP is used in expression that undefines CONFIG_USB_PD_TCPC_VCONN BUG=b:182500469 BRANCH=none TEST=Use util/compare_build.sh to verify if firmware wasn't changed with this commit. Boards tested: "icarus kracko haboki cozmo drawcia lantis wheelie volteer delbin" Signed-off-by: Michał Barnaś <mb@semihalf.com> Change-Id: If26e855186c56c9cf118e727b8bafe5e3d1ea734 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919908 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Reland "zephyr: zmake: Show devicetree / compiler errors"Simon Glass2021-05-263-12/+381
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a984234afc7763018f9b5f9e767e567fd1137e4c. Reason for revert: Seeing if this can be landed now Original change's description: > Revert "zephyr: zmake: Show devicetree / compiler errors" > > This reverts commit 6b3b01cbf8a7c2a6a41402fcbc504028b4434497. > > Reason for revert: depends on CL:2807486, which is responsible for CQ > failures (crbug.com/1198472). > > BUG=chromium:1198472 > BRANCH=none > TEST=pytest zephyr/zmake/test > > Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> > Change-Id: I3f05e547c95b05d0ac3803bed946d7666346bf25 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2823546 > Reviewed-by: Sonny Rao <sonnyrao@chromium.org> BUG=b:184298184, chromium:1198472 BRANCH=none TEST=(cd zephyr/zmake/; python3 -m pytest tests/*.py -v -k test_filter) Change-Id: I9065a5682090b5e32414bbb6a518788ec02a6f0c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2841024 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* Homestar:LED:LED function realizationtongjian2021-05-263-67/+59
| | | | | | | | | | | | BUG=b:187539586 TEST=make -j BOARD=homestar Verify build on EVT board BRANCH=Trogdo Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Change-Id: I9c77b60e11135df5e289ef32adfe34fef3134760 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2915162 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* zephyr: cros_system_npcx: do jtag_init only when dbg node existsJun Lin2021-05-261-0/+2
| | | | | | | | | | | | | | | | With this CL, we can build the zephyr project even when the dbg node is not declared in the device tree. BRANCH=none BUG=none TEST=remove dbg node from npcx.dtsi, there is no build error reported. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I8c4ec1f81ba04e62d9b871b10d185d1244a2da6b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2918808 Reviewed-by: Yuval Peress <peress@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org> Tested-by: Yuval Peress <peress@chromium.org>
* brya: Board ID 1: Set GPIO PCHHOT as inputCaveh Jalali2021-05-261-1/+1
| | | | | | | | | | | | | | | This fixes the definition of the PCHHOT GPIO to be an input on the EC side. This signal can be used to monitor the PCH status. Updated the GPIO spreadsheet for board ID 1 and regenerated file. BRANCH=none BUG=b:184811017 TEST=boots on brya board ID 1 Change-Id: Idde5ef2e95c1690833532eb598c257a001499f4d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2918476 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* asurada: implement customized usb port power controlTing Shen2021-05-264-2/+16
| | | | | | | | | | | | | | | | | | | | | Some Sandisk stickers would enter fault status (down-train to USB2 or not detected) if Vbus is applied before xhci initialization. To fix this, copy usb_port_power_dumb.c to baseboard folder to implement board-specific enable mechanic. BUG=b:187149602 TEST=manually BRANCH=asurada Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I80536b640b4f67a4c17a3da7b193c92ab2f7b3eb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2909972 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* haboki: Update fw_config_dbTommy Chung2021-05-261-6/+12
| | | | | | | | | | | | | | | | Update fw_config_db to meet cbi_fw_config table on haboki. BUG=b:189154383 BRANCH=none TEST=on haboki, make sure that all DB configs act correctly. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I014afd6939094db12f4abd76483a21567e3aee8f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905035 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Commit-Queue: Henry Sun <henrysun@google.com>
* kracko: Update fw_config_dbTommy Chung2021-05-261-6/+12
| | | | | | | | | | | | | | | Update fw_config_db to meet cbi_fw_config table on kracko. BUG=b:189131006 BRANCH=dedede TEST=on kracko, make sure that all DB configs act correctly. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I0a2ccd9a90127a51042c115176e382900c396bf4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2902075 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Henry Sun <henrysun@google.com> Commit-Queue: Henry Sun <henrysun@google.com>
* lantis: Update fw_config_dbTommy Chung2021-05-261-6/+12
| | | | | | | | | | | | | | | Update fw_config_db to meet cbi_fw_config table on lantis. BUG=b:186393848 BRANCH=dedede TEST=on lantis, make sure that all DB configs act correctly. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I7cade5d603f815a60ba89c6cdf86ac48b41eafe3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2902073 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Henry Sun <henrysun@google.com>
* drawcia: Update fw_config_dbTommy Chung2021-05-261-6/+12
| | | | | | | | | | | | | | | | Update fw_config_db to meet cbi_fw_config table on drawcia. BUG=b:186393848 BRANCH=dedede TEST=on drawcia, make sure that all DB configs act correctly. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I1d123f6119911840f3ffae9d3746820ca3e5511d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2902071 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Henry Sun <henrysun@google.com>
* zmake: Allow filter tests to be run without pytestSimon Glass2021-05-261-46/+54
| | | | | | | | | | | | | | | | | | | | Put these tests in a class and add a main program so we can run the tests directly. This makes it easier to see any output produced by the test, for debugging purposes. For example a print() added to a test will not be suppressed. This makes debugging easier. BUG=b:184298184 BRANCH=none TEST=(cd zephyr/zmake/; PYTHONPATH=`pwd` python3 tests/test_zmake.py TestFunctional.test_filter ) Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ic5384d8926e54322a4bf828dd6ee91b1ab4507ff Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911474 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
* host sleep: add command to change sleep fail detection timeoutBoris Mittelberg2021-05-261-1/+46
| | | | | | | | | | | | | | | sleeptimeout is a new EC console command to change S3/S0ix sleep fail detection timeout. Needed for debug only. The command is present only if CONFIG_POWER_SLEEP_FAILURE_DETECTION is defined BRANCH=none BUG=b:187532888 TEST=manual Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I9a2afbb89dbfb4bdaf8666e06cf810e7cace9aad Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2904896 Reviewed-by: caveh jalali <caveh@chromium.org>
* usb_common: Assert CCD_MODE when DTS connectedRob Barnes2021-05-2611-5/+89
| | | | | | | | | | | | | | | | | | Drive CCD_MODE_ODL from EC when EC sees DTS connected to CCD port. This will fix some cases where the Cr50 is not able to detect that a CCD debug cable has been connected. BUG=b:175056327 TEST=Connect/disconnect SuzyQ cable, see assert/unassert in log Check gpioget on CR50 and ec, confirm CCD_MODE_ODL is correct Connect/disconnect charger, do not see assert/unassert in log Repeat with ServoV4 BRANCH=None Change-Id: I411e75a47f2e1303ddbd9caa63a9417630c99b46 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2659282 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Zephyr: npcx: Move fiu0 to a common locationYuval Peress2021-05-254-29/+9
| | | | | | | | | | | | | | | The fiu0 node is common to all npcx family chips. So it can live in npcx.dtsi. BRANCH=none BUG=b:188605676 TEST=build kohaku, trogdor, and volteer Cq-Depend: chromium:2916719 Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ied2ceaf04c32a2bf748c37bf70c303d3a6c94aab Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2909753 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: npcx: rename cros/nuvoton/npcx.dtsi to npcx7Yuval Peress2021-05-255-42/+57
| | | | | | | | | | | | | | | | | The the upstream changes to support npcx9 there have been some changes to the nuvoton dtsi structure. These allow us to now depend on the more generic npcx7.dtsi instead of the specific npcx7m6fb.dtsi. It also moves some of the common code of the npcx family away from the more specific npcx7. BRANCH=none BUG=b:188605676 TEST=build volteer, trogdor, and kohaku Change-Id: I552bad25c2d9392059ab5dcb0684a2bdac01d545 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2909752 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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