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* osiris: Update gpio output typestabilize-14918.B-mainYu-An Chen2022-06-161-2/+2
| | | | | | | | | | | | | | | | Set AMP_PWR_EN(GPIO57) to GPIO_OUT_LOW from GPIO_ODR_LOW. Set RGB_KB_INT(GPIO56) to GPIO_INPUT BUG=b:224423318 b:235020065 BRANCH=none TEST=HW team confirmed IO voltage as expected Signed-off-by: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com> Change-Id: I8550703b84249f339663861964b5d65c2eb17e0e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3706482 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* osiris: Remove unused i2c portYu-An Chen2022-06-163-11/+3
| | | | | | | | | | | | | | Remove unused i2c port BUG=b:224423318 BRANCH=none TEST=check i2cscan will not scan i2c3 Signed-off-by: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com> Change-Id: I31d5d8907ee99436b2f418ba693025843972a720 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705160 Commit-Queue: caveh jalali <caveh@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* nissa: Initial zephyr config for pujjojimmy.wu2022-06-1614-1/+1613
| | | | | | | | | | | | | Initial EC Zephyr config for Nissa/Pujjo. BUG=235755496 TEST=zmake build pujjo BRANCH=none Signed-off-by: jimmy.wu <jimmy.wu@lcfc.corp-partner.google.com> Change-Id: I81d0e505d3bacb7176d3e4356deb50301c4efc18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3688907 Reviewed-by: Andrew McRae <amcrae@google.com>
* zephyr: console: redirect messages to printk when shell is inactiveJun Lin2022-06-161-1/+2
| | | | | | | | | | | | | | | | | | | | The log messages printed in the main thread (e.x. the system banner) cannot be shown in the UART console. Instead, The warning message "WARNING: A print request was detected on not active shell backend." is printed. This CL redirects the log message to printk if the shell thread is inactive. BRANCH=none BUG=b:235896474 TEST=Check the system banner and other log messages in the main thread can be printed. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I42365b32d5131a80bd56c27c61e6a9aa360b250d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3706487 Reviewed-by: Andrew McRae <amcrae@google.com> Tested-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* corsola: Enable CHIPSET_RESUME_INIT hook configurationlschyi2022-06-162-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable CHIPSET_RESUME_INIT hook on mt8186 platform and corsola, and trigger it from S3 -> S0. BUG=b:229810117 TEST=Check the operation mode register (0x00) entering/leaving S3: (1) USB 3 device is connected, register value not changed with different type c side. (2) USB 2 device is connected, only the USB mode bit is unset at S3, and set in S0. (3) USB 2 device is connected in S0, and remove the device when in S3. USB mode bit is unset after back to S0. (4) Connect a A->C adapter in S0, then insert USB 2/3 device in S3. The USB mode bit is set after leaving S3. `lsusb` can identify the device under USB 2/3 bus. (5) USB mode bit is always unset if no device is connected. (6) type c display is connected, register value not changed. BRANCH=None Signed-off-by: lschyi <lschyi@google.com> Change-Id: Ic7bfcbc401e5e94d2cc8f2ec7d39c5801daaf0b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3707068 Tested-by: Sung-Chi Li <lschyi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Sung-Chi Li <lschyi@chromium.org>
* ps8743: Fix mode to apply power optimization and value to writelschyi2022-06-162-14/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apply the power optimization if USB mode is on and DP mode is off. The check of these modes are achieved by checking the Misc register. Correct value to write to the mode register. As the optimization only applies when only USB2 devices are connected, and should not turn on USB mode if device is removed during S3, create enum and record status with internal variable, then restructure the logic for suspend and resume. BUG=b:229810117 TEST=Check the operation mode register (0x00) entering/leaving S3: (1) USB 3 device is connected, register value not changed with different type c side. (2) USB 2 device is connected, only the USB mode bit is unset at S3, and set in S0. (3) USB 2 device is connected in S0, and remove the device when in S3. USB mode bit is unset after back to S0. (4) Connect a A->C adapter in S0, then insert USB 2/3 device in S3. The USB mode bit is set after leaving S3. `lsusb` can identify the device under USB 2/3 bus. (5) USB mode bit is always unset if no device is connected. (6) type c display is connected, register value not changed. BRANCH=None Change-Id: Ic85ee805ffea26bfa3fc5004c3d319cefcf2e68e Signed-off-by: lschyi <lschyi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3702073 Commit-Queue: Sung-Chi Li <lschyi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Sung-Chi Li <lschyi@chromium.org>
* nivviks: update def-lvol-io-list with 1.8V GPIOsCH Lin2022-06-161-1/+8
| | | | | | | | | | | | | | | | | Few GPIO's which operate at 1.8v are added to the property of def-lvol-io-list device node. This improves in EC power consumption in S0ix mode. BUG=b:228222441 BRANCH=none TEST=Verified S0ix on nivviks Change-Id: I58cb81ba8e85bf03998b8e7abcf994ef4d12ea6f Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3702877 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Andrew McRae <amcrae@google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* agah: support USBC retimerZick Wei2022-06-163-10/+74
| | | | | | | | | | | | | | | | | This patch apply support of USBC retimer ps8818 on USBC2, will upload another CL after EQ setting confirmed. BUG=b:218400524, b:233552228 BRANCH=none TEST=make BOARD=agah Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: I3f6490dd8809b37cf974f2663374a472399c5861 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3406469 Commit-Queue: Kenny Pan <kennypan@google.com> Reviewed-by: Kenny Pan <kennypan@google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* Agah: Change GPIO_EN_PPVAR_BJ_ADP control methodDavid Huang2022-06-162-3/+3
| | | | | | | | | | | | | | | | | Change GPIO_EN_PPVAR_BJ_ADP control method for proto 1. BUG=none BRANCH=none TEST=Attached BJ adapter and system can power on. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I9b0cbf86d8c1b63dbe60df435cd01263edf4bf26 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3662669 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: David Huang <david.huang@quanta.corp-partner.google.com> Commit-Queue: Kenny Pan <kennypan@google.com> Tested-by: Kenny Pan <kennypan@google.com>
* Felwinter: Move RT_RST to different pinLeila Lin2022-06-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | Felwinter moves the USB_C2_RT_RST_ODL pin from GPIO02 to GPIO07 of the nct3807. When a debug accessory is connected, GPIO02 becomes uncontrollable and causes FAFT setup test errors. So move RT_RST to different pin. BRANCH=brya BUG=b:234560670 TEST=build pass and run FAFT setup test pass. Signed-off-by: Leila Lin <leilacy_lin@compal.corp-partner.google.com> Change-Id: I5206b66a424aab7756b0e077f3b972d0c18756bd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3697270 Commit-Queue: LeilaCY Lin <leilacy_lin@compal.corp-partner.google.com.test-google-a.com> Tested-by: LeilaCY Lin <leilacy_lin@compal.corp-partner.google.com.test-google-a.com> Reviewed-by: Ricky Chang <rickytlchang@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org> Auto-Submit: LeilaCY Lin <leilacy_lin@compal.corp-partner.google.com.test-google-a.com> Reviewed-by: Ko Ko <ko_ko@compal.corp-partner.google.com> Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com>
* Mithrax: Turn on RGB enable pin by CBIjohnwc_yeh2022-06-161-0/+12
| | | | | | | | | | | | | | | Checking fw_config bit RGB to pull high enable pin. BUG=b:223526803, b:229186412 BRANCH=None TEST=make BOARD=mithrax Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com> Change-Id: I07cbdbab50c562b4467b613494f2a871d570f4c4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3703979 Reviewed-by: Ko Ko <ko_ko@compal.corp-partner.google.com> Tested-by: Ko Ko <ko_ko@compal.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* common: Fix host command print formattingFiras Sammoura2022-06-162-5/+5
| | | | | | | | | | | | | | | | | | | | Modify the format of how the host commands are being printed. Change the zero paddings from 2 to 4 to conform with the command, which is defined as a 16-bit value. The previous method will not result in incorrect output for commands requiring more than two digits. BUG=b:231975323 BRANCH=None TEST=./test/run_device_test.py --board bloonchipper TEST=make buildall Signed-off-by: Firas Sammoura <fsammoura@google.com> Change-Id: I4dd5507096a5a02f9554a164cae610683aebfec0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705694 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Bobby Casey <bobbycasey@google.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Tom Hughes <tomhughes@chromium.org>
* docs/fingerprint: Resolve contradictory FPMCU factory flashing instructionsTom Hughes2022-06-161-5/+2
| | | | | | | | | | | | | | | | | In fingerprint-factory-requirements.md, we said we don't recommend using "flash_fp_mcu" for mass production, but fingerprint-factory-quick-guide.md recommended using "update_fpmcu_firmware.py" (which uses "flash_fp_mcu"). BRANCH=none BUG=b:234772776 TEST=view in gitiles Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: If1c15c800b00b84688bdd2f7175462ef94a269c1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3687545 Reviewed-by: Bobby Casey <bobbycasey@google.com> Reviewed-by: Andrea Grandi <agrandi@google.com>
* Agah: Enable bypass modeDaisuke Nojiri2022-06-156-41/+226
| | | | | | | | | | | | | | | | | | | | | This patch enables bypass mode for ISL9241 on Agah. Tested cases: 1. Boot on BJ. 2. Unplug BJ. 3. Boot on Type-C. 4. Unplug Type-C. 5. Switch from Type-C to BJ. 6. Not switching from BJ to Type-C. BUG=b:214057333, b:216206104 BRANCH=None TEST=On Agah. See above. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I8d015d401291391b8b8e7f25e9db8697d211cd4d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3583044 Reviewed-by: Kenny Pan <kennypan@google.com>
* Makefile: Set core-specific LLVM toolchainTom Hughes2022-06-153-5/+19
| | | | | | | | | | | | | | | There are separate toolchains for ARMv6-M (cortex-m0) and ARMv7-M (cortex-m). BRANCH=none BUG=b:172020503, b:234181908 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Icc131934a7b721ef3732d1b0e3f26bd4906239d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3693041 Reviewed-by: Diana Z <dzigterman@chromium.org>
* tree: Files should end with single newlineTom Hughes2022-06-1515-15/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | One of the checks that runs as part of "repo upload" looks for a single newline at the end of each file. I'm getting warnings about this when I touch files that do not follow this, even though I didn't add the extra newlines. This commit fixes additional files not included in https://crrev.com/c/3229797 by running the following: for f in $(find . -name '*.mk'); do printf '%s\n' "$(cat ${f})" > ${f}; done for f in $(find . -name '*.S'); do printf '%s\n' "$(cat ${f})" > ${f} done BRANCH=none BUG=b:172020503, b:234181908 TEST=./util/compare_build.sh -b all -j 120 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ib4e4d0e74bf3b00a0b2c81505fef65e2c1b7401f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705766 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* emul: usb common partner describes delay unitsAaron Massey2022-06-151-1/+1
| | | | | | | | | | | | | | | | | The delay parameter in the tcpci_partner_send_control_msg function desoen't describe a unit of time in the function doc. Describe the unit of time so clients don't have to delve into the implementation to find out the unit of time. BRANCH=none BUG=None TEST=zmake test test-drivers Signed-off-by: Aaron Massey <aaronmassey@google.com> Change-Id: Iaf5214fdfcf2eafb2440c1fd317521baaaa4418c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708433 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* tests: Successful invoke of pd_get_amode cmdAaron Massey2022-06-151-0/+21
| | | | | | | | | | | | | | Verify that invoking the EC host command EC_CMD_USB_PD_GET_AMODE has a successful return code and the response size is unchanged. BRANCH=none BUG=b:219562077 TEST=zmake test test-drivers Signed-off-by: Aaron Massey <aaronmassey@google.com> Change-Id: Icd29c921c0c080aeff1316bfa7b211d63687f9fe Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3687085 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* tests: usb_alt_mode uses constant defined portAaron Massey2022-06-151-2/+4
| | | | | | | | | | | | | | Replace usages of a particular port number in the usb_alt_mode tests with a #define TEST_PORT to remove the magic port number usages. BRANCH=none BUG=b:219562077 TEST=zmake test test-drivers Signed-off-by: Aaron Massey <aaronmassey@google.com> Change-Id: I410a0ae8ef7a0e9b2d61e8fd4dc253a60a460308 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3687082 Reviewed-by: Al Semjonovs <asemjonovs@google.com>
* core/cortex-m[0]: Remove C++ exception unwind stubsTom Hughes2022-06-152-18/+0
| | | | | | | | | | | | | | | | | | | | | | These symbols should only be needed for unwinding C++ exceptions: https://sourceware.org/binutils/docs/as/ARM-Unwinding-Tutorial.html It's unclear why these are here since we're not compiling with C++ at this point. The code was introduced in commit e24fa592d2a215d8ae67917c1d89e68cdf847a03, which doesn't provide any details. Once we start compiling C++, these definitions cause problems since they conflict with the real symbols in libunwind. BRANCH=none BUG=b:234181908 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I085ba56a822cae4b02991a9e5395aba60ec8bad7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3701131 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* chip/stm32: Set -mcpu to cortex-m7 for STM32H7Tom Hughes2022-06-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling this slightly increases the amount of flash used in dartmonkey's RW: Before the change: RO: 740252 bytes in flash and 509440 bytes in RAM still available RW: 802380 bytes in flash and 506112 bytes in RAM still available After the change: RO: 740252 bytes in flash and 509440 bytes in RAM still available RW: 802324 bytes in flash and 506112 bytes in RAM still available BRANCH=none BUG=b:145677491 TEST=./test/run_device_tests.py --board dartmonkey Test "aes": PASSED Test "cec": PASSED Test "cortexm_fpu": PASSED Test "crc": PASSED Test "flash_physical": PASSED Test "flash_write_protect": PASSED Test "fpsensor_hw": PASSED Test "fpsensor_spi_ro": PASSED Test "fpsensor_spi_rw": PASSED Test "fpsensor_uart_ro": PASSED Test "fpsensor_uart_rw": PASSED Test "mpu_ro": PASSED Test "mpu_rw": PASSED Test "mutex": PASSED Test "pingpong": PASSED Test "printf": PASSED Test "queue": PASSED Test "rollback_region0": PASSED Test "rollback_region1": PASSED Test "rollback_entropy": PASSED Test "rtc": PASSED Test "sha256": PASSED Test "sha256_unrolled": PASSED Test "static_if": PASSED Test "system_is_locked_wp_on": PASSED Test "system_is_locked_wp_off": PASSED Test "timer_dos": PASSED Test "utils": PASSED Test "utils_str": PASSED Test "panic_data_dartmonkey_v2.0.2887": PASSED Test "panic_data_nocturne_fp_v2.2.64": PASSED Test "panic_data_nami_fp_v2.2.144": PASSED TEST=./util/compare_build.sh -b all -j 120 => All boards match, except the following Cortex M7 boards: dartmonkey nami_fp nocturne_fp nucleo-dartmonkey nucleo-h743zi Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I0b611ccccfaaf2f930c5b00a9eaa51cd1806c276 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3699794 Reviewed-by: Andrea Grandi <agrandi@google.com>
* core/cortex-m: Set FPU to autoTom Hughes2022-06-151-1/+13
| | | | | | | | | | | | | | | | | | | | | | | Use "-mfpu=auto" so that the compiler will choose the correct FPU settings based on the settings of -mcpu and -march: https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html. According to the above doc "-mfpu=auto" is the default and shouldn't be required, but compilation using gcc fails without the flag. clang does not support the "-mfpu=auto" flag, but will choose the correct floating point unit based on the -mcpu flag: https://lists.llvm.org/pipermail/llvm-dev/2018-September/126468.html BRANCH=none BUG=b:145677491, b:234181908 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I3c255ee53e31763d29dfb2086fcebf3d8290dc56 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3699793 Reviewed-by: Andrea Grandi <agrandi@google.com>
* chip: Remove -march, since -mcpu itself is sufficientTom Hughes2022-06-156-15/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the GCC documentation: -mcpu specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified by -march) and the ARM processor type for which to tune for performance (as if specified by -mtune). https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html This means that unless we're overriding some setting with -march or -mtune, there's no need to specify them. In our case, we aren't overriding the default for -mtune that -mcpu sets, so make things simpler by only specifying -mcpu. Additional details in https://community.arm.com/arm-community-blogs/b/tools-software-ides-blog/posts/compiler-flags-across-architectures-march-mtune-and-mcpu BRANCH=none BUG=b:145677491 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I1999ef25642ed9e32b2e8eeb76d4ba7a23dc2b8a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3699792 Reviewed-by: Andrea Grandi <agrandi@google.com>
* nissa: correct name of craask CMake projectPeter Marheine2022-06-151-1/+1
| | | | | | | | | | | BUG=none TEST=builds BRANCH=none Change-Id: Icbe48f30837b8230b7d232b226ecea709639ed6c Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3707514 Reviewed-by: Andrew McRae <amcrae@google.com>
* nissa: define LED policy for S0_BAT_LOWPeter Marheine2022-06-151-0/+2
| | | | | | | | | | | | | | Not having a policy for this state causes frequent errors to be logged to the console when in S0 and the battery is low. BUG=b:236093557 TEST=builds BRANCH=none Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: Ia42c74a11d4af5ec2be0a22871afc5b66dd6fa2a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3707513 Reviewed-by: Andrew McRae <amcrae@google.com>
* charge_state: Remove unnecessary macro guardsDaisuke Nojiri2022-06-151-3/+1
| | | | | | | | | | | | | | | | | | Declarations don't needed to be guarded unless there is a conflicting declaration. This patch removes guards for charge_get_percent and board_get_battery_soc in charge_state.h. This patch allows the aforementioned declarations to be used in unit tests without declaring CONFIG_CHARGER or CONFIG_BATTERY. BUG=None BRANCH=None TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Iee833210e00b34df874c89cacfc49d45253b5600 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704269 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* test: Relocate test_mockable for better compatibilityDaisuke Nojiri2022-06-151-16/+16
| | | | | | | | | | | | | | | | test_mockable macros are placed after config.h. This causes header files included indirectly by common.h not to be able to use the macros. This patch places test_mockable macros before config.h in common.h so that the macros will be defined for aforementioned header files. BUG=None BRANCH=None TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I05716931bc7aedd3171569189ae228d2e9052b13 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704267 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* zephyr: allow only one power sequencing option via kconfigPeter Marheine2022-06-151-0/+1
| | | | | | | | | | | | | | PLATFORM_EC_POWERSEQ and AP_PWRSEQ implement the same subsystem, so update the kconfig to prevent both from being enabled at the same time. BUG=b:233681784 TEST=zmake testall BRANCH=none Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: Ied6ffdd8b541acb343ac4e36ea901f9d252717c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3703088 Reviewed-by: Keith Short <keithshort@chromium.org>
* chipset: introduce CONFIG_AP_POWER_CONTROLPeter Marheine2022-06-1521-63/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | Because the new Zephyr power sequencing support is gated on a different config option than HAS_TASK_CHIPSET which code has historically assumed implies there is an AP present, it is now easy to introduce bugs when code that applies in both configurations uses the old option test. This change decouples the presence of an AP from HAS_TASK_CHIPSET, introducing a new CONFIG_AP_POWER_CONTROL symbol that is derived from the power sequencing config options. All existing applicable users of HAS_TASK_CHIPSET are changed to use the new symbol, fixing several callers which would not behave correctly under Zephyr with the new power sequencing code. The duplicate stub implementations of functions provided by Zephyr's chipset_api are removed, because they already appear in the header that declares those functions. BUG=b:233681784 TEST=make buildall, zmake testall BRANCH=none Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I282da30839ca52fcc88c6f9dea2bd00d4811b976 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3670735 Reviewed-by: Keith Short <keithshort@chromium.org>
* adlrvp[rpl]: Disable dual role toggle in S0poornima tom2022-06-151-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FUSB TCPC chip does not support dual role auto toggle by default. Hence, the PD state of a non-attached port remains in PD_DRP_TOGGLE_ON in active state. Thus the TCPC ports do not enter Low power mode. To fix the issue, added board specific code to disable the dual role toggle in S0. Note: Originally CL:3088161 was merged to fix this issue. But, it was reverted due to b:197298349(CL:3109275). BUG=b:195406641 BRANCH=none TEST=Tested on ADL RVP on ITE & FUSB based TCPC ports In NDA case and exit of LPM when a device is attached: >pd 0 state Port C0 CC1, Disable - Role: SNK-UFP TC State: LowPowerMode, Flags: 0x0010 PE State: , Flags: 0x8400000 >pd 1 state Port C1 CC1, Disable - Role: SNK-UFP TC State: LowPowerMode, Flags: 0x0010 PE State: , Flags: 0x8400000 Any attachment of any TypeC based device exits the port from low power mode. Example of attaching TBT: C0: Exit Low Power Mode] -- >pd 0 state Port C0 CC2, Enable - Role: SNK-DFP-VC TC State: Attached.SNK, Flags: 0x9001 PE State: PE_SNK_Ready, Flags: 0x8211 >typec 0 Port 0: USB=0 DP=0 POLARITY=INVERTED HPD_IRQ=0 HPD_LVL=0 SAFE=0 TBT=1 USB4=0 Signed-off-by: poornima tom <poornima.tom@intel.com> Change-Id: Ia47a0b252fd3ce9da27832dbcba1298897c6406f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3690048 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* zephyr: Remove choice from pd_vbus_detection KconfigBrandon Breitenstein2022-06-151-6/+0
| | | | | | | | | | | | | | | | Some platforms might need to use multiple different vbus detection types. It is up to the board to differentiate which ports need what type of vbus detection. BUG=b:236127051 BRANCH=none TEST=zmake testall, and zmake mtlrvpp_npcx to verify that mtlrvp is able to use ppc on ports 0/1 and tcpc on 2/3 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Change-Id: Id0efbff95869da6bb8c1c74ad0cff55e52c5d174 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3703208 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Massey <aaronmassey@google.com>
* Mithrax:implement keyboard matrixjohnwc_yeh2022-06-155-5/+222
| | | | | | | | | | | | | | | | Implement customizition keyboard. Initialize vivaldi keyboard and modify combination key row and col. BUG=b:231249540 BRANCH=None TEST=make BOARD=mithrax and verify with evtest 2 Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com> Change-Id: Id72c5902e0a79a503173d5135aac9380a7200639 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3690198 Reviewed-by: Ricky Chang <rickytlchang@chromium.org> Commit-Queue: Ricky Chang <rickytlchang@chromium.org> Reviewed-by: Ko Ko <ko_ko@compal.corp-partner.google.com>
* krabby: enable lid accel interruptTing Shen2022-06-152-9/+2
| | | | | | | | | | | | | | | | | Follow asurada rev2+ to enable interrupt mode on lid sensor. Also removed duplicated int_base_imu entry. BUG=b:230818312 TEST=accelread BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I3a3c97c5631b99fc9961c4033c4e6f3b31ad1f2e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3702195 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* rt1718s: workaround Vconn output spike hits OCPEric Yilun Lin2022-06-152-3/+45
| | | | | | | | | | | | | | | | | | | | | | | | RT1718S is unable handle the Vconn output spike internally. We workaround this by disabling the Vconn OCP at the beginning of sourcing Vconn, and re-enable the OCP back after passing the spike stage. Also, make Vconn OCP detection less sensitive by increasing the detecting time to 3~5us. Last, this CL also turn on the Vconn RVP to prevent the hotplug short from VBUS. BUG=b:233698718 b:235173903 TEST=Tested with JCA374 hub, and the DP out functions normally. BRANCH=none Change-Id: I30bb1035afaaa183587f33c928f29d15bf48afac Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3676601 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com>
* gimble: modify ectool control battery ledElsie Shih2022-06-151-15/+34
| | | | | | | | | | | | | | We will use ectool led battery <amber | white> to test if led is working for factory automated testing. BUG=b:235763023 BRANCH=none TEST=make -j BOARD=gimble Signed-off-by: Elsie Shih <elsie_shih@wistron.corp-partner.google.com> Change-Id: I630efb195e496f6e834da8b5ea51684666530d0a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3448055 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* ap_pwrseq: Use correct polled power signalsAndrew McRae2022-06-141-1/+1
| | | | | | | | | | | | | | Ensure that the correct power signal is used when clearing the initial state of the power signals. BUG=b:234094006 TEST=zmake build nivviks BRANCH=none Signed-off-by: Andrew McRae <amcrae@google.com> Change-Id: Ib65a7a6a1537a74f9eafff28acea8715b572f8d6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705058 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* Revert "sm5803: verify CHG_MON_REG settings when sinking"Peter Marheine2022-06-142-35/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 042f73594fc0dd58c159f4cbec5133cc0b7be475. Reason for revert: charger problems appear to have been caused by low power mode ordering with regard to other operations; this check was not found to be useful. Original change's description: > sm5803: verify CHG_MON_REG settings when sinking > > Incorrect settings for this register may be implicated in hardware > damage that has been observed, so add a runtime check for correct > configuration before enabling sinking. This should help debugging of > issues that may be observed and prevent damage. > > CMD_CHARGER_DUMP is enabled on Nereid to assist in this investigation. > > BUG=b:230712704 > TEST=zmake build nereid, `charger dump` on earlier nereid shows charger > register 5C reading expected 7A. > BRANCH=none > > Change-Id: If81ec544b7b26ec20316cb7bc92eaa1770b1da77 > Signed-off-by: Peter Marheine <pmarheine@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3676613 > Reviewed-by: Andrew McRae <amcrae@google.com> Bug: b:230712704 Change-Id: I866f070b1afd83296d3872772ad6d9dcca6b1ff2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705676 Reviewed-by: Andrew McRae <amcrae@google.com> Tested-by: Peter Marheine <pmarheine@chromium.org> Commit-Queue: Peter Marheine <pmarheine@chromium.org>
* zephyr: herobrine: Obsolete LED file removalKshitiz Godara2022-06-149-191/+9
| | | | | | | | | | | | | | | | | Removed obsolete source file and changed villager dt names for uniformity. Also merged the LED configuration in common config and removed from inidividual config. BRANCH=None BUG=None TEST=Verified compilation for herobrine, villager and hoglin. Tested on hoglin and LED color is changing based on charging states. Signed-off-by: Kshitiz Godara <kgodara@qualcomm.corp-partner.google.com> Change-Id: I5471b97ea554692a1da2750d85bb802642db1345 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704918 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Parth Malkan <parthmalkan@google.com>
* taniks: remove unused define and code for clamshell systemarthur.lin2022-06-144-48/+9
| | | | | | | | | | | | | | | | Remove unused define and code about tablet mode, because taniks is clamshell only. BUG=b:231930177 BRANCH=none TEST=make buildall -j TEST=on taniks, run test_that -b brya "IP" power_WakeSources can get pass result. Signed-off-by: arthur.lin <arthur.lin@lcfc.corp-partner.google.com> Change-Id: Iaed80bb621993eb3b054cfce6e054630439becb8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3690035 Reviewed-by: Parth Malkan <parthmalkan@google.com> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* Banshee: Support different vivaldi keyboardJosh Tsai2022-06-144-8/+44
| | | | | | | | | | | | | | | | | | We need to support different vivaldi keyboard, so used board id to distinguish BRANCH=none BUG=b:231265647 TEST=evtest check the T8 function is KEY_KBDILLUMTOGGLE Signed-off-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Change-Id: Icb42a413b84e40a8a1fbf096928fe5410c39c378 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3670779 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com> Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com>
* zephyr: kingler: drop unused power-on configwen zhang2022-06-141-3/+0
| | | | | | | | | | | | | | Kingler will use D2, drop the workaround config for H1 BUG=b:234572040 TEST=verify the GPIO state after sysjump rw BRANCH=none Change-Id: I513ea6bb42f1091eafbf64c2cd8db820690c1ee3 Signed-off-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3692639 Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* moli: update power_monitor functionality and gpio configurationElsie Shih2022-06-143-154/+35
| | | | | | | | | | | | | | | - Add TYPE_C1 to power_monitor functionality - Modify USB_A_LOW_PWR1_OD / USB_A_LOW_PWR2_OD to GPIO_OUT_LOW - Modify current divider of ADC_PPVAR_IMON - Remove the 5v regulator capacity BUG=b:220670917, b:233007149, b:222550779 TEST=make BOARD=moli Change-Id: I655d229494cbc9ac77ef9f4d3ae0e4f123b5fd2a Signed-off-by: Elsie Shih <elsie_shih@wistron.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3653383 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* moli: modify fan frequencyElsie Shih2022-06-141-2/+2
| | | | | | | | | | | | | Modify fan freq to 25kHz and remove the PWM_CONFIG_DSLEEP flag. BUG=b:235436516 TEST=make BOARD=moli Signed-off-by: Elsie Shih <elsie_shih@wistron.corp-partner.google.com> Change-Id: Iff5e94110a1f6706abae5f3e0be90501d5b8fead Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3697269 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Vincent Wang <vwang@chromium.org>
* brya: increase SYV226 PWM freqCaveh Jalali2022-06-141-1/+1
| | | | | | | | | | | | | | | | | The SYN226 is rated at 10 KHz to 100 KHz on the PWM pin, so bump up the frequency to meet the spec. BRANCH=none BUG=b:235898482 TEST=verified keyboard backlight is still adjustable using keyboard shortcuts Change-Id: I4181fbc3ae8cf041e61581df7d52d172d1ea9504 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3701142 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: hoglin: Charger LED IndicatorsKshitiz Godara2022-06-145-4/+141
| | | | | | | | | | | | | | | | | | Hoglin board has single LED indicator on right side having two colors, red and blue. Added DT based charger LED indicators for all the cases. BRANCH=None BUG=b:230464231 TEST=Tested image on hoglin board for following 1) Charging indicator works fine in S0/S3/S5 2) Discharging indicator works fine in S3, off in S0/S5 3) ectool related commands working fine and led color changes accordingly Change-Id: I270500546fb4d8c5840ec6b446601945d77259e1 Signed-off-by: Kshitiz Godara <kgodara@qualcomm.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3702080 Reviewed-by: Parth Malkan <parthmalkan@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* zephyr: npcx9: Create platform specific keyboard DTS filesSam Hurst2022-06-1413-29/+297
| | | | | | | | | | | | | | | | | | | For npcx9 chips, move common keyboard DTS configuration into platform specific keyboard DTS files. BUG=b:229717952 BRANCH=none TEST=zmake testall On herobrine: Plug Non-PD 5V@2A charger into Port0 and Port1 and execute: chgsup port=0, type=3, cur=1500mA, vtg=5000mV, lsm=1 port=1, type=3, cur=1500mA, vtg=5000mV, lsm=1 Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I8ed884f32ea912d603a578a6443c13185b6e82e3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3628669 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* taniks: remove BYPASS_CBI_EEPROM_WP and SYSTEM_UNLOCKED definearthur.lin2022-06-141-3/+1
| | | | | | | | | | | | | | | remove CONFIG_BYPASS_CBI_EEPROM_WP_CHECK setting remove CONFIG_SYSTEM_UNLOCKED setting undefine CONFIG_CMD_POWERINDEBUG BUG=b:235285356, b:226200706 BRANCH=main TEST=make buildall -j Signed-off-by: arthur.lin <arthur.lin@lcfc.corp-partner.google.com> Change-Id: I7e13e35dc9b4d38866893faf87c0f039519d9ab6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3702078 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* baseboard/brya: add ifdef for CONFIG_TABLET_MODEarthur.lin2022-06-141-0/+2
| | | | | | | | | | | | | | | Add #ifdef in brya baseboard.c for compile successfully when undefine CONFIG_TABLET_MODE. BUG=b:231930177 BRANCH=none TEST=make buildall -j Signed-off-by: arthur.lin <arthur.lin@lcfc.corp-partner.google.com> Change-Id: I825ccd34ba381f6d85541315d64dee58d6a457f9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3695792 Reviewed-by: Parth Malkan <parthmalkan@google.com> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* zephyr: MTL driving PCH_PWROK from ECLi Feng2022-06-142-15/+27
| | | | | | | | | | | | | | Porting from CL:3585883. BUG=none BRANCH=none TEST=MTL-RVP can boot to S0 Signed-off-by: Li Feng <li1.feng@intel.com> Change-Id: I4fa2be2560f9eb31908a5676fec97a8912568542 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3658302 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Andrew McRae <amcrae@google.com>
* zephyr/mtlrvp: Update battery information to add aliasesBrandon Breitenstein2022-06-142-16/+1
| | | | | | | | | | | | | | | | | | Initial MTLRVP code did not add aliases for the types of battery options there were for the RVP. Since ADL and MTL RVPs share the same battery configs just reuse the ADL file instead of adding one in MTL. BUG=none BRANCH=none TEST=battery console command works on MTLRVP Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Change-Id: I3a44f41c066c2f5aa406d022fc8bb580896f2588 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3703207 Reviewed-by: RAJESH KUMAR <rajesh3.kumar@intel.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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