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* HC: check response buffer size before copying datastabilize-15359.58.B-mainstabilize-15359.50.B-mainstabilize-15359.45.B-mainrelease-R112-15359.B-mainLi Feng2023-03-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISH has allocated 128 bytes for HECI response message; 112 bytes can be used to store HC response data. But EC_CMD_GET_VERSION v1 response data has 132 bytes. Copying data without checking buffer size causes buffer overflow. And we observed an issue that HECI client handle is changed by this. The fix is to add size check and return EC_RES_RESPONSE_TOO_BIG on error. CL:4302834 increases ISH buffer size as well; so that host can get version information. BUG=b:271502099 BRANCH=none TEST=on Rex platform with ISH enabled, monitor HECI client handle value is the same all the time. No more "Timed out for response to host message". Change-Id: Ibee2fb6a54d3c7d1d60d90a8f6b20bc89066ff5a Signed-off-by: Li Feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4305920 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit c8234cc5335ad31d27d578d89bab4f2172e4f22a) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4359514 Tested-by: Li Feng <li1.feng@intel.corp-partner.google.com> Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
* dibbi: add back the MKBP event for the power keystabilize-15359.B-mainZhuohao Lee2023-02-231-4/+0
| | | | | | | | | | | | | | The MKBP event is needed otherwise the UI won't sense the power key event correctly. BUG=b:270501058 BRANCH=none TEST=deployed to the device and press power key in UI Change-Id: I8167f551f304bdf621e881bd653472e94a3615d5 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4286384 Reviewed-by: Sam McNally <sammc@chromium.org>
* dibbi: Always enable EN_PP5000.Sam McNally2023-02-232-11/+2
| | | | | | | | | | | BUG=b:269050050 TEST=Boot to OS on USB-C power BRANCH=none Change-Id: If2334dc5408fd0f86c7ae2880168e3653dfa22bc Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4240913 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* dibbi: Update temp sensors.Sam McNally2023-02-232-2/+17
| | | | | | | | | | | | | Temp sensor 2 is SoC power; temp sensor 3 is ambient. BUG=b:268309238 TEST=dibbi reports temperature values for 3 sensors BRANCH=none Change-Id: I0601ee49bdaf3d139931d37880f7934857837d2c Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4273929 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* Increase supported host events to 64Tim Van Patten2023-02-222-2/+13
| | | | | | | | | | | | | | | | | | | | | | ectool is hard-coded to support 32 host events even though the EC supports 64 host events. Add an enum value to indicate what the current count of the host events is, so it can used by ectool in place of magic numbers. Also add an assert to enforce the 64 host event limit. BRANCH=none BUG=b:261141172 TEST=Manually build and flash, verify device boots TEST=ectool version Change-Id: If9724cf905a7d2eb42a2ad67c5e1da784ca05e8e Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4261961 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mtlrvp: rex: Send VW based overcurrent to APVijay Hiremath2023-02-222-6/+19
| | | | | | | | | | | | | | | | Meteorlake PCH uses Virtual Wire for over current error, hence Send 'Over Current Virtual Wire' eSPI signal. BUG=b:243120083 BRANCH=none TEST=Observed 'usb usb3-portX: over-current condition' on MTLRVP Kernel console Change-Id: Ia4ac4b71622e91377410458efd57b1fa75c985a7 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3863940 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.corp-partner.google.com>
* zephyr/test/skyrim: Kconfig cleanupRobert Zieba2023-02-221-3/+0
| | | | | | | | | | | | | Cleanup unneeded default values. BRANCH=none BUG=b:247151116 TEST=Ran skyrim tests Change-Id: I2d99543db54f0b96deab54b9e0cb1325dd8863b1 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263561 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* zephyr/test/skyrim: Finish general refactorRobert Zieba2023-02-2213-2/+21
| | | | | | | | | | | | | Finish general refactor by moving remaining variant-specific code. BRANCH=none BUG=b:247151116 TEST=Ran skyrim tests Change-Id: I8c7f1c612292e96a66daf0df08e968c39293b168 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263560 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* zephyr/test/skyrim: Refactor USB mux config testRobert Zieba2023-02-229-13/+56
| | | | | | | | | | | | | | Move USB mux config test to match new code structure. Add fake functions to allow frostflow test to compile pending implementation of full test. BRANCH=none BUG=b:247151116 TEST=Ran skyrim tests Change-Id: I63d62b9957846dd761c83db9f58f9900f722be45 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263559 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* zephyr/test/skyrim: Refactor fan testRobert Zieba2023-02-224-5/+11
| | | | | | | | | | | | | | Move fan test to match new code structure. BRANCH=none BUG=b:247151116 TEST=Ran skyrim tests Change-Id: I0d243d0836b62526f73f89bce35d72e672833c27 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263558 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* zephyr/test/skyrim: Refactor alt charger testsRobert Zieba2023-02-224-5/+11
| | | | | | | | | | | | | | Refactor alt charger tests to match new code structure. BRANCH=none BUG=b:247151116 TEST=Ran skyrim tests Change-Id: I18b6c4bd01c6451172d8bceb66e1ade73a87634b Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263557 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* zephyr/test/skyrim: Refactor ppc_config testsRobert Zieba2023-02-227-15/+24
| | | | | | | | | | | | | | Move ppc_config tests to match new code structure. BRANCH=none BUG=b:247151116 TEST=Ran skyrim tests Change-Id: If6237b909a92b775006b9125eccf1b3c0bd341ee Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263556 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* zephyr/test/skyrim: Refactor baseboard codeRobert Zieba2023-02-223-1/+6
| | | | | | | | | | | | | | Move baseboard pd tests to match new code structure. BRANCH=none BUG=b:247151116 TEST=Ran tests Change-Id: I180b2681db3b526966dd9e16020dfe77b998c488 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263555 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* zephyr/test/skyrim: Refactor common codeRobert Zieba2023-02-223-1/+8
| | | | | | | | | | | | | | Move common code as the first step of a larger refactor. BRANCH=none BUG=b:247151116 TEST=Ran skyrim tests Change-Id: Ic527a71629d899e3f46463898373ded7314d9867 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263554 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Skyrim: Remove i2c transactions from interrupt contextDiana Z2023-02-221-2/+10
| | | | | | | | | | | | | | | | | | Calls to retrieve the status of GPIOs on the I/O expander require running i2c commands, which should not be run from the interrupt context. Instead, use a deferred call to schedule these to be processed. BRANCH=None BUG=b:268491130 TEST=on frostflow, ensure overcurrent tool no longer causes a watchdog reset Change-Id: Ia7e3bd673ddc5a995cb846a0807cfaebcd43d36b Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4277882 Tested-by: SamSP Liu <samsp_liu2@compal.corp-partner.google.com> Reviewed-by: Robert Zieba <robertzieba@google.com>
* osiris,volmar: disable TCPC VCONNBoris Mittelberg2023-02-222-4/+1
| | | | | | | | | | | | | | | | | Disable TCPC sourcing VCONN via SYV682. The CC pins on SYV682 are not 5V tolerant, use internal VCONN sourcing instead. BUG=b:180973460 BRANCH=none TEST=make buildall Change-Id: I5a852a998cfcef613c720e200b542e43eece9cd5 Signed-off-by: Boris Mittelberg <bmbm@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4279301 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org> Commit-Queue: YH Lin <yueherngl@chromium.org>
* mt8186,mt8188: force turning off PMIC at S3S5Eric Yilun Lin2023-02-222-96/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL ensures that before going to S5, the PMIC has turned off the power source to AP, and we can move SHUTDOWN_COMPLETE to S3S5. It did this by asserting EC_PMIC_EN_ODL at S3S5. For pressing button shutdown, the flow becomes: S0 -> hold powerkey 8 seconds -> S3 -> S3S5 -> hold EC_PMIC_EN_ODL for 8 seconds -> S5 -> G3 For the other shutdowns: S0 -> S3S5 -> hold EC_PMIC_EN_ODL for 8 seconds -> S5 -> G3 Also, the AP won't boot when it's turning off the PMIC (S3S5) until it goes to S5. BUG=b:242012415 b:267268982 TEST=On Steelix, Tentacruel and Geralt: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control dut-control power_key:8.2 Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control dut-control power_key:9.2 Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control dut-control power_key:tab Result: G3 -> S0 * Console command: apreset Result: S0 -> S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 * AP console: reboots Reulst: S0 -> S0 * AP console: poweroff Reulst: S0 -> G3 * Short power press to power-on: $ dut-control dut-control power_key:tab Result: G3 -> S0 BRANCH=none Change-Id: Iacaa3dbcdafd61b2f3371e2ba376ebdcf29659ff Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4269797 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* flash_ec: delay cold_reset releasing timeEric Yilun Lin2023-02-221-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using cold_reset (which was EC reset, and now changes to GSC reset), and not enough sleep time would cause a race condition of FW_UP_L and EC_RST. The booting sequence would be: 1. GSC_RESET on 2. EC_RESET on 2. FW_UP_L on 3. GSC_REST off 4. EC_RESET off 5. FW_UP_L off The race condition happens at the step 4 and step 5 if the EC reset released too lade. This causes an issue entering the EC flashing mode on the new Ti50 platforms. We extend the sleep time between FW_UP_L release and COLD_RESET release to 0.2, which should be sufficient by the data we measured. BUG=b:269182955 TEST=flash over ccd and servo_micro on hayato (cr50,ite), kingler (ti50, npcx), geralt (ti50, ite) BRANCH=none Change-Id: I5a8b5c30bc44779f03ec4ed95cb505e7aaf1a0f0 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4259125 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com>
* markarth: remove anx7483 redriver on typeC0 portLeila Lin2023-02-222-2/+10
| | | | | | | | | | | | | | | | TypeC0 port has no redriver, remove anx7483's setting. BRANCH=None BUG=b:269784092 TEST=Verify markarth typeC0 port can project Change-Id: Ib819ac3fd0f60956c7b08bbe8732f15cbd33a83d Signed-off-by: Leila Lin <leilacy_lin@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4273451 Commit-Queue: Chao Gui <chaogui@google.com> Tested-by: LeilaCY Lin <leilacy_lin@compal.corp-partner.google.com.test-google-a.com> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Remove CONFIG_HOST_EVENT64Tim Van Patten2023-02-218-36/+7
| | | | | | | | | | | | | | | | | | | The config option CONFIG_HOST_EVENT64 has been unconditionally enabled since 2017. This CL removes the option entirely, to clarify that 64 bit host event support is enabled by default. BRANCH=none BUG=b:261141172 TEST=Manually build and flash, verify device boots TEST=ectool version Change-Id: I806c12b8e69955dd19d32ad96587050fd189bea4 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4255275 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* Skyrim: Enable 4 byte postcodesDiana Z2023-02-211-0/+1
| | | | | | | | | | | | | | | | Set up the last CONFIG item needed for 4-byte post codes now that the upstream patch to support them better is in place. BRANCH=None BUG=b:259971621 TEST=on skyrim, boot and ensure 4-byte post codes are seen with no errors listed Change-Id: I9840e96c023f6afd4f15364dd61909a5d406f917 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4278261 Commit-Queue: Robert Zieba <robertzieba@google.com> Reviewed-by: Robert Zieba <robertzieba@google.com>
* Fan: print 'stalled' for rpm == 0xfffeDaisuke Nojiri2023-02-212-1/+6
| | | | | | | | | | | | | | | | | This patch makes 'ectool pwmgetfanrpm' print 'stalled' in case the EC returns 0xfffe. This value used to be used for the EC to indicate a stalled fan but has been deprecated. ectool needs to continue to support old ECs. BUG=b:269241655 BRANCH=None TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I252f35880859847b524857b6c2c44adb4b118b88 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4275601 Commit-Queue: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: Remove pd_dev_dump_infoAbe Levkoy2023-02-213-17/+1
| | | | | | | | | | | | | | | Remove the remnants of CMD_PD_DEV_DUMP_INFO from TCPMv2. The function that was left did not link when enabled. BUG=b:250015035 TEST=make buildall BRANCH=none Change-Id: I884bade638873d79dfcbc72bb5bf98d53f5afa78 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263563 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* voltorb: update the LED behavior according to new requirementJiahong Wei2023-02-211-84/+0
| | | | | | | | | | | | | | | | According to OEM new requirements, updates the behavior of LED lights in different states. BUG=b:269208753 BRANCH=corsola TEST=1. zmake build voltorb. 2. Verify LED light color base on specification. Change-Id: Ia435ec4a6c73e92dd5692e2295d991ba06c0d76a Signed-off-by: Jiahong Wei <weijiahong@huaqin.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4270696 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
* geralt: remove PLATFORM_EC_SHA256_UNROLLEDTing Shen2023-02-211-1/+0
| | | | | | | | | | | | | | | Use hw acceleration instead BUG=none TEST=zmake compare-builds geralt BRANCH=none Change-Id: I0ad567c2bbd9252bdb8ea23145502f79f152b8e7 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4274112 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* dibbi: Update EN_PPVAR_BJ_ADP_OD and its uses.Sam McNally2023-02-212-3/+3
| | | | | | | | | | | | | | It should be open-drain, and the logic has been inverted since the original definition. BUG=none TEST=none BRANCH=none Change-Id: I78092db8314baa512589a79bfe538fb4401f4cab Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4273905 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* dibbi: Change EC_RECOVERY_BTN_OD to active high.Sam McNally2023-02-212-2/+3
| | | | | | | | | | | | | | EC_RECOVERY_BTN_OD is active-high, so set the recovery button flags for this signal to BUTTON_FLAG_ACTIVE_HIGH. BUG=b:268309238 TEST=dibbi boots in normal mode BRANCH=none Change-Id: Id7f7e65e0e3a35097de4865a8578bd0b47aea5eb Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4240911 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* common/button.c: Support configuring recovery buttons as active high.Sam McNally2023-02-213-2/+14
| | | | | | | | | | | | | | | | | | | | | | Dedicated recovery buttons may be active high rather than the current default of active low. Add config options for specifying flags for dedicated recovery buttons following the style of power button flags. Since neither the power button flags config this is following, nor the dedicated recovery button configs themselves are surfaced to zephyr, add these dedicated recovery button flags configs to config_allowed.txt. While possible to add now, it would likely result in a non-functional implementation to be largely or entirely replaced when the first zephyr platform actually requires this functionality. BUG=b:268309238 TEST=none BRANCH=none Change-Id: Iba658735e87c20ace140a783c2a2242897baf8c1 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4240910 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* dibbi: Keep barrel-jack presence interrupts enabled.Sam McNally2023-02-211-2/+0
| | | | | | | | | | | BUG=b:269666578 TEST=none BRANCH=none Change-Id: Ie641fc103e6ff2fb31f73717599ebbfc80ad1e19 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4273626 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* dibbi: Set maximum PD input to 20V, 3.25A, 65W.Sam McNally2023-02-211-1/+5
| | | | | | | | | | | BUG=b:269666625 TEST=dibbi negotiates 65W BRANCH=none Change-Id: Ic26e683235b066ca12f02c4196a44e4bc237e7d0 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4273625 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* mt8186,mt8188: disable IN_AP_SUSPEND interrupt in G3/S5Eric Yilun Lin2023-02-211-12/+6
| | | | | | | | | | | | | | | | | | | GPIO_AP_IN_SLEEP_L will be floating when the AP off, so only enable the interrupt when AP is on. Also, drop the unnecessary interrupt enables, which should have done in power_common_init(). BUG=none TEST=AP suspend, and AP_IN_SLEEP_L is captured by the powerindebug BRANCH=none Change-Id: I496c2a4a0b7d7e2f18d8c14945f67d91878ac045 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4269796 Commit-Queue: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com>
* mt8186,mt8188: check IN_AP_RST signal when wachdog IRQ raisedEric Yilun Lin2023-02-211-5/+2
| | | | | | | | | | | | | | | | | Watchdog interrupt is only significant only when AP is on, which means the IN_AP_RST should not be asserted. BUG=b:242012415 TEST=stop daisydog; echo > /dev/watchdog; EC report AP_WACHDOG reset BRANCH=none LOW_COVERAGE_REASON=initial bringup Change-Id: I2af6fc6f61b909a31e542d86a5a43011cdb6afac Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3820873 Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip/stm32: ADC fixesJes B. Klinke2023-02-214-37/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ADC drivers for STM32L4 (and L5) seems to have significant flaws. The chip has the ability to continuously perform ADC conversions according to a set sequence of channels and bit depths. In addition to that, the chip can perform a one-off "injected" sequence of up to four channels, in response to a hardware or software trigger. The driver uses only a software triggered "injected" sequence to convert two pre-set channels. The code of `adc_read_channel()` has some odd properties, though. On first invocation, it sets up the injected sequence to consist of the two configured ADC channels. Each invocation takes one particular ADC channel number as input, but the code simply kicks of the sequence of two channels to read, and then returns the relevant of the two, discarding the other reading. The has the needless limitation that it cannot be used with more than two ADC channels. Since it is permitted to modify the list of channels in the injected sequence as long as no conversion is in progress, it would be more straightforward, if each invocation of `adc_read_channel()` would reconfigure the injected sequence to consist of a single channel, the one requested. This CL makes that change. BUG=b:269621551 TEST=Read and of a dozen ADC channels on HyperDebug Change-Id: I62387979faf494cfefc3b6e7dd1d9a1954017ae6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265223 Tested-by: Jes Klinke <jbk@chromium.org> Commit-Queue: Eric Yilun Lin <yllin@google.com> Auto-Submit: Jes Klinke <jbk@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* config: Update CONFIG_HOST_EVENT_REPORT_MASK to 64bTim Van Patten2023-02-201-4/+0
| | | | | | | | | | | | | | | | | | Update CONFIG_HOST_EVENT_REPORT_MASK to the 64 bit value. The config value CONFIG_HOST_EVENT64 is unconditionally enabled, but after CONFIG_HOST_EVENT_REPORT_MASK is defined. This updates the mask to fit with the rest of the EC code that has 64b host events enabled. BRANCH=none BUG=b:261141172 TEST=Manually build and flash, verify device boots TEST=ectool version Change-Id: I8ff662cc069d3b36cc7233c70fb1f2e685336036 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4261959 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* flash_fp_mcu: Dynamically determine gpiochip number for guybrushPatryk Duda2023-02-201-17/+16
| | | | | | | | | | | | | | | | | Guybrush-kernelnext uses upstream kernel which changes every week. In this case it's cumbersome to hardcode gpiochip number in the script and we should determine it dynamically. BUG=b:269985136 BRANCH=none TEST=Run `flash_fp_mcu --hello` on guybrush and guybrush-kernelnext Change-Id: Ia416b664fffdaf0dd9bf14e79da6fd6f4d9c05f0 Signed-off-by: Patryk Duda <pdk@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4271785 Commit-Queue: Patryk Duda <patrykd@google.com> Reviewed-by: Josie Nordrum <josienordrum@google.com> Tested-by: Patryk Duda <patrykd@google.com>
* flash_fp_mcu: Don't change GPIO direction to input on SkyrimPatryk Duda2023-02-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | If we change nRST (pin 780) GPIO direction to input, the value on that line will be 0, so FPMCU will be in reset until we reboot DUT. As a result flash_fp_mcu script could accidentally reset FPMCU while disabling sector write protection (first FPMCU boot with HW WP disabled). This will corrupt STM32 flash internal structures in a way that can be only recovered by flashing new firmware using internal bootloader (running flash_fp_mcu). BUG=b:253362456 BRANCH=none TEST=After running 'flash_fp_mcu --hello' execute 'echo "780" > /sys/class/gpio/export'. Make sure that: 'cat /sys/class/gpio/gpio780/direction' prints 'out' and 'cat /sys/class/gpio/gpio780/value' prints '1'. Change-Id: I42497bb01bff4a7fe5a1342c38d861284d5e4d68 Signed-off-by: Patryk Duda <pdk@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4264110 Reviewed-by: Andrea Grandi <agrandi@google.com> Commit-Queue: Patryk Duda <patrykd@google.com> Tested-by: Patryk Duda <patrykd@google.com>
* geralt: enable LEDTing Shen2023-02-201-88/+27
| | | | | | | | | | | | | | | | The board has only one LED with green and blue channel. Update DTS to reflect the hw implementation. BUG=b:269706760 TEST=`ectool led color (GREEN|BLUE)=1' BRANCH=none Change-Id: Ia5ee4fea2c60b055047a3572fe6662e1b3c4cfa5 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263850 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org>
* aurash: update EC related functionScott Chao2023-02-2015-586/+522
| | | | | | | | | | | | | | | | | | | | | - Support power on by HDMI/ DP monitor. - Remove third type-c port. - Update GPIO setting according to schematic. - Update power_monitor function according to aurash design. - Update ADC channel setting. - Update Barrel adapter to 90w and 135w. - Remove all fan related function. - Update thermal shutdown point from thermal team request. BUG=b:269212574 BRANCH=none TEST=make buildall Change-Id: Ic268884c9e633e65774394445ca24bcabf23614f Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4248461 Reviewed-by: Ricky Chang <rickytlchang@chromium.org> Commit-Queue: Ricky Chang <rickytlchang@chromium.org>
* Add unit test for EC_CMD_CHARGE_CURRENT_LIMIT v1Daisuke Nojiri2023-02-192-29/+89
| | | | | | | | | | | | | | This patch add unit test for EC_CMD_CHARGE_CURRENT_LIMIT v1. BUG=b:265372046,b:269725114 BRANCH=None TEST=make run-sbs_charging_v2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I1f1528f0017c30a1b24b1593b5355938d99ddd6e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263562 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Commit-Queue: Peter Marheine <pmarheine@chromium.org>
* binman: Add CBI section to fmapMadhurima Paruchuri2023-02-182-0/+12
| | | | | | | | | | | | | | | | | | | CBI section is added to fmap. The CBI section will be filled with 0xFF in binary. The size and offset could be overridden with device tree config in chip/program/project. A property named "preserve" is added, to determine the CBI portion should not be updated during flashing of chip. BRANCH=None BUG=b:266972341 TEST=dump_fmap <ec.bin location> && manually checking ec.bin content Change-Id: I43647285502917bf557b2fb4ce174c24538fb363 Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4253328 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* motion_sense: Log stats at suspend, resume, and shutdownDouglas Anderson2023-02-181-1/+33
| | | | | | | | | | | | | | | | | | | | If motion sense stops working it's very mysterious. Add some stats at key points in time to help figure out what could be going wrong. Prints look like: [58.816888 Motion pre-resume; loops 1280; last 12067 ms ago; a=0x7, s=0x111] BUG=b:267680317 TEST=See printouts at key times BRANCH=trogdor Change-Id: I4daa2d2a51ca8c3d560e13e4ad7fdc467c691913 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265366 Reviewed-by: Wai-Hong Tam <waihong@google.com> (cherry picked from commit daa98348b2d8d02dc2e9c67c2368e68631661e69) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4266201 Commit-Queue: Wai-Hong Tam <waihong@google.com>
* chip/stm32: Sample time off-by-oneJes B. Klinke2023-02-183-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32L4/5 ADCs use three bits to configure the time to sample the input voltage, that is the time during which an analog MUX conducts, allowing the internal holding capacitor to settle. The enums declared in adc_chip.h has eight usable values, plus an additional value called DEFAULT. It makes sense to have the DEFAULT be represented by a zero value, such that if a board.c file does not mention the sample_time field in its adc_t, then due to the C convention of data being zero-initialized, the code can detect it and apply a sensible default. However, the body of adc_configure() has no such logic, but takes the raw enum value and attempts to stuff it into a 3-bit field, which will be off by one, and overrun for the largest enum value of 8. Also, I find the term "sample rate" misleading, as it implies a continuous process. This sample time setting applies equally to one-off injected conversions, as it refers to the duration of the sampling of the input signal, before conversion begins, not a rate of conversions happening. BUG=b:269621551 TEST=Made measurements with the longest same time setting Change-Id: Id8d297fcec883565dea1e09d6bbbfa1ab564778d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265222 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Jes Klinke <jbk@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org>
* isl9241: Prevent isl9241_nvdc_to_bypass from locking control3 mutex twiceDaisuke Nojiri2023-02-181-7/+18
| | | | | | | | | | | | | | | | | | | isl9241_nvdc_to_bypass locks control3 mutex and calls isl9241_get_vsys_voltage, which tries to lock the same mutex. This deadlocks whatever task calling isl9241_nvdc_to_bypass. This patch makes isl9241_nvdc_to_bypass call an internal version of isl9241_get_vsys_voltage, which skips mutex lock. BUG=b:266742386 BRANCH=None TEST=Agah Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I690dd0011f05f7488be6566146b7863bf747d9e6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4261958 Reviewed-by: Jes Klinke <jbk@chromium.org> Tested-by: Jes Klinke <jbk@chromium.org>
* chip/stm32: Add warnings in stm32l4 files also used by L5Jes B. Klinke2023-02-172-0/+4
| | | | | | | | | | | | | | | | | | In several cases, the L4 and L5 series can use the same driver, which is different from other STM32Lx chips. This CL introduce a warning at the top of such files, alerting readers to the fact that they are also used by L5 despite this not being apparent from the file name. BUG=b:269621551 TEST=none Change-Id: I6edff6c0aea57ea9679729db20a292d75b4b8df0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4264176 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org> Tested-by: Jes Klinke <jbk@chromium.org>
* chip/stm32: ADC status register "write 1 to clear"Jes B. Klinke2023-02-171-2/+9
| | | | | | | | | | | | | | | | The convention of the STM32_ADC1_ISR register is that writing a 1 to any bit clears that one latched interrupt status bit. Existing code wrongly uses |= on this register, effectively clearing every latched bit in the register, not merely the intended one. BUG=b:269621551 TEST=Observe ADC conversions on HyperDebug Change-Id: Ia9fe3f6ca6f2f67614628b23bc7ba2e3a3caf058 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265221 Tested-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org>
* chip/stm32: Extend ADC support to L5xx familyJes B. Klinke2023-02-174-6/+12
| | | | | | | | | | | | | | | | | The L5 family has basically the same ADC component as L4. L5 does not have ADC3, but that happened to not be used by the stm32l4.c, so the existing implementation can be used without modification. BUG=b:269621551 TEST=Observe ADC conversions on HyperDebug Change-Id: I4ce279dca3ff23ae2a9d2f00c23399732eecf15f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265220 Tested-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org>
* skyrim/usbc_config: Ensure that type-A ports are powered after TCPC resetRobert Zieba2023-02-171-0/+13
| | | | | | | | | | | | | | | | | | The GPIO restore code in `reset_nct38xx_port` can disable vbus supply to the type-A port if the device transitions to S0 during the function call. Add code to ensure vbus is supplied to the type-A port if we're in S0. BRANCH=none BUG=b:265709281 TEST=ODM verified on frostflow device Change-Id: I2f4d58801ebbc7c1e5f350a3917e7e2dcc6b5d61 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4250037 Tested-by: SamSP Liu <samsp_liu2@compal.corp-partner.google.com> Commit-Queue: Chao Gui <chaogui@google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* i8042: return self-test status on resetBoris Mittelberg2023-02-172-3/+15
| | | | | | | | | | | | | | | | | As described in PS/2 keyboard protocol spec, the reset command 0xff is followed by diagnostic self-test, aka BAT. Along with the ACK for reset command EC must return BAT status. BRANCH=none BUG=b:134366527 TEST=buildall; make run-kb_8042; depthcharge screen on brya Change-Id: I5803d06b204d552c458ad443393f80072d41e40e Signed-off-by: Boris Mittelberg <bmbm@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4252007 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: Raul Rangel <rrangel@chromium.org>
* motion_sense: Add printf on set_data_rate() errorGwendal Grignou2023-02-171-6/+7
| | | | | | | | | | | | | | To validate the sensors are not responsive on coming back from S5 on Lazor, print ODR setting information, even on error. BUG=b:267680317 TEST=compile BRANCH=trogdor Change-Id: If5c9e87cfc0f4ee49f6276b6ffd78cd9168ed6f0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4255277 Reviewed-by: Douglas Anderson <dianders@chromium.org>
* zephyr: de-clang-format a bunch of enums and initsFabio Baltieri2023-02-1719-112/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | Usually clang-format works great, but it gets really confused by macros that include a comma termination in their definition. In those situation it tends to add unnecessary indentation and makes it more confusing to understand that the statements on different lines are actually doing the same thing. Don't think there's a good way of configuring the tool to do that properly, and frankly it's probably fine to indent few weird code snippets manually. This fixes a bunch of enums and initialization code that had unusual indentation by shutting clang off for the block and indenting manually BRANCH=none BUG=none TEST=zmake compare-builds -a Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com> Change-Id: Ic923b27c2ed9f66a2858bfa12e63838f1538700d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4264115 Tested-by: Fabio Baltieri <fabiobaltieri@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Fabio Baltieri <fabiobaltieri@google.com>
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