| Commit message (Collapse) | Author | Age | Files | Lines |
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BUG=chromium-os:31902
TEST=manual
1. reboot ec
2. port80; nothing there
3. powerbtn
4. retype port80 repeatedly during boot and see it fill and then scroll
Change-Id: Id227d5debbdd635332ed2f42bc0f163833031b5c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25442
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This test checks the sanity of timer value when jumping between images.
BUG=chrome-os-partner:9188
TEST=Test passed
Change-Id: If264e28e4ceec6ddb8325f3496825a40e7a038d8
Reviewed-on: https://gerrit.chromium.org/gerrit/25371
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
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For particularly nasty errors the stack or stack pointer may be corrupt,
or in a place that we do not want overwritten. Provide and option to
place the stack in a fresh place, assuming you can reach exception_panic().
Note that exception_panic() does not write anything to stack itself.
BUG=chrome-os-partner:10146
TEST=manual:
build for all boards
On snow, cause a panic and see that it is reported correctly.
Change-Id: I21d8b9bb12455758309d54ef20de66640d8a2df6
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24504
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Rather than just reset with no information when we hit a watchdog, try
to anticipate the problem and display a trace message as on lm4.
This solution is not ideal since we must constantly reset the WWDG to make
it work. It may be better to look at dedicating a timer to this purpose
instead, since we are really just shadowing the IWDG and don't actually
need the reset functionality.
One problem is that we now have a fairly short time limit on many
operations, since if we can't service an interrupt within about 30ms then
the WWDG will reset the system.
It also affects JTAG since it seems that the watchdog goes off the first
time JTAG is invoked to program the flash. The solution here is to retry.
For these reasons it is implemented as an option, CONFIG_WATCHDOG_HELP.
BUG=chrome-os-partner:10145
TEST=manual:
build for all boards
On snow:
> waitms 500
See that there is no message
> waitms 1300
Time: 0x0000000000733ba3 us
Deadline: 0x00000000006b6db2 -> -0.511473 s from now
Active timers:
Task Ready Name Events Time (s)
0 R << idle >> 00000000 0.000000
1 R WATCHDOG 80000000 0.000000
2 KEYSCAN 00000000 0.000000
3 GAIAPOWER 00000000 0.000000
4 R CONSOLE 00000000 0.000000
5 HOSTCMD 00000000 0.000000
--- UART initialized after reboot ---
[Reset cause: watchdog]
[Image: RO, snow_v1.1.32-8c00326-dirty 2012-06-03 07:54:29 sjg@sglass.mtv.corp.google.com]
done
Change-Id: I042fcc9ecd9c21210ea3826ca69c943aab949d1f
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24398
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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We want this function to be available for all chips, so move it into a
generic place.
The task_disable_irq() from the LM4 version can be left in
watchdog_check(), to keep the watchdog_trace() function generic.
BUG=chrome-os-partner:10145
TEST=build for all boards
Change-Id: I98c60ce5958f1498b84a233ef04290a68a7838c5
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24397
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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(And maybe other keyboard status in the future...)
BUG=chrome-os-partner:10358
TEST=manual
reboot
kbd -> should show disabled
power on system, wait for it to boot
ctrl+alt+F2 -> should be able to type at console
kbd -> should show enabled
kbd disable -> should no longer be able to type at console
kbd enable -> should again be able to type at console
Change-Id: Icdb38b09f318a47b0413609294b44cd810e8f389
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25353
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
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The SCB registers are defined in the ARMv7-M architecture, so they are
common to all chips.
We will need System Control Register (SCR aka SYSCTRL) to implement
power management on stm32.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=snow
Change-Id: I35c283731306541b3d21398c96fdca89954fe20a
Reviewed-on: https://gerrit.chromium.org/gerrit/25392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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When we need to mock modules in a unit test, we need a way to mock
the actual modules. This CL enables mock of given source files.
For example, if we need to mock watchdog for test 'foo', we can add to
test/build.mk: "core-mock-foo-watchdog.o=fake_watchdog.o", and then
implement its own watchdog in fake_watchdog.c.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:10356
TEST=Set a mock fake_watchdog.c and check the test is compiled with
fake_watchdog.c instead of watchdog.c.
Change-Id: I4a0afb589a49dad7c4d6faf8926438085cdc46cf
Reviewed-on: https://gerrit.chromium.org/gerrit/24942
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
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The current delay is set to 0 second, which causes unexpected shut down
whenever we get an erroneous value. Since 2 seconds is short enough for
EC to respond to CPU overheating event, let's lengthen it to 2 seconds to
prevent this.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:10382
TEST=none
Change-Id: I7f971108943d74310b69b97c5f082fb2478f273b
Reviewed-on: https://gerrit.chromium.org/gerrit/25186
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
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No code changes, just rearranging source in preparation for an
experiment to see how much the binary shrinks if we disable the
interactive console.
BUG=none
TEST=none
Change-Id: Ie21f1b3dcd04272e80fd40b2ed54d1eaf7fb1cdf
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25232
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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Note that util/comm-lpc.c already does this for the host side of the
commnunication.
BUG=chrome-os-partner:10444
TEST=none; all EC responses are currently well-formed
(but do try 'ectool hello' from host and make sure it still works)
Change-Id: I731ed326e281be6a7435edfa03c783225e105b72
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25124
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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Previously, the host could write to this space and corrupt the memmap data.
BUG=chrome-os-partner:10210
TEST=manual
From a root shell:
localhost ~ # io_read32 0x960
0x574e5553
localhost ~ # io_write32 0x960 0x1234
localhost ~ # io_read32 0x960
0x574e5553
That verifies that the EC is rejecting host writes on the memmap range
localhost ~ # ectool hello
EC says hello!
That verifies the host is still able to write to the user param range
Change-Id: I8c29571f439a14f308ed73f4c641264e17f944e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25115
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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This bug unexpectedly comes from 2 related features:
1. Issue chrome-os-partner:7486: stop driving keyboard columns ASAP when
power button is pressed. This is to avoid the keys on ESC column to
reset the system if the power button is also pressed. This is done by
keyboard_enable_scanning(0) in power_button_interrupt().
2. During the booting, the power button state is set to BOOT_RECOVERY and
will ignore the power button release (to avoid confusing the host).
However, before the state is set back to IDLE, the
power_button_interrupt() can be triggered ever so that the matrix scan
is disabled.
Therefore, we have to enable the matrix scan in the BOOT_RECOVERY (and
the derived EAT_RELEASE) because they ignore power button release.
Note that in the regular states, the power_button_released() is called
after debounce time. They are fine.
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
BUG=chrome-os-partner:10358
TEST=Press ESC+Refresh+Power for many many times with vatious hold time.
The tab key works to disable the recovery reason.
Change-Id: Ic05fc6e22caadb4a3892a4b201dd5bfc7e9c3f44
Reviewed-on: https://gerrit.chromium.org/gerrit/24991
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
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Move the implementation of panic into C code. Only a very small part
needs to be in assembler, and the reset is easier to maintain as C.
As part of this, define panic_putc() and panic_puts() which directly
wite to the UART.
To make things more convenience for the future, add a simple printf()
implementation in the panic path. This is not reliant on the uart
buffering system being in a happy state. However, we do call the
emergency flush so that our panic message will appear after previous
output rather that surpressing it (which would be extremely confusing).
Code/data size for panic.o grows by about 200 bytes, but this is mostly
due to the increased flexibility.
text data bss dec hex filename
292 272 0 564 234 old panic.S
692 3 48 743 2e7 new panic.c
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow:
> rw 0x06000000
=== EXCEPTION: 03 ====== xPSR: 01000000 ===========
r0 :0000000b r1 :00000047 r2 :06000000 r3 :200013dd
r4 :00000000 r5 :080052cc r6 :200013d0 r7 :00000002
r8 :00000000 r9 :200013de r10:00000000 r11:00000000
r12:00000000 sp :200009a0 lr :08002a5d pc :08003962
Rebooting...
Change-Id: If3e3f572e0f32af780b6ebda235b1b3cde4de5e4
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24503
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Add the minimal amount of stubs (namely MOSCCTL, UARTCC and FLASH_FMPPEx
registers) to the emulation to be able to boot link EC firmware and
pass OS tests.
the QEMU binary is generated from the chromeos-ec-0.15.1 sandbox of the
chromium.org qemu.git repository at hash 1a48940.
I will add next better GPIO control and default states to ensure we are
booting the proper mode.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:10240
TEST=make qemu-tests BOARD=link
./util/run_qemu_test -b link
Change-Id: I3d7b9247628133289e0ef04bb7d85c7438b6ed81
Reviewed-on: https://gerrit.chromium.org/gerrit/24880
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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BUG=none
TEST=none
Change-Id: I00ac033d36a8472007ea66a4aebde003970cd1a2
Signed-off-by: Luigi Semenzato <semenzato@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24878
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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BUG=none
TEST=none
Change-Id: I54f24672dd8294b17bae1de4eae2f2791c73998d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24855
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Perviously we have a 10-second delay for all temperature sensor. This is
not suitable for CPU temperature. Let's change that to have an option to
set the delay length for each temperature sensor. And also shorten the
delay of TMP006 sensor to 7 seconds, that of EC internal temperature to
4 seconds, and that of PECI CPU temperature to 0 second.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:10233
TEST=Check EC issued warning as soon as CPU temperature reached the
threshold.
(cherry picked from commit cf24df7f3ee24eaa5dbeae3b304d11ddada9a914)
Change-Id: Id2cc4a437bde15697afe4020b6153e5d13466759
Reviewed-on: https://gerrit.chromium.org/gerrit/24694
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
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Any command/data coming from host will be placed in from_host queue, and
the interrupt handler returns immediately. The i8042_command_task() will
handle them later.
Data reply to the host will be protected by the mutex.
BUG=chrome-os-partner:10090
TEST=randomly play around on the link board.
Change-Id: Ic19d5abd1abf8dc261ddaad4224cd9305c2f36a4
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24299
Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
Reviewed-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
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- update strings which were modified by the message text "compression"
- updated QEMU which supports a couple of additional registers for LM4F
(getting internal oscillator calibration status and writing timer
counter through TAV)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:10008
TEST=make qemu-tests
Change-Id: Idf0ee13f354b4e14405e949861d426f3e4c3022b
Reviewed-on: https://gerrit.chromium.org/gerrit/24827
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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When recovery is required, it will be because there's either a hardware pin
pulled somewhere, or because the recovery_reason is set in NVRAM. Coreboot
and U-Boot can see both of those, so the EC shouldn't make up a new reason.
If it does, it changes the original cause.
BUG=chrome-os-partner:9706
TEST=manual
Reset the EC using ESC+Power (Refresh+Power on EVT). At a root shell, run
crossystem recovery_request=11
reboot
When you see the Recovery screen, press TAB. It should say
recovery_reason: 0x0b We have no idea what this means
Prior to this fix, you'd see recovery_reason 2 instead, which is wrong.
Change-Id: Ie54185471927e7e829962d30bba9d142d593088f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24152
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Off-by-one is not my friend.
BUG=chrome-os-partner:10206
TEST=manual
1. rw 0x20000000
2. ww back the same number printed
3. rw 0x20000000. should match
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I61e0d26cf4cb274a88326d4e7d24ff1c82d6e515
Reviewed-on: https://gerrit.chromium.org/gerrit/24756
Reviewed-by: Simon Glass <sjg@chromium.org>
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When kb_fifo_start is 0, the index calculation yields -1 because C got
the mod (%) operation arguably wrong. By adding KB_FIFO_DEPTH to the
index before computing the mod with respect to KB_FIFO_DEPTH, we avoid
the negative case and (obviously) produce the same result in all other
cases.
BUG=chrome-os-partner:10247
TEST=saw incorrect state from kernel log before fix: could not repro after.
Signed-off-by: Luigi Semenzato <semenzato@chromium.org>
Change-Id: I3a30c229dc9f762dd45203e842128811a24cf53f
Reviewed-on: https://gerrit.chromium.org/gerrit/24730
Tested-by: Luigi Semenzato <semenzato@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Luigi Semenzato <semenzato@google.com>
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Some terminals do not generate backspace correctly, so accept delete
as a substitute.
BUG=chrome-os-partner:10147
TEST=manual:
ssh into workstation, then telnet to serial port (with ser2net running)
See that the backspace key now works correctly, instead of injecting
strange characters into the terminal.
Change-Id: Ief6f2bcab9b8e82cb5720d18c596326b49ffc336
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24715
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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We were going straight to S5. When the PCH first goes into S5 after
power-loss, it decides to boot for some reason. So, stay in G3.
Still exit G3 if waking from hibernate or if the power button is
pressed when the EC boots on a power-on reset.
BUG=chrome-os-partner:10239
TEST=manual
1) Unplug battery and AC power. Plug in AC power. System does not boot.
2) Press power button. System boots now.
3) From console, 'hibernate 10'. Close and open lid. System boots.
4) From console, 'hibernate 10'. Press power button. System boots.
5) Hold power+esc+refresh. System boots into recovery.
6) Hold power+esc. EC reboots. Release esc. System stays off.
7) Unplug battery and AC power. Plug in AC power while holding power button.
System boots.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I7612a40ab5ebe41d356ac3a6b89cedf1174125f4
Reviewed-on: https://gerrit.chromium.org/gerrit/24729
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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EVT uses power+refresh as the Silego combination not power+esc, so
holding down power+esc+D wouldn't turn on the fake dev switch, and
holding down power+refresh+D wouldn't either because on a short enough
tap the EC would measure refresh as still held down.
BUG=chrome-os-partner:10210
TEST=manual
1) hold down reset combo + D -> turns on fake dev mode
2) hold down reset combo + F -> turns off fake dev mode
Change-Id: I85b51d3684500ae821513e71a2cd01aa4fcf5e8f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24646
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Should be no functional changes; this is just rearranging code.
BUG=none
TEST=boot system and type on console; should still work
Change-Id: I1c0d44db2d32048b1aaf458728b887b4a008c8cd
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24644
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BUG=chrome-os-partner:10209
TEST=boot system and type on console; should still work
Change-Id: I9f89420acd59947baee445fc2a655857809f8fb9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24636
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BUG=chrome-os-partner:9495
TEST=manual
Build image, run dump_fmap. Look for those entries.
Change-Id: I6dfc38e00ce1e11ea24c8392d1691fab32a59d1f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24696
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Also add snprintf(), and %X format code.
BUG=chrome-os-partner:10206
TEST=timerinfo; should print correctly. 'ectool battery' on host side should print same serial as 'battery' on EC console.
Change-Id: I5c9f69d1a20ee5d0a59440c122655adbf62c9aea
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24635
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
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Since they're not used outside of this source file.
BUG=none
TEST=if it builds, it worked
Change-Id: I92c13c7d58e0e6977c2696746c9d95cbdcb6dbd5
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24638
Reviewed-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
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BUG=chrome-os-partner:10205
TEST=boot system; still works
Change-Id: I05808068954af40ef8d259e5dc5c94324e8e256d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24621
Reviewed-by: Simon Glass <sjg@chromium.org>
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BUG=chrome-os-partner:10194
TEST=manual
Run "powerinfo" at the EC console.
Change-Id: I4c8fe8bc32ae6600bd8f0729e81bd239198c73fc
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24578
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Some things about watchdogs are common across Cortex-M3, so create a
common watchdog file to hold these. Put the watchdog task in there as
the first customer.
BUG=chrome-os-partner:10145
TEST=build for all boards
Change-Id: Id55f71a807ee12bae3758afc213c30c731eadc07
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24395
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Use the same prototype for watchdog_init() everywhere. One version takes
a parameters and one doesn't. We don't need the parameter since we have
a #define. Tidy this up.
Also move watchdog defines into watchdog.h.
BUG=chrome-os-partner:10145
TEST=build for all boards
Change-Id: I38ae63d7cc137b93017c850e767703d5f90f56ad
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24394
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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We don't really need this, and want to free up the LED for other
debugging uses, so drop it.
BUG=chrome-os-partner:10145
TEST=build and boot on snow (for want of a better test)
Change-Id: I62aad38e9b29556dde0a3bf8e10a85df577a8e73
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Keyboard recovery used to persist until the next time the EC was
reset. It should release the next time the user turns on the system
via the lid or power button.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:10034
TEST=manual
1. power system on normally. not in recovery.
2. press Power+Esc+Refresh. System turns on into recovery.
3. shut system down
4. power system on with lid-open. System boots normally.
5. repeat steps 2-3, then power system on with power button. System boots normally.
Change-Id: I455c7191d128614629c50ba27d7ef977e414fe90
Reviewed-on: https://gerrit.chromium.org/gerrit/24409
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:10132
TEST=manual
Connect uart console to Daisy, boot and remove the battery.
The I2C debug trace should not show up by default.
Change-Id: I911923138cb233cf2897983997c4a4764a62981b
Reviewed-on: https://gerrit.chromium.org/gerrit/24363
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
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This causes the reboot command to respond to the host via I2C with
EC_RES_SUCCESS.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
TEST=tested on Snow and Link using ectool and flashrom
Both machines were able to reboot the EC and go thru an EC update via
Flashrom successfully:
localhost ~ # ectool reboot_ec RO ; echo $?
done.
0
Flashrom is also able to do a fully automatic update, without the
user specifying a layout:
Reading old contents from flash chip... done.
Found 'RO_SECTION' in image.
Found 'RW_SECTION_A' in image.
GEC is jumping to [RO_SECTION]
GEC has jumped to [RO_SECTION]
Erasing and writing flash chip...
...
GEC is jumping to [RW_SECTION_A]
GEC has jumped to [RW_SECTION_A]
GEC needs 2nd pass.
...
Change-Id: Id723c26caa8f352a7ddc6ebfae664448c38300f0
Reviewed-on: https://gerrit.chromium.org/gerrit/24290
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
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- throw away all the incoming garbage after a NACK to be protect against
unexpected behavior on the embedded monitor.
- increase the command timeout :
on STM32F100, I have measured up to 1.4s to execute the erase 64kB
command. With the current 2s timeout, it was failing when you are
unlucky (since it's using a integer second timestamp to measure the
timeout).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=with a Snow, flash the board using stm32mon -w ec.bin
from various states.
Change-Id: I260b3b1311eac9be7c43f835eeac68051befd24a
Reviewed-on: https://gerrit.chromium.org/gerrit/24314
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
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We need to be able to toggle these signals to increase test coverage.
BUG=chrome-os-partner:9967
TEST=Toggle 'ectool wireless' and see GPIO signal changes.
'ectool backlight 0' and see LCD backlight turn off.
Change-Id: Ic96fe26aa82c33b0e51e1f973280a0edc322f158
Reviewed-on: https://gerrit.chromium.org/gerrit/23625
Commit-Ready: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
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This produces a host binary running on the application processor and
which is able to re-flash th EC firmware over the AP-to-EC link (either
LPC or I2C).
The payload (ie the EC firmware) to use is embedded inside the flasher
binary.
This is just aimed at testing and developer upgrade. The auto-update
flow is using flashrom.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=build for link/daisy/snow/bds and tests
On Snow, run burn_my_ec from the serial console and see that the EC was
correctly re-flashed.
Change-Id: I7f90e773678a7ef3d8dc6dbacf54e80f3294607b
Reviewed-on: https://gerrit.chromium.org/gerrit/24236
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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Const- and static-ifying data and pointers.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=kblog on, then boot system, then kblog; should print log
Change-Id: I2e1da8e3d614b66dad8749b18c43bd77dc75928d
Reviewed-on: https://gerrit.chromium.org/gerrit/24233
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:10042
TEST=boot system, ctrl+alt+F2, type on console; shouldn't crash
Change-Id: I935bc141fbbc1e7d0d073f1754104808a24fe869
Reviewed-on: https://gerrit.chromium.org/gerrit/24232
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=none
TEST=none
Change-Id: I369522c00724c959d1eac18ca9c3ce57bd55aeff
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This is an initial commit of tps65090 pmu driver. An empty charging
task added.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:9756
TEST=manual
When connected to a battery, the EC uart console will display
battery status on value change.
Check pmu register with 'i2c r 0x90 4'. Output should be '0x03'.
Change-Id: I99e243d203c438751af0c3647556cbf9a94e928f
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A polling mode I2C master driver. Interfaces for read/write byte
and word are implemented. i2c_read_string() is currently an empty
function.
CONFIG_SMART_BATTERY added to daisy board for testing.
Move smart_battery.o back to CONFIG_SMART_BATTERY since it is not
depended on charging state machine.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:9724
TEST=manual/host commands
> battery
Temp: 0x0bad = 298.9 K (25.8 C)
Manuf:
Device:
Chem:
Serial: 0x0001
V: 0x1cb7 = 7351 mV
V-desired: 0x20d0 = 8400 mV
V-design: 0x1c20 = 7200 mV
I: 0x0000 = 0 mA
I-desired: 0x0bb8 = 3000 mA
Mode: 0x6001
Charge: 49 %
Abs: 47 %
Remaining: 2705 mAh
Cap-full: 5575 mAh
Design: 5800 mAh
Time-full: 0h:0
Empty: 0h:0
Change-Id: I9f4e9e8819955ad1b107fb3b70ac2559d9b02b55
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Check if ESC+Power+Refresh is pressed at startup, if the recovery
combination is detected, record it to allow U-Boot to go into recovery.
The status of the keyboard recovery can be read from the response of the
EC_CMD_MKBP_INFO command.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9916
TEST=On Snow, do a recovery reset by pressing ESC+Refresh+Power and see
the trace, try other resets and don't see it.
Change-Id: I0e1a8214781a6e74bd90bf8313887a9dcf4df56d
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This sets the PMIC_PWRON_L signal to correspond with the keyboard
power button state.
BUG=chrome-os-partner:9821
TEST=Tested on Lucas (see notes below)
Signed-off-by: David Hendricks <dhendrix@chromium.org>
1. AC power plugged in, AP off, EC booted
> gpioget PMIC_PWRON_L
1* PMIC_PWRON_L
2. AP running, press and release power button (should see screen zoom
out and then back in, but I don't have a monitor...)
2a. AP running, power button not pressed
> gpioget PMIC_PWRON_L
1 PMIC_PWRON_L
2b. Press power button
> Waiting for long power press 280507864
> gpioget PMIC_PWRON_L
0* PMIC_PWRON_L
2c. release power button before 8s
> Cancel power off
> gpioget PMIC_PWRON_L
1* PMIC_PWRON_L
3. From AP off state, press and hold keyboard power button
> gpioget PMIC_PWRON_L
0* PMIC_PWRON_L
After 8s, we see:
Timeout waiting for GPIO 0/KB_PWR_ON_L
Power button was not released in time
Shutdown complete.
4. AP on, press and hold keyboard power button
> gpioget PMIC_PWRON_L
1 PMIC_PWRON_L
> Waiting for long power press 654024769
> gpioget PMIC_PWRON_L
0* PMIC_PWRON_L
> Power off after long press now=654025073, 0
ending loop 2
Shutdown complete. <-- Note: This message comes from power_off() which
also de-asserts PMIC_PWRON_L
> gpioget PMIC_PWRON_L
1* PMIC_PWRON_L
Change-Id: I6955771707ecea2926570be0e8bd77ebddbca4d4
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