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* accel: clapper: glimmer: Add support for accelerometer interrupt.stabilize-5696.BAlec Berg2014-03-267-9/+184
| | | | | | | | | | | | | | | | | | | | | | | | | Adding in support for accelerometer interrupt for use currently in clapper and glimmer. This is disabled by default and can be enabled with CONFIG_ACCEL_INTERRUPTS. BUG=none BRANCH=rambi TEST=Manual test on a glimmer using accelint console command. On console enter: accelint 0 32 When you tap the lid, it should fire the interrupt and print msg to console. accelint 1 32 Tap the base and it will fire another interrupt. Change-Id: Iaab324945e34d527140399ec4f06efd812a62840 Original-Change-Id: I0329112fdcae3c8adc0ca07e74fef7a591d4b9a1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190099 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191549
* accel: glimmer: Fixed sign of accel z-axisAlec Berg2014-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The accelerometer calibration routine came up with the wrong sign for the z-axis. Fixed that bug and flipped the sign for glimmer in the standard reference frame rotation matrix. BUG=none BRANCH=rambi TEST=Tested on a glimmer. Ran calibration routine and then verified that if the unit is sitting flat on a table with lid open to 90, the accelometer data send to host should read: base = 0, 0, 1024 lid = -1024, 0, 0 When the laptop is closed and flipped over, the data should read: base = 0, 0, -1024 lid = 0, 0, -1024 Change-Id: I1e8bcda26c16496d9cb49dece12db0c4ea929ece Original-Change-Id: If3bb7a095e400f5a247fab64b0050a44f4947e6c Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190400 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191579 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Use a special task event for ADC conversionsChromeOS Developer2014-03-262-6/+19
| | | | | | | | | | | | | | | | | This prevents other task events from continuing the ADC conversion prematurely; potentially leading to a panic if the conversion interrupt occurs after the ADC has been powered down. BUG=chrome-os-partner:26919 BRANCH=rambi TEST=Perform ADC conversions while running a deferred function calling itself on a 10mSec delay. Verify no panics after ~6 hours. Change-Id: Ic3894849c154b3f058e812b2da816e7cffb12cbf Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191302 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Update i2c handler to use task_wait_event_maskChromeOS Developer2014-03-261-25/+1
| | | | | | | | | | | BUG=chrome-os-partner:27180 BRANCH=rambi TEST=Verify i2c devices are still working (battery, charger) Change-Id: I9dc70454df35be9c9be3d9020c8dc3b760de5e07 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191301 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cortex-m: Add task_wait_event_mask() helper functionChromeOS Developer2014-03-262-1/+49
| | | | | | | | | | | | | BUG=chrome-os-partner:27180 BRANCH=rambi TEST=Tested indirectly via subsequent patches to use this call in the adc and i2c handlers for the lm4. Change-Id: I53501fdf47d606ea6c7705facb66e945e25d9745 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191300 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cortex-m: Add debug config option for disabling buffered writesChromeOS Developer2014-03-262-0/+19
| | | | | | | | | | | | | | | This can be helpful when debugging "Imprecise" data bus errors. BUG=None BRANCH=None TEST=Write to a memory-mapped register such as LM4_ADC_ADCISC for a hardware block that is powered down. Check the exception trace for a "Precise" error. Change-Id: Ia246c3661b482e212bb0ce37b9c2d383021de639 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191392 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* test: fix scratchpad testing on targetVincent Palatin2014-03-261-2/+2
| | | | | | | | | | | | | | | | | | | | | On STM32, the scratchpad size is limited to the 16 LSB (due to a limitation on STM32F100). Let's adapt the test to pass also on those targets. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run "utils" test on STM32 Discovery board. Change-Id: I04e9ae39b38afa14e4e72faa0e544c991c9ec1df Reviewed-on: https://chromium-review.googlesource.com/189152 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191513 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* 8042: Add typematic support for non-matrixed buttonsChromeOS Developer2014-03-251-17/+59
| | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:24956 BRANCH=ToT TEST=Using evtest, verify off-keyboard buttons now send repeat codes while held down. Verify power button does not send repeat codes. Verify keyboard keys still send repeat codes as before. Original-Change-Id: I873548181cdfa40d8e8929a6538c0ecd5ed8e92c Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187938 Reviewed-by: Randall Spangler <rspangler@chromium.org> Conflicts: common/keyboard_8042.c Change-Id: Ie7c7a1064cf45083f4707580f4ffc4d364035df9 Reviewed-on: https://chromium-review.googlesource.com/191312 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dave Parker <dparker@chromium.org> Tested-by: Dave Parker <dparker@chromium.org>
* rambi: EC take control on charger to make sure charge batteryKein Yuan2014-03-251-0/+24
| | | | | | | | | | | | | | | | | in non-S0 states when work with DPTF. If user sleeps/shutdown system when on battery(or when TCHG is throttled), system will never charge while in S3 or S5. BUG=chrome-os-partner:355015 BRANCH=rambi TEST=with the same test system will charge in S3 or S5. Change-Id: Idc68b2f533da0a55ad07d0ff8e3e5294c1e2143c Signed-off-by: Kein Yuan <kein.yuan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/191153 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: add more register definitionsVincent Palatin2014-03-231-4/+220
| | | | | | | | | | | | | | | | add detailed registers for DAC, COMP, RI and CRC. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: Ib456d1fbc72c2f6c658ea96e5a3ab72035b33ed2 Reviewed-on: https://chromium-review.googlesource.com/189864 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Add a charger boardVincent Palatin2014-03-236-0/+343
| | | | | | | | | | | | | | | | | | | | Using minimal runtime to fit the charger flash and RAM size. It is currently more an experiment than the final layout written in the stone. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run on STM32F051 Discovery with limited RAM and Flash to mimic STM32F031. Change-Id: I10ee1decfd1f1448edbc909f0e997367921c4b53 Reviewed-on: https://chromium-review.googlesource.com/189405 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Blaze: Configure board to use CHARGER_V1stabilize-5680.BChromeOS Developer2014-03-221-0/+1
| | | | | | | | | | | | | Looks like this board just missed a change to temporarily fork the charger code while it is being refactored. BUG=None BRANCH=nyan,blaze TEST=make -j BOARD=blaze Change-Id: I4ca630cc5210486928fbeda9af3e9c11ddbc8daa Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191214
* Add initial blaze supportNeil Chen2014-03-226-1/+518
| | | | | | | | | | | | | | | once firmware branch exists, this commit need go into it and doesn't need to be carried in master forever BRANCH=blaze BUG=chrome-os-partner:27120 TEST=USE="nyan_blaze" emerge-nyan_blaze chromeos-ec;flash nyan board, verify ec is alive and version is reported as blaze Change-Id: I115890a7122440a25c3d1f5e4b94248099a1de99 Signed-off-by: Neil Chen <neilc@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/190610 Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
* stm32: add STM32F03x configurationVincent Palatin2014-03-223-0/+47
| | | | | | | | | | | | | | | | | | Add STM32F03x as part of the STM32F0 family. STM32F031 will be used for devices requiring low-end parts. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=along with the following CLs, run on STM32F051 Discovery with limited RAM and Flash to mimic STM32F031. Change-Id: Ie95303eaf00ce53fe7c8d2ac84c19a983aadbf0d Reviewed-on: https://chromium-review.googlesource.com/189404 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* make the common runtime optionalVincent Palatin2014-03-2211-10/+49
| | | | | | | | | | | | | | | | | | | | | In order to achieve really tiny firmwares, make our runtime (tasks, hooks, muxed timers, GPIO abstraction ...) optional. Add 2 new build options for it : CONFIG_COMMON_RUNTIME and CONFIG_COMMON_GPIO which are enabled by default, and ensure all the source files are built according to the right configuration variable. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall build a minimal board with no runtime. Change-Id: Icb621cbe0a75b3a320cb53c3267d6e578cd3c32f Reviewed-on: https://chromium-review.googlesource.com/189403 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* samus: enable config option for low power idleAlec Berg2014-03-212-0/+10
| | | | | | | | | | | | | | | | Enable low power idle for Samus. BUG=none BRANCH=none TEST=tested on samus. made sure EC comes up with no obvious problems and that the EC goes into deep sleep a minute after no console activity. Change-Id: I00e196560759dfd62915e645319de606f2f29df3 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190791 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Sameer Nanda <snanda@chromium.org>
* rambi: change EC accel sampling rate and default sensor output data rate.Alec Berg2014-03-202-4/+26
| | | | | | | | | | | | | | | | | | Two accelerometer changes: - Lower accel sampling rate when chipset is off to 10Hz. Increase sampling rate back up to 100Hz when transitioning to S0. - Change the default output data rate of the accelerometers to 100Hz which matches the EC sampling rate when in S0. BUG=none BRANCH=rambi TEST=manual testing. used lidangle command to verify that in S0, EC is sampling at 100Hz, and in S3 or lower it is sampling at 10Hz. Change-Id: Ie4e20f45f9371d674c3325a362d2729c331fac4f Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190032 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: implement ADC support for STM32F0xxVincent Palatin2014-03-203-5/+277
| | | | | | | | | | | | | | | | | | | | | | Replace the stubs by an actual implementation for ADC and Analog watchdog support on STM32F0xx chips. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=manually read ADC values on STM32F072B discovery. TEST=read all ADC values at once. TEST=Enable watchdog and check it fires when the voltage goes out of range. TEST=read ADC value(s) while watchdog is enabled. TEST=Disable watchdog and check it's actually disabled. Change-Id: Ie6fbd1aa95a3d76394fa47803e8cfc24bf5e4562 Reviewed-on: https://chromium-review.googlesource.com/190710 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: add analog GPIO configurationVincent Palatin2014-03-203-1/+12
| | | | | | | | | | | | | | | | | Allow to setup a GPIO pin in analog mode on STM32 chips. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run comparators with GPIOs in analog mode on STM32L151 and STM32F072. Change-Id: Ie11dd8711e39ab191c96478c6d8c7b7e0dfa7ea4 Reviewed-on: https://chromium-review.googlesource.com/189863 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Create stub files for charge_state_v2.cBill Richardson2014-03-205-79/+160
| | | | | | | | | | | | | | | | | | | Remove copied code from V1 implementation, reduce to bare minimum needed to satisfy external dependencies. Don't actually enable it for any platforms, though. BRANCH=ToT BUG=chrome-os-partner:23776 TEST=make buildall -j It's used by anything and doesn't do anything if it was, but test compilation of the changed sources by defining CONFIG_CHARGER_V2. Change-Id: Iea37d0b4fc48c8ebf7f7088cd1674d6e275d03d4 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190853 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Rename charge_state.[ch] to charge_state_v1.[ch]Bill Richardson2014-03-2015-151/+198
| | | | | | | | | | | | | | | Making room for a new charge_state implementation. BRANCH=ToT BUG=chrome-os-partner:23776 TEST=make buildall -j No new functionality, just renaming some files. Change-Id: I80ce861f09129a518e180cac20d32e867a93cd46 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190852 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Remove conditional declaration of charge_want_shutdown()Bill Richardson2014-03-201-4/+0
| | | | | | | | | | | | | | This is only used in power_button_x86.c, which always defines CONFIG_CHARGER, so there's no need to make it conditional. BRANCH=ToT BUG=chrome-os-partner:23776 TEST=make buildall -j Change-Id: I415572e691cc5bd6b189f9d3dd737b4209c33669 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190851 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* baytrail: Increase time after all voltages good to 15 msRandall Spangler2014-03-181-3/+3
| | | | | | | | | | | | | | We had decreased this from 100 ms to 5 ms, but apparently we need at least 10 ms. Use 15 ms to give us some margin. BUG=chrome-os-partner:25264 BRANCH=rambi TEST=boot system Change-Id: I4d96aeb1040a042bac46fa8701a073d3355bfd2a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190485 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* it8380dev: fix firmware can't startup (re-generate)Dino Li2014-03-183-4/+15
| | | | | | | | | | | | | | | | | | | | | | Some section(entry point, interrupt vector, e-flash signature and so on) of linker script file are not linked. The start address of e-flash signature should always at 00000080h. Default firmware treats VCC logic high to prevent pin 11 logic low but use following functions. (EC2I, KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI) Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Firmware can startup on IT8380 emulation board. Change-Id: I9860ac5b99dcc6e9e00dbc9d1e79a141237b7789 Reviewed-on: https://chromium-review.googlesource.com/190008 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* Big: Add ectool discharge command.cloud_lin2014-03-183-0/+30
| | | | | | | | | | | | | | | BRANCH=big BUG=None TEST=Run ectool chargecontrol command with each option (normal, idle, discharge) on Big. Verifiy battery is discharging in discharge mode via EC console 'battery' command. Signed-off-by: Cloud Lin <Cloud_Lin@compal.com> Change-Id: Iab150c36df64016d06831a6a6c620742738ae2af Reviewed-on: https://chromium-review.googlesource.com/189450 Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Lin Cloud <cloud_lin@compal.com> Commit-Queue: Lin Cloud <cloud_lin@compal.com>
* stm32: add 32-bit timer supportstabilize-5656.BVincent Palatin2014-03-143-1/+172
| | | | | | | | | | | | | | | | | | | | | Some STM32 variants have a 32-bit timer in addition the bunch of 16-bit timers. Add the option to use the 32-bit timer as the system clock source to lower the overhead of the timer code compared to a pair of 16-bit timers. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run the EC on STM32F072 Discovery board with 32-bit TIM2 as the clock source. Change-Id: If55c4e23a3f68dd8f6ca32e93f3a27c1743c767b Reviewed-on: https://chromium-review.googlesource.com/189861 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: remove the conflict I2C2/GPIO config in nyan/big.Louis Yung-Chieh Lo2014-03-135-11/+0
| | | | | | | | | | | | | | After Alex's CL 8a9817a, the i2c driver no longer hardcodes the I2C port pin (Ya!). Remove the conflict pin setting in board files. BRANCH=nyan,big BUG=chrome-os-partner:26620 TEST=build and run on nyan board. Everything looks good. Change-Id: Iee2c5f10f642da7ad00f503b6e615cb6aa472459 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189245 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Measure speed gain in utils test only on deviceVic Yang2014-03-131-2/+17
| | | | | | | | | | | | | | | | | When measuring speed gain of mem*() in utils test on host, there are too many reasons that the results may be fluctuate. This gets even worse when the unit tests run on buildbots. Let's only check for speed gain on device. BUG=chromium:351870 TEST=Check the speed gain check assertion is not compiled. BRANCH=None Change-Id: I0369d07d1da8cbb469d3a2a9d846406415c06745 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189804 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Big: implement the power and battery LED behaviortest-5619.Bgit-cloud_lin.compal.com2014-03-115-8/+178
| | | | | | | | | | | | | | | | | | | | | | | Remove power_led_task and add the big-specific LED logic BRANCH=big BUG=None TEST=manually >> ectool led power blue: PWR LED blue >> ectool led power yellow: PWR LED orange >> ectool led power off: PWR LED off >> ectool led power auto: PWR LED auto control >> ectool led battery blue: BAT LED blue >> ectool led battery yellow: BAT LED orange >> ectool led battery off: BAT LED off >> ectool led battery auto: BAT LED auto control Signed-off-by: Cloud Lin <cloud_lin@compal.com> Change-Id: I5ded361a46c627e4e4e6fcb6bddea9b487a46768 Reviewed-on: https://chromium-review.googlesource.com/188631 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Commit-Queue: Lin Cloud <cloud_lin@compal.com> Tested-by: Lin Cloud <cloud_lin@compal.com>
* stm32: flush write buffer before start DMA transfer.Louis Yung-Chieh Lo2014-03-111-0/+3
| | | | | | | | | | | BUG=chrome-os-partner:22849 TEST=Tested on peach-pit FAFT. No "checksum invalid" from cpu_uart.txt BRANCH=pit,nyan Change-Id: I64f4b636943158fab48892020980f784ca551e4f Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178087 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* discard unused functions at link timeVincent Palatin2014-03-114-64/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | Put each functions in a separate section by using -ffunction-sections, then discard the non-referenced ones in the linker with -gc-sections. Force keeping a few special symbols by using the KEEP() linker directive. This modification is not saving a lot of spaces per se, but will enable larger code pruning with future optional features. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall, manually check discarded symbols in the .map file and run on Spring and Link. The size delta is the following: Link: total 85.7k -> 84.9k (.text 60.3k -> 59.5k) Spring: total 59.2k -> 57.2k (.text 44.4k -> 42.5k) Change-Id: Ib6eb0d3f2cc4fc172c9fc26acac2e486921690a3 Reviewed-on: https://chromium-review.googlesource.com/189224 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* properly define __packed when using itVincent Palatin2014-03-111-0/+2
| | | | | | | | | | | | | | | | | | | we don't want to get a __packed symbol, so we need to define __package attribute before using it for "struct version_struct". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST="make buildall" and verify that we no longer have a __packed symbol in any of the build/<board/ec.{RO|RW}.map. Change-Id: I4c229660f9b751a9149c08261fe71154067e6e62 Reviewed-on: https://chromium-review.googlesource.com/189223 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* add support for FruitPie boardVincent Palatin2014-03-114-0/+128
| | | | | | | | | | | | | | | | | | Until we have real hardware, use the STM32F072B Discovery board as a test vehicle and do a configuration compatible with both boards. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board, and pass all available unit-tests on target. Change-Id: Ica691f9fc915d2873761025e7c019f8a6484b9b1 Reviewed-on: https://chromium-review.googlesource.com/188984 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add support for STM32F0xx familyVincent Palatin2014-03-1114-17/+608
| | | | | | | | | | | | | | | | | | Add support for the STM32F0xx family of devices using a Cortex-M0 core and slightly newer peripherals than F1xx family. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board. and pass all available unit-tests on target. Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735 Reviewed-on: https://chromium-review.googlesource.com/188983 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Add Cortex-M0 core supportVincent Palatin2014-03-1114-0/+1734
| | | | | | | | | | | | | | | | | | The Cortex-M0 core is based on ARMv6-M instruction set rather than ARMv7-M as Cortex-M3 and M4. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run console on STM32F072, and pass all available unit-tests on target. Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e Reviewed-on: https://chromium-review.googlesource.com/188982 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* force the compiler to use a valid register allocation for irq handlersVincent Palatin2014-03-1127-71/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* rambi: fix potential bug in accelerometer initAlec Berg2014-03-081-2/+2
| | | | | | | | | | | | | | | | | | | | | Fixed a potential bug in accelerometer initialization that could result in failing to write the desired accelereometer settings. Before writing the desired settings, we first send a command to perform a software reset. While waiting for software reset to complete, if we have an I2C error, then we could interpret this as software reset complete and go on to write the accelerometer settings before the reset has actually completed. BUG=none BRANCH=rambi TEST=Code inspection. I haven't actually seen this bug, I just saw the potential for it. Change-Id: I78757106291ffbaeff27f94aa6f74c9cea81e0b9 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189064 (cherry picked from commit 521a99e38428fcfe928616f4932b5d1167e2f6cb) Reviewed-on: https://chromium-review.googlesource.com/189233 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Add host command to read raw tmp006 dataRandall Spangler2014-03-073-0/+67
| | | | | | | | | | | | | | | This is needed to calibrate the tmp006 remote sensor values. BUG=chrome-os-partner:26581 BRANCH=none TEST='ectool tmp006raw N' works for N=0,1,2,3 And fails with invalid param for N=4. Data matches result of tmp006 ec console command. Change-Id: I04ec093c7727b55caca7d02baaf373d1ff234731 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189207 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* test: remove one more 64-bit multiplicationVincent Palatin2014-03-071-1/+1
| | | | | | | | | | | | | | | | | | | On some CPU cores, the compiler needs an helper to perform the 64-bit multiplication. As the only remaining 64-bit multiplication in the code base is not necessary, fix it rather than adding the helper. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=build for Cortex-M0 platform. Change-Id: I88dd7a4f2eabeca5b03fb3db232bbca9a037dcf8 Reviewed-on: https://chromium-review.googlesource.com/189151 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Big: add LGC 3s battery infocloud_lin2014-03-071-0/+24
| | | | | | | | | | | | | | | BRANCH=big BUG=chrome-os-partner:26533 TEST=build ec and flash to big board; verify battery works Signed-off-by: Cloud Lin <cloud_lin@compal.com> Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Change-Id: Ia005a549b8318b4f8df81e7b1341d50da28f4282 Reviewed-on: https://chromium-review.googlesource.com/188632 Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
* rambi: Add 7 ms delay before turning off PP3300_DX at shutdownRandall Spangler2014-03-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This works around an issue where LCDVCC falls too slowly. The impact is to slow shutdown by 7 ms, which isn't noticeable to the user. BUG=chrome-os-partner:26561 BRANCH=rambi TEST=shut down rambi; still shuts down, and ~7 ms more time is spent in S0->S3 state. before: [429.933010 power state 3 = S0, in 0x043f] [429.933240 power state 7 = S0->S3, in 0x043f] [429.933614 power state 2 = S3, in 0x042b] [429.934013 power state 8 = S3->S5, in 0x0428] after: [20.355975 power state 3 = S0, in 0x003f] [20.356194 power state 7 = S0->S3, in 0x003f] [20.363957 power state 2 = S3, in 0x002c] [20.364179 power state 8 = S3->S5, in 0x002c] [20.364877 power state 1 = S5, in 0x0008] Change-Id: Ie843bdcf740f3dbc1b866a0356cea2a8b42d4194 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189092 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Big: add 4s battery LGC AC14B8K supportMilesDY_Chen2014-03-071-1/+25
| | | | | | | | | | | | | | Big can't be powered on by using 4s LGC AC14B8K battery. Thus, add 4s battery definition to ec. BRANCH=big BUG=chrome-os-partner:26533 TEST=flash ec to big device and confirm battery works Change-Id: I32d2eb2fabc70f3fc075a49a67c1fd4d30975981 Signed-off-by: MilesDY_Chen <MilesDY_Chen@compal.com> Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188651
* stm32l: supports fake-hibernateLouis Yung-Chieh Lo2014-03-066-5/+139
| | | | | | | | | | | | | | | | | | We don't have available GPIO pin for power button as the hibernate (stand-by) wake-up source. Also, we don't want to do board change. So, put the EC in a decent infinite loop to pretend the hibernate mode and wait for particular wake-up event. This should be fine because the AP is already down before EC hibernates. BUG=chrome-os-partner:25435 BRANCH=Nyan TEST=see comment #6 of issue for detailed test steps. Change-Id: I2cae131789f9ca5808b60d5f2495222ca9016e7c Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186061 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: add wedge commandHung-ying Tyan2014-03-062-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This command wedges the I2C bus by writing part of a byte to or reading part of the response from the slave device. To enabled the wedge command you must define CONFIG_CMD_I2CWEDGE and you must define I2C_PORT_HOST, the i2c port to use the wedge command. BUG=chrome-os-partner:19286 TEST=Manual test on peach pit, spring, and glimmer. Define config in board.h to enable the command: On the EC console, execute the following "i2cwedge" command i2cwedge 0x90 0 1 (wedge write) or i2cwedge 0x90 0 2 (wedge read) and then "battery". Observe that the command reports an error. Similarly, execute i2cwedge 0x90 0 5 (wedge write + reboot) or i2cwedge 0x90 0 6 (wedge read + reboot) on the EC console and observe a reboot. Then execute "battery" and observe that the command works properly. BRANCH=none Change-Id: I10ccb21b047df907a4dfdbd84c0f582cfa2d939a Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/66389 Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* Move CLZ emulation to common codeVincent Palatin2014-03-065-39/+51
| | | | | | | | | | | | | | | | | | | Move the CLZ instruction emulation C code to the common directory, so it can be reused for all CPU cores missing a CLZ instruction (e.g. CortexM0). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board with Cortex-M0 core, and pass all available unit-tests on target. Change-Id: Ief56cac7430fcb0fbced8a8925250c89cbd0bcfc Reviewed-on: https://chromium-review.googlesource.com/188981 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* test: remove 64-bit multiplicationVincent Palatin2014-03-061-2/+2
| | | | | | | | | | | | | | | | | | | | On some CPU cores, the compiler needs an helper to perform the 64-bit multiplication. As the only 64-bit multiplication in the code base is not necessary, fix it rather than adding the helper. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=build for Cortex-M0 platform. Change-Id: Id5d6b4b6641f81732a456dacb78dee7262f6729d Reviewed-on: https://chromium-review.googlesource.com/188980 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Add initial big supportKatie Roberts-Hoffman2014-03-066-1/+522
| | | | | | | | | | | | | | BRANCH=big BUG=chrome-os-partner:26533 TEST=emerge-nyan_big chromeos-ec; flash big board, verify ec is alive and version is reported as big Change-Id: Idbf84d029b5c7b7c198f8c4a2bd2a90d79524441 Reviewed-on: https://chromium-review.googlesource.com/188926 Tested-by: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Samus: Enable manual control of TOUCHSCREEN_RESET_LBill Richardson2014-03-061-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The charger task was holding this either on or off in S3, no matter what we wanted. We really only need to set it at S3->S0 or S3->S5, or when the lid opens or closes. The rest of the time we should be able to turn it off and on with gpioset, for testing purposes. BUG=chrome-os-partner:26502 BRANCH=ToT TEST=manual Check the state with gpioget TOUCHSCREEN_RESET_L Open and close the lid, suspend the AP with powerd_dbus_suspend, etc. The touchscreen should be on when the lid is open and the AP is in either S3 or S0, off when the lid is closed or the AP is off. Then gpioset TOUCHSCREEN_RESET_L 1 gpioget TOUCHSCREEN_RESET_L gpioset TOUCHSCREEN_RESET_L 0 gpioget TOUCHSCREEN_RESET_L The change should persist as long as nothing else changes. Change-Id: If7b6f809b1b28ae2699d0fbc6c9b2305fc57cbff Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188869 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Combined i2c unwedge code into one common functionAlec Berg2014-03-0610-268/+489
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactored the i2c unwedge code to place it in the common directory so that any EC chip can use it. Added to the STM32F and LM4 boards, code to automatically detect and unwedge the i2c bus at the start of an i2c transaction. Note that STM32L already had this ability. To enable unwedging of the i2c port though, the gpio pins for SDA and SCL must be defined in the i2c_ports[] array in the board.c file. This allows the i2c module to bit bang the unwedging for the given port. If SDA and SCL are not defined for the port, then the unwedge code will not run. BUG=chrome-os-partner:26315, chrome-os-partner:23802 BRANCH=none TEST=Manual testing on machines with different EC chips. Testing made extensive use of https://chromium-review.googlesource.com/66389 in order to force wedging of the i2c bus so that we can attempt to unwedge it. Note that you can easily test if the bus is wedged by running i2cscan. On pit and spring: On pit, after each of the following, I verified that the bus was automatically unwedged. On spring, the unwedge only runs at reboot, so, for the non-reboot wedge commands, I manually ran console command unwedge, and verified that the bus became unwedged. (1) Bit bang a transaction but only read part of the response. Command to wedge: i2cwedge 0x90 0 2 2 (2) Bit bang a transaction to do a "write" and stop while the other side is acking. Command to wedge: i2cwedge 0x90 0 1 (3) Same as (1) but do a reboot instead of returning and see that the unwedge works at init time w/ no cancelled transactions. Command to wedge: i2cwedge 0x90 0 6 2 (4) Same as (2) but do a reboot instead of returning and see that the unwedge works at init time w/ no cancelled transactions. Command to wedge: i2cwedge 0x90 0 5 On glimmer: Added code to call i2c_unwedge in accel_init(). Then tested unwedging the accelerometer with the following. One extra difficulty testing this with the accelerometer is that sometimes the bit you stop on is high, which means it won't be wedged at all, the next start transaction will reset the bus. So, sometimes running i2cwedge won't wedge the bus and sometimes it will depending on the acceleration data. (1) Big bang transaction to do a "read" of accelerometer and stop partway: i2cwedge 0x1c 0x0f 2 2 i2cscan to make sure bus is actually wedged i2cunwedge i2cscan to make sure bus is now unwedged. (2) Bit bang transaction to do a "read" and stop partway, then reboot: i2cwedge 0x1c 0x0f 6 2. i2cscan to verify that the bus is working after the reboot. Change-Id: Ie3328e843ffb40f5001c96626fea131c0f9ad9b1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188422 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Remove time-dependent test from coverage measurementsBill Richardson2014-03-051-0/+3
| | | | | | | | | | | | | | | | | | | Compiling with coverage enabled screws up the time that things take, so don't test for a particular speedup in that case. It fails unreliably. BUG=chrome-os-partner:20881 BRANCH=ToT TEST=manual cd src/platform/ec make coverage Before, it failed about half the time. Now it doesn't. Change-Id: I535f0193bf450a922b486777b296fea1b2768a1a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188790 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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