summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* ryu: workaround MAX77620 shutdown issuestabilize-6946.55.Brelease-R43-6946.BVincent Palatin2015-04-041-0/+10
| | | | | | | | | | | | | | | | | | | | | When shutting down the MAX77620 PMIC by asseting its SHDN pin, the EN_PP3300 output of the PMIC (GPIO3) is not going off keeping the PP3300 rail up. Workaround that issue by removing the pull-up on EN_PP3300 when we assert SHDN. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:38689 TEST=on a P5 board, type "apshutdown" and see the power state machine going to S5, type "powerbtn" and see it going back to S0. Change-Id: I0e5fba6da118d931b07fff58088604ee00a6bcdd Reviewed-on: https://chromium-review.googlesource.com/263958 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* samus_pd: ryu: change sink capabilities for voltage inaccuracyAlec Berg2015-04-032-4/+4
| | | | | | | | | | | | | | | Change sink capabilities to account for +/-5% voltage inaccuracy for variable and battery PDOs. BUG=none BRANCH=samus TEST=test with third party variable power supply and make sure it see's our sink capabilities as 4.75V-21V. Change-Id: Id793142c486dfc908c81c4894b2ec48f99c868f4 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/263295 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* motion: do not enter S3 if it is already in S5Chris Zhong2015-04-021-0/+5
| | | | | | | | | | | | | | | | | | If sensor->active is S5, do not enter S3, since the sensor has been shut down. BUG=chrome-os-partner:38627 TEST=Gsensor works well BRANCH=firmware-veyron-6588.B Change-Id: I35ab82b8e197b3bc8f8a4d3ae7d8c3b70c17e385 Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/263628 Tested-by: 小华 王 <anndy_wang@asus.com> Tested-by: BoChao Jhan <james_chao@asus.com> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org> Commit-Queue: Alexandru Stan <amstan@chromium.org>
* cr50: add USB supportVincent Palatin2015-04-029-0/+1223
| | | | | | | | | | | | | | | | | | | | | Add a USB device driver for the Synopsys DWC USB device controller. The common USB protocol stack code still need to be de-duplicated with the STM32 implementation. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:33919 TEST=plug Cr50 to a Linux workstation and see USB descriptors using "lsusb -v -d 18d1:5014" Change-Id: I4a367241053de2c2d94aa06f82ea4bee51f9f89a Reviewed-on: https://chromium-review.googlesource.com/231160 Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* charger: add TI BQ2589x charger driverVincent Palatin2015-04-024-0/+365
| | | | | | | | | | | | | | | | | | Driver for Texas Instrument bq25890/bq25892/bq25895 battery charger chip. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:38603 TEST=On a modified board with BQ25892, charge a 1S battery and check ADC values. Change-Id: I536c6b58438464a63ad3d3536b9bb84ff35920e8 Reviewed-on: https://chromium-review.googlesource.com/263458 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: add P5/Smaug supportstabilize-6937.BVincent Palatin2015-04-014-9/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update EC board configuration for P5 boards : - PMIC_THERM_L GPIO used for PMIC shutdown has moved. - add 5V regulator control (used for VBUS only) - the Type-C superspeed muxes control changed - add a temporary pull-up on EN_PP3300 - add new FW_DEBUG_MODE GPIO Try to be compatible with both P4 and P5 by detecting the board variant at runtime. At EC startup, USBC_SS1_USB_MODE_L/USBC_SS2_USB_MODE_L/USBC_SS_EN_L (aka PD3/PD9/PE0 aka MUX_CONF0/1/2) now default to low level rather than high (as the new default value on P5), but they are reset to the correct value when initializing the PD task (high for P4, low for P5+). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:38330 TEST=Ran on P4, check board ID on P5 PCB. Change-Id: Ie9010805a91362c2b4d5eddd825d452d6ccc5b28 Reviewed-on: https://chromium-review.googlesource.com/262310 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Strago: Enable battery chargingDivya Jyothi2015-04-012-0/+65
| | | | | | | | | | | | | | Setting up numbers for Battery info like input current limit, Battery voltage, temperature limits as per the actual battery spec. BUG=None TEST=Tested on Braswell Ref Design BRANCH=None Change-Id: I66c3dfe6166d03d2cb79d80a887168f08753d22d Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/260631 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Strago:Fix I2C Block Read operation.Shamile Khan2015-04-011-0/+39
| | | | | | | | | | | | | | | | | I2C Block reads were split into two i2c_xfer() calls. However, i2c_xfer() implementation for MEC does not maintain state in between calls. This was causing block read failures because the settings for the Control Register got corrupted. Fix this by calling i2c_xfer() only once. This retrieves both string size and string. Only return the string back to the user. BUG=None TEST=Tested on Braswell Ref Design BRANCH=None Change-Id: Ife8fcb66425c6198d0dcf10f74e89c001ccac49a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/260627 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec: Created lightbar params v2Aseda Aboagye2015-03-313-15/+779
| | | | | | | | | | | | | | | | | | | | The 'lightbar params' v1 command has a parameter list that exceeds 120 bytes, which will not work over i2c. Therefore, I created a params v2 command which breaks up the existing parameters into logical groups which are less than 120 bytes. TEST=Tested new lightbar params2 command and ran get/sets on all groups for samus. Repeated test on ryu as well. BUG=chromium:467716 BRANCH=none Change-Id: If0fa92e9a2f373b20257f8ce7eb66b7836d9ac60 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/263106 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mighty: fix the LED bug of removed batteryZhengShunQian2015-03-311-4/+20
| | | | | | | | | | | | | | | | | | | | | | | Clear curr.batt_is_charging when the battery is not present. Add a new batt_was_removed flag to track when the battery has been removed. This causes PWR_STATE_ERROR so the LED shows error state, and triggers re-reading the static parameters from the battery when it's reattached. BUG=chrome-os-partner:38235 TEST=check the LED state on mighty BRANCH=veyron Change-Id: I400c22eda4bc0043adf7217166bd9f80c557d991 Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/262007 Commit-Queue: Gediminas Ramanauskas <gedis@chromium.org> Tested-by: Gediminas Ramanauskas <gedis@chromium.org> (cherry picked from commit 6727e1dba2aafa81fa9572145413545106ae9626) Reviewed-on: https://chromium-review.googlesource.com/262140
* ectool: Revert: Do not increase buffer size after probe max size from ecGwendal Grignou2015-03-282-21/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Not needed with kernel fix: Commands are currenly limited to 252 bytes. Even if EC support protocol v3, ectool would only limit the command sizes, never go beyond 252 bytes. This reverts commit be0bd9b83538427cc350ad38d64b821dfcad82a0. It also remove a TODO. CQ-DEPEND=CL:262870 TEST=With proper kernel, and firmware supporting commands > 252 bytes, check that ectool console does not crash anymore. /usr/sbin/ectool --name cros_sh console returns more character than before. Check ectool version as well. /usr/sbin/ectool --name cros_sh version BUG=chromium:399057,chromium:454324,chrome-os-partner:31989,chrome-os-partner:23823 BRANCH=none Change-Id: I058ab0e6df96196a0fae186d1ffedcfa16e5dc3b Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/262885 Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
* sb_firmware: update arguments and configsstabilize-6919.BSheng-Liang Song2015-03-271-45/+106
| | | | | | | | | | | | | | | | | | | | - Updated arguments to support two sub commands: - check: check if AC adapter is connect. - update: trigger battery firmware update. - All Delay values are from .cfg file. BUG=chrome-os-partner:36310 BRANCH=none CQ-DEPEND=CL:260868 TEST=Verified on Glimmer. crosh> battery_firmware check crosh> battery_firmware update Change-Id: I7324e1f329383cf5ee62660f4ac4cb0b1c30c056 Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/260210 Reviewed-by: Shawn N <shawnn@chromium.org>
* sb_firmware: write PID to lockfile for powerdSheng-Liang Song2015-03-273-0/+110
| | | | | | | | | | | | | | | Add logic to write PID to /var/lock/battery_tool_powerd.lock while performing destructive battery firmware update actions. BUG=chrome-os-partner:36310 BRANCH=none CQ-DEPEND=CL:261318 TEST=Verified on glimmer. Change-Id: I47f34a3a2cb890e66591ef16ac5cf7186d662900 Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/260868 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Fix the ACPI EC0 BAR settingSteven Jian2015-03-261-1/+1
| | | | | | | | | | | | | Per datasheet, it should be 304. BUG=None BRANCH=None TEST=None Change-Id: I3f7b82bf2f63ed011183cd72f4e19daa7dd0dcf0 Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262283 Reviewed-by: Shawn N <shawnn@chromium.org>
* presubmit: enable branch/checkpatch checksMike Frysinger2015-03-261-0/+5
| | | | | | | | | | | | | We're moving the hardcoded check lists out of the pre-upload script. BUG=chromium:466264 TEST=uploading a CL w/out a branch line is rejected BRANCH=None Change-Id: Ifa0f8c3b4be6a20355babb6f9d8896ac8d1fb2be Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/262490 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Skip the battery device name reading on BQ27742Vincent Palatin2015-03-261-0/+6
| | | | | | | | | | | | | | | | | | | | Contrary to the BQ2751 and BQ27741 it is sharing code with, BQ27742 does not have a "device name" register. So we need to skip the I2C reads else the battery_device_name() function returns an I2C error and the charge code retries until the end-of-time to read it hogging the CPU. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:38401 TEST=run on Ryu P4 and verify that we are no longer seeing 20ms of I2C transactions every 100ms on the battery I2C bus. Change-Id: I961af54017f661ee928058b346a42b7206ad8217 Reviewed-on: https://chromium-review.googlesource.com/262449 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* charge_state_v2: properly print static battery info errorsVincent Palatin2015-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | When calling problem() with 0 as value, it's never printed on the EC console since the problem() function is de-duplicating the messages by checking against the last value (which is initialized at zero). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:38401 TEST=run on the current Ryu code (which has a faulty BQ27742 driver) and see the "charge problem: static update [...]" message. Change-Id: Iedfbc95e3751bc5b22452187b404a09b633160d7 Reviewed-on: https://chromium-review.googlesource.com/262448 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* ACPI: Support accessing memmap data over ACPI CMD / DATA portsstabilize-6915.BShawn Nematbakhsh2015-03-2513-129/+304
| | | | | | | | | | | | | | | | | | | | | | | Some platforms are unable to access the 900h-9ffh region over LPC and must instead access memmap data through the ACPI CMD / DATA ports. To avoid racing with data updates, disallow changes to multi-byte memmap data while in burst mode. Linux currently enables burst mode when accessing multi-byte data and disables it immediately afterward, though the ACPI spec defines burst mode in a more general way. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Undefine LPC_MEMMAP and modify asl to move memmap data to ERAM at offset 0x20. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ib848bdb491fdfece96ad0cee7a44ba85b4a1a50b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/262072 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Ryu: Add support for the SPI over USB bridgeAnton Staaf2015-03-253-14/+69
| | | | | | | | | | | | | | | | | | | | This enables the USB SPI bridge and adds Ryu specific functions for enabling and disabling the SPI bridge. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Verify that a modified flashrom can read and write the AP SPI Flash. Change-Id: I3ed2503e23c360c0de7a3aedd1d256be7e82df1e Reviewed-on: https://chromium-review.googlesource.com/260965 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* charger: bq24773: Fix read input current errorstabilize-6912.Bjames_chao2015-03-241-2/+2
| | | | | | | | | | | | | | | | | | | 'ectool chargestate show' shows the wrong input current since the function charger_get_input_current() uses REG8_TO_CURRENT. BUG=None TEST=Use 'ectool chargestate show' or UART command 'charger' check the input current value. BRANCH=None Signed-off-by: james_chao <james_chao@asus.com> Change-Id: I29229ea1ef22811035b500c7a33fedee6562db35 Reviewed-on: https://chromium-review.googlesource.com/259842 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Shawn N <shawnn@chromium.org>
* charger: Add support for bq24770james_chao2015-03-244-27/+109
| | | | | | | | | | | | | | | | Add support for bq24770 (smbus) in the bq24773 (i2c) driver. BUG=None TEST=Use the UART command "charger" and check the charger information. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie5f5af60e93aa73d9ef68115af36a8d28f6d6c2b Reviewed-on: https://chromium-review.googlesource.com/259870 Reviewed-by: BoChao Jhan <james_chao@asus.com> Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* CCD: Add ability to enable and disable SPI bridgestabilize-6909.BAnton Staaf2015-03-233-40/+84
| | | | | | | | | | | | | | | | | | | | | This required changing the USB-SPI implementation slightly so that all work is done within the deferred callback. In particular, this allows the board specific enable and disable functions to do things that can only be done from a task context, like sleeping. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I3f6a01ed9d6f31a3259ba0a0f6b4e123d6d2e718 Reviewed-on: https://chromium-review.googlesource.com/260964 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* USB-SPI: Set the interface SubClass to Google SPIAnton Staaf2015-03-232-2/+5
| | | | | | | | | | | | | | | | | | This SubClass will provide a simple mechanism for host tools to discover SPI bridge enabled devices. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I0c800ca7b1a2ac58584eab8ba201a6b2a5a894ea Reviewed-on: https://chromium-review.googlesource.com/260963 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* it8380dev: add KBC/KMSC moduleDino Li2015-03-2214-62/+610
| | | | | | | | | | | | | | | | | 1. DLM 16KB. 2. Add KBC/KMSC module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EVB + x86 MB can boot into DOS and keyboard works. Change-Id: Ia5cc2d4f1733ce07879d410b0447b2d48e50cd95 Reviewed-on: https://chromium-review.googlesource.com/259923 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* cr50: Added PMU driverSheng-Liang Song2015-03-214-316/+767
| | | | | | | | | | | | | | - Porting from cosmo code base. - Support clock initialization BRANCH=none BUG=chrome-os-partner:33813 TEST="make buildall -j; Verified on RevA1 Chip" Change-Id: I59e2bb133968d408acde44a3082e1b3b8f4bbbff Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/236394 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: Added macros for register read/writeSheng-Liang Song2015-03-202-7/+90
| | | | | | | | | | | | | | | | Added macros for register read/write. BRANCH=none BUG=chrome-os-partner:33815 TEST="make buildall -j; Verified on RevA1 chip" Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Change-Id: I25c6f6b5865c7fdde002b2191b1f2eaaba15f589 Reviewed-on: https://chromium-review.googlesource.com/236402 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Sheng-liang Song <ssl@chromium.org> Tested-by: Sheng-liang Song <ssl@chromium.org>
* cr50: added cr50 a1 chipSheng-Liang Song2015-03-2013-7/+18598
| | | | | | | | | | | | | | cr50_a1 is for cr50 Rev A1 chip. BUG=chrome-os-partner:33432 BRANCH=none TEST=Compile Only Change-Id: I5490d1a5b89fa66c8e8b969cff7538a293a7d053 Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/259847 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* spi_flash: Rework protection translation functionsShawn Nematbakhsh2015-03-175-237/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we defined separate functions to map registers to protect ranges for each supported SPI ROM. This change instead adds a protect range table + flags for each supported SPI ROM and adds common functions for translation between ranges + registers. This makes supporting new parts easier. Since we will never use most supported protection ranges, we can even simplfy the tables. The implementation is now similar to flashrom. BUG=chrome-os-partner:37688 TEST=Manual on Glower. flashwp disable + spi_flash_rsr --> 0 flashinfo --> shows no protection spi_flash_prot 0 0x10000 + spi_flash_rsr --> 0x24 flashinfo --> shows 64KB protected spi_flash_prot 0 0x20000 + spi_flash_rsr --> 0x28 flashinfo --> shows all 96KB protected spi_flash_prot 0 0x40000 + spi_flash_rsr --> 0x2c spi_flash_prot 0 0x80000 + spi_flash_rsr --> 0x10 spi_flash_prot 0 0 + spi_flash_rsr --> 0x00 spi_flash_prot 0 0x1000 --> error spi_flash_prot 0x10000 0x10000 --> error BRANCH=None Change-Id: Ie5908ce687b7ff207b09794c7b001a4fbd9e0f5a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/259310 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* USB: Add udev rule to handle CCD devicesAnton Staaf2015-03-161-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | This udev rule creates a directory in /dev/google for each device attached. The name of the directory is unique to the device and is prefixed with the device product name. Within the directory there is a serial directory that contains symlinks to each USB serial port exposed by the device. The symlinks are named based on the USB interface name provided by the EC. Additional subdirectories can be added for I2C, JTAG, GPIOs, and SPI as needed. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=Verify that two different CCD devices generate uniquely named entries. Change-Id: I7e6f2ace29b7302c7c072bcf6aab7c8f060b993a Reviewed-on: https://chromium-review.googlesource.com/260420 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* lm4: stm32: Store panic data in backup registers on hard resetShawn Nematbakhsh2015-03-148-20/+136
| | | | | | | | | | | | | | | | | | On hard reset / hibernate, RAM will be erased and panic data will normally be lost. When software panic data saving is enabled, try to save this data just before hard reset and restore it when we come back up. BUG=chrome-os-partner:37380 TEST=Manual on Samus with WP + SW sync enabled. Boot AP, then run "crash divzero" on console. After hard reset, verify that "panicinfo" dumps data and shows divzero exception code. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9516dd4b6db12ef35e512cc4710f9b97d7e663cb Reviewed-on: https://chromium-review.googlesource.com/255912 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ectool: Always try v0 of GET_VERSIONS command if v1 failsShawn Nematbakhsh2015-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ioctl return status for CROS_EC_DEV_IOCXCMD is inconsistent across kernel versions: - In 3.8 kernel, on INVALID_VERSION EC result, -EBADMSG is returned - In 3.14 kernel, on INVALID_VERSION EC result, success status is returned In both cases, the INVALID_VERSION result is written to the cros_ec_command.result parameter. The inconsistency here should be fixed with kernel patches. In any case, there is little harm with trying v0 of GET_VERSIONS on any failure of the v1 command. BUG=chrome-os-partner:37668,chromium:466896 TEST=Manual on peppy. Verify 'ectool thermalget 0 0' prints threshold info. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic1eb3f8f2fa95711ec15a5afb740af8f18b88b55 Reviewed-on: https://chromium-review.googlesource.com/260004 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Bill Richardson <wfrichar@chromium.org> Trybot-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: make source-only PD devices compatible with the common runtimeVincent Palatin2015-03-132-5/+11
| | | | | | | | | | | | | | | | | | Add the proper checks to be able to compile source-only PD devices with the common runtime. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:37078 TEST=make buildall build honeybuns without CONFIG_USB_PD_DUAL_ROLE defined Change-Id: I7ad0b39b2e62736117ec2d7b5163502afbf14786 Reviewed-on: https://chromium-review.googlesource.com/259112 Reviewed-by: Scott Collyer <scollyer@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* honeybuns: fix CC voltage thresholdsVincent Palatin2015-03-121-4/+4
| | | | | | | | | | | | | | | | | | | | | The Rp resistor on CC1 is set for a 3.0A capability, so Vnc (no-connection voltage) is 2.45 V. CC2 is not connected (captive cable), so for a PD source, it's identical to being always pulled-up to 3.3V (no sink connection). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:37078 TEST=connect to Samus and see PD activity Change-Id: I8df0561cea59896d65d9be6523d4eed953851129 Reviewed-on: https://chromium-review.googlesource.com/259301 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* honeybuns: fix CC line sensing ADCVincent Palatin2015-03-121-1/+1
| | | | | | | | | | | | | | | | | The CC line is connected to the ADC 1 not 0. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:37078 TEST=use the "adc" command and see the pull-up to 3.3V on CC1_PD. Change-Id: I6327adc8ea166c4fb450c6711e17d8140fd6c71d Reviewed-on: https://chromium-review.googlesource.com/259300 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* honeybuns: add HX3 hub configurationVincent Palatin2015-03-122-1/+117
| | | | | | | | | | | | | | | | | Send the Cypress HX3 Hub configuration over I2C. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:37078 TEST=see the Hub booting in normal mode and enumerating. Change-Id: I7e32eecd1d69ba0899b726c0405d392602e7d8b7 Reviewed-on: https://chromium-review.googlesource.com/256697 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* honeybuns: Initial /board filesScott Collyer2015-03-128-0/+728
| | | | | | | | | | | | | | | | | | Modified version of /board/fruitpie. Attempted to capture GPIO definitions. Other changes consisted of modifying functions to enable compilation. No real functionality as of yet. TEST=Serial console and I2C functions have been verified BUG=chrome-os-partner:37078 BRANCH=samus Change-Id: Iedfc724a058e4220176193ef0f66e5bf45eabbd9 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/252426 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add flash physical interface functionsShawn Nematbakhsh2015-03-129-21/+282
| | | | | | | | | | | | | | | | | | | | | | | | Add physical flash interface for read / write / protection of external SPI on mec1322. BUG=chrome-os-partner:36167 TEST=Manual on glower: flashread 0xf000 0x200 --> dumps 0xff flashwrite 0xf000 0x200 flashread 0xf000 0x200 --> dumps write pattern flasherase 0xf000 0x1000 flashread 0xf000 0x200 --> dumps 0xff spi_flash_prot 0 0x10000 flashinfo --> shows first 64KB protected spi_flashwrite 0xf000 0x200 --> access denied spi_flashwrite 0x1f000 0x200 --> OK flashread 0x1f000 0x200 --> dumps write pattern BRANCH=None Change-Id: I2cb20a49934999fc0dd9b3425eb99708711637c5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/257132 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* spi_flash: Add protect support for W25X40Shawn Nematbakhsh2015-03-116-20/+117
| | | | | | | | | | | | | | | | W25X40 uses a different protection register encoding than our existing W25Q64 code. Move the SPI ROM option to a config, and add support for the new part. BUG=chrome-os-partner:37688 TEST=`make buildall -j`. W25X40 protection code tested in a subsequent commit. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iaaeabf42c6c62c20debc91afd2cf8671c14244c8 Reviewed-on: https://chromium-review.googlesource.com/258440 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Ryu: Share SensorHub UART control with ServoAnton Staaf2015-03-101-1/+3
| | | | | | | | | | | | | | | | | | | | | Previously the EC UART connected to the SensorHub console was being driven push/pull potentially fighting with a connected servo. This way servo wins, but at least we don't drive the line in opposite directions causing a large current flow. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I02b8e09af6c902b523494b757f4bc7ea4365df2e Reviewed-on: https://chromium-review.googlesource.com/255954 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* llama: enable the EC backlight override for mediatek platform.Ben Lok2015-03-092-2/+35
| | | | | | | | | | | | | | | | | | | 1. Override the panel backlight enable signal from SoC in llama board, force the backlight off on lid close. 2. Revise the function llama_lid_event to mtk_lid_event, makes more sense. BRANCH=master BUG=none TEST=lid switch to open/close, observe the LCD backlight behavior. the backlight should be off, when lid is close. the backlight should be on, when lid is open. BOARD=llama Change-Id: Id1bff440c8bb6cee19c82615e916b8a2f2aa62ac Signed-off-by: Ben Lok <ben.lok@mediatek.com> (cherry picked from commit a90516b0a5493a55536e29d550f65cc743156710) Reviewed-on: https://chromium-review.googlesource.com/255441 Reviewed-by: Rong Chang <rongchang@chromium.org>
* llama: implement battery ship shutdown modeyh.huang2015-03-092-1/+40
| | | | | | | | | | | | | | | Support battery cut-off as host command and console command. BUG=none BRANCH=master TEST=tested "cutoff" console command cuts off battery BOARD=llama Change-Id: Id5c67d296b7ecfac99389d5cfcdcaa79da9ad4f3 Signed-off-by: Ben Lok <ben.lok@mediatek.com> (cherry picked from commit 0274ffd14a35b478b8efa74cdd2d3303da96ec54) Reviewed-on: https://chromium-review.googlesource.com/255440 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* usb_pd: fix HPD State error under IRQ_HPDBernard Shyu2015-03-071-1/+1
| | | | | | | | | | | | | | | | The HPD State field (bit7) should be HIGH when IRQ_HPD (bit8) is asserted. BUG=none BRANCH=samus TEST=make buildall Change-Id: I27181623d5ef2f657839aa63222d6788a3257dad Reviewed-on: https://chromium-review.googlesource.com/253930 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org>
* samus: ryu: allow charge ramp on CDP and proprietary chargersAlec Berg2015-03-075-8/+27
| | | | | | | | | | | | | | | | | | | Modify charge ramp so that when it ramps it ramps from 500mA and up to the maximum allowed by that supplier. Also modify Samus and Ryu to use charge ramping for CDP and proprietary chargers due to the possibility that they may not be able to supply the amount that is supposed to be guaranteed by their advertisement. BUG=chrome-os-partner:37549 BRANCH=samus TEST=test on a proprietary charger, make sure we can ramp. test a DCP and make sure we also ramp as before. Change-Id: I08fd43c8f0b21aa54d114fbe5a1296c9556357e4 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/256972 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* lightbar: clear all segments first before starting konami seqAlec Berg2015-03-061-0/+3
| | | | | | | | | | | | | | | | | | | Clear all lightbar segments first before starting konami sequence. If currently displaying Google colors, we need this so the start of the sequence shows up correctly. BUG=chrome-os-partner:37469 BRANCH=samus TEST=from S0 with google colors on lightbar, run "lightbar seq konami" from EC console and make sure 1st and 4th segments are cleared before starting konami sequence. Change-Id: I92ba8f29414c279895658167f8d5958fe49ea034 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/256192 Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* flash_ec: add support for strago and cyanBernie Thompson2015-03-061-0/+2
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=`flash_ec --board=strago --image /ec.bin` `flash_ec --board=cyan --image /ec.bin` Verify flashing success. Change-Id: I10b93f5e646687ac1f299b12ff5a91aedfdd3d75 Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/255950 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Remove RO image to save program memoryShawn Nematbakhsh2015-03-061-3/+8
| | | | | | | | | | | | | | | | mec1322 projects are running very low on flash space. We don't yet have a loader to load either RO or RW at runtime, so remove the RO image entirely. This is a temporary change and should be reverted once we have a working loader. BUG=chrome-os-partner:37510 TEST=make buildall -j BRANCH=None Change-Id: I8c502ec2bcabf246d5a3ea939f1a8d0c366acd9f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/256381 Reviewed-by: Vic Yang <victoryang@chromium.org>
* samus: change tap for battery to not show dimmed last segmentAlec Berg2015-03-062-1/+19
| | | | | | | | | | | | | | | Change tap for battery lightbar sequence to not show the last segment dimmed as a percentage of your battery. BUG=chrome-os-partner:37335 BRANCH=samus TEST=use battfake console command to test out every increment of 10% and use "lightbar seq tap" to show tap. Change-Id: I4f38d26a8cfbecfa6efc86fcc8751ca8cb34879b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/256191 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: limit input current when batt near full and 5V chargerAlec Berg2015-03-062-23/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | Limit input current to 2A when battery is near full and we are using a charger below the boost bypass threshold in order to prevent charging noise from the charge circuit. This also changes the threshold at which 5V ramping is allowed to 90% because this is roughly the threshold at which the battery stops drawing full current. BUG=chrome-os-partner:36534 BRANCH=samus TEST=load onto samus. use battfake EC console command to test various battery states of charge: - With zinger, verify that at 20V we never limit input current based on battery SOC. - With zinger at 5V, verify that >= 90% we limit input current to 2A, and < 90% it's still 3A. - With 5V BC1.2 DCP, verify that >= 90% we don't ramp, <90% we do. Change-Id: I868828b5807572736ea58f62bf3596f6416533d2 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/256072 Reviewed-by: Shawn N <shawnn@chromium.org>
* motion_sense: Add required headerAlexandru M Stan2015-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | include/motion_lid.h is generally included by board.c in the various boards. But include/motion_lid.h actually needs host_command.h defined or else including it in board.c will cause a confusing error. This probably doesn't show up on other platforms like samus and glimmer because they define a few custom commands in board.c, but veyron doesn't need that. motion_lid ought to just include it directly if it really needs it. BUG=None, see next commits in the series, they won't compile without this TEST=See series BRANCH=veyron Change-Id: I42e966d891dbbcca7df484b59c9d1bb35d1357bc Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/256696 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* samus_pd: disable i2cxfer console command to save spaceAlec Berg2015-03-063-0/+4
| | | | | | | | | | | | | | | Disable the i2cxfer console command by default to save space BUG=chrome-os-partner:37167 BRANCH=samus TEST=make -j buildall From .map file, 576 bytes of flash saved Change-Id: I0b50161ef0a49231e45c422da5042db77874aed1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/256071 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
View Lorry Controller Status