| Commit message (Collapse) | Author | Age | Files | Lines |
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According to spec, RSMRST shouldn't be deasserted until 10ms after power
signals become active.
BUG=chrome-os-partner:41556
TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to
G3 on apshutdown, and back to S0 on powerbtn.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4
Reviewed-on: https://chromium-review.googlesource.com/280571
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.
BUG=chromium:496895
BRANCH=none
TEST=make buildall -j
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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There is no need for the usb flag, remove it.
There is no need for the unprotect flag, remove it.
BRANCH=none
BUG=chrome-os-partner:22990
TEST=run flash_ec before and after
Change-Id: I201bad7f5be63a90bb8168e21baef2c6fa8d85b4
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Update the recovery key combination to: power key + volume up when the
AP is off.
Add a fastboot key combination: power key + volume down when the AP is
off.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41629
TEST=on Ryu, shutdown the AP, press "power+volup" or "power+voldown" and
see the right trace.
Change-Id: I42cf368d42885717758fc4b494af5c8a16fc58b0
Reviewed-on: https://chromium-review.googlesource.com/278323
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
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For the few platforms without gpio.inc, use this
enum gpio_signal {
GPIO_COUNT
};
instead of this
enum gpio_signal {
NULL
};
The only reason this worked at all is that the headers are
included in a particular order.
BUG=none
BRANCH=none
TEST=make buildall
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I81533f3614d0b4c7389f9edd42cd8ac018581f46
Reviewed-on: https://chromium-review.googlesource.com/278120
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This puts the .PHONY declaration next to the target, so that we
don't overlook any.
BUG=none
BRANCH=none
TEST=make buildall
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I944537fdc3a90691a7f2de0bff9d7f9df4898cf8
Reviewed-on: https://chromium-review.googlesource.com/278019
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Console command 'batter' reaches STM32F0's TASK_STACK_SIZE(488). Oak
needs a larger stack in development stage.
BRANCH=none
BUG=none
TEST=manual
load on oak and type 'battery' in console.
Change-Id: Iab3d0bd23837932acb873ecdeb194af74f10f29c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277979
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Use the right rounding function for the charging voltage selection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41594
TEST=On Smaug EVT2, check that the battery is charging to 100% and
compare the voltage requested by the battery (using "battery" command)
to the voltage set by using "charger" command.
Change-Id: Ic5076f23242d1fac31ad34e0c8c9bfe0a868a91e
Reviewed-on: https://chromium-review.googlesource.com/278260
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
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Setup wakeup source and enable hibernate support.
BRANCH=none
BUG=chrome-os-partner:40752
TEST=manual
start servod:
sudo servod -b oak -c oak.xml
in EC console, type 'hibernate' to enter hibernate mode.
check ec 3.3v current and power consumption:
dut-control ec_3v3_ma ec_3v3_mw
check wakeup source:
open lid, press power button or plug in charger
Change-Id: Ic32c3879b0b9dac86c5e08ab9f3daba428c58720
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277978
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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This just makes the LEDs blink continually, because I have a
development board sitting on my desk and I like to see it doing
something.
You can still force the GPIOs on and off using the tool in
extra/usb_gpio/.
BUG=none
BRANCH=none
TEST=make buildall
Try it:
sudo make BOARD=discovery-stm32f072 flash
The LEDs blink.
Force them on and off with:
cd extra/usb_gpio
make
./usb_gpio write -1 0
./usb_gpio write 0 -1
./usb_gpio write 2 0
./usb_gpio write 4 2
To resume blinking, use
./usb_gpio write 0 0
Change-Id: Iadbe7436c02de5b6eae81885d95bad154ca3692c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274131
Reviewed-by: Anton Staaf <robotboy@chromium.org>
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This change enables USB3/DP superspeed mux. Oak's two type-C ports share
one DP hardware. When both ports connect to DP output device, only the
first DP signal will be routed to SoC. On exit dp mode, oak sends HPD
again if the other port's DP flag is on.
BRANCH=none
BUG=chrome-os-partner:41404
TEST=none
Change-Id: I7eebc0b2354f93d7421bf83796294a6b2acf4c3b
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277000
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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BUG=chrome-os-partner:38103
TEST=flashrom -p ec -w ec.bin updates EC successfully.
Does not cause a reboot and does not corrupt flash.
BRANCH=none
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Change-Id: Id45074b991dc6d6d7ed68f72c57a81d9ec1a0713
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/278002
Reviewed-by: Shawn N <shawnn@chromium.org>
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Add pmc(LPC ACPI) control module for emulation board.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. 62h/66h port.
1-a. out 66h 80h, out 62h 00h, in 62h 02h
1-b. out 66h 81h, out 62h 01h, out 62h 55h
1-c. out 66h 80h, out 62h 01h, in 62h 55h
1-d. out 66h 80h, out 62h 02h, in 62h aah
2. H2RAM LPC I/O cycle 900h ~ 9FFh = DLM 0x8D900 ~ 0x8D9FF
and host read only.
3. 80h port, console command port80.
4. host command.
4-a. host request (LPC I/O 800h ~ 807h)
03 FD 00 00, 00 00 00 00
out 204h DAh, in 200h 00h
host response (LPC I/O 800h ~ 80Bh)
03 F7 00 00, 04 00 00 00, 02 00 00 00
4-b. host request
03 EE 01 00, 00 00 04 00, 01 02 03 04
out 204h DAh, in 200h 00h
host response
03 E5 00 00, 04 00 00 00, 05 05 05 05
Change-Id: I5c3bac66306dfba380548a74a64536ea606ddd3e
Reviewed-on: https://chromium-review.googlesource.com/269271
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Dino Li <dino.li@ite.com.tw>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
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Add functions and associated test to read/write a 32 bit register
BRANCH=smaug
TEST=Test on smaug with bm160 driver
BUG=chromium:39900
Change-Id: Ieff24b65f1eb8610874fe13c4a8fadf583a218cb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277535
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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VESA SCR titled,
'DP Alt Mode Plug Corrections & Protocol Clarif'
Simplified the DP config mode VDM to longer include two separate bytes
for UFP vs DFP pin modes since bits <1:0> designate the desired port
direction.
This change corrects our VDM accordingly so that <23:16> are now zero
(SBZ) and <15:8> carry the appropriate pin mode.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus_pd
BUG=chromium:501002
TEST=manual,
1. samus -> hoho, dingdong or apple hdmi dongles still drive DPout
2. twinkie console output samus -> hoho shows correct DP config VDM
369.275296 SRC/2 [256f]VDM Vff01:DPCFG,INI:ff018111 00000406
where:
<31:16> = SBZ == 0x0000
<15:08> = PIN_C == 0x04
Change-Id: I1146045dd94458c82b7ed08940af6009658afa05
Reviewed-on: https://chromium-review.googlesource.com/278083
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Add TCPC support for USB VID register and use that register
from the TCPM side to know when the TCPC is ready. TCPC is
ready when phy layer is initialized and CC ADC channels have
been read.
BUG=chrome-os-partner:40920, chrome-os-partner:41258
BRANCH=none
TEST=load and run glados. verify that glados EC doesn't
start sending TCPC commands until it can successfully
read TCPC VID. verify that we can boot with zinger and no
battery.
Change-Id: Iafbab529a16ff904cdb817901baac5e72e3d7220
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277710
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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BUG=chrome-os-partner:40526
TEST=Enable Software Sync in Coreboot and Depthcharge. Compile
EC followed by Coreboot and program Coreboot. Compile a new
version of EC and program it. Reboot and check EC version of
RW image when Login Screen appears. The version should not be
the latest.
BRANCH=none
Change-Id: Ib6f5aa57fdda607a5c1cf59c8786a4a3a46b575f
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276426
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Initialize CC termination variable based on the default PD role.
BUG=chrome-os-partner:40920
BRANCH=none
TEST=load on glados. test by rebooting PD from PD console with
nothing plugged into the type-C ports. Without this change, the
EC gets stuck in SNK_DISCONNECTED_DEBOUNCE, because the PD defaults
to using the wrong termination and so the PD thinks the CC ADC
readings represent Ra. At this point you have to reboot EC to get
back to normal functionality. With this change, rebooting PD does
not wedge the PD protocol state machine.
Change-Id: I4eb6d881d8fc995be4d6a99ffa69e484141343f2
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277666
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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BUG=chrome-os-partner:41063
TEST=Enable Software Sync in Coreboot and Depthcharge.
Enable hash computation in EC. Compile EC followed by
Coreboot and program Coreboot followed by EC on a Cyan
system. System should boot to Chrome Login Screen.
BRANCH=none
Change-Id: I4b53e9e55e4da279366eb1283a11a010c52b865f
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276305
Reviewed-by: Shawn N <shawnn@chromium.org>
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To avoid hardware tests build errors of oak
BRANCH=None
BUG=None
TEST=make -j BOARD=oak tests
Change-Id: Ia1874c2d271508414e32e89a05763c144d9e3b84
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/277625
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Rong Chang <rongchang@chromium.org>
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changes added to support flashrom are:
sysjump support to be able to copy the RO/RW image
and jump to it without causing AP to reboot while
its alreday ON.
LPC init should be reinitialized on sysjump
corrected gpio_set_flags_by_mask to make sure we
update the register only for GPIO_LOW condition and not
all else conditions.
BUG=chrome-os-partner:38103
TEST=commands : flashrom -p ec -w ec.bin
flashrom -p ec -r ec.bin
BRANCH=none
Change-Id: I23892f0378d756052030e73034c3acdd41477e34
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/272000
Reviewed-by: Shawn N <shawnn@chromium.org>
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RO/RW images may reside at an offset to the start of code memory,
defined at the chip-level by CONFIG_R*_MEM_OFF.
BUG=chrome-os-partner:38103
TEST=Manual on Cyan. Verify sysjump works correctly in both directions.
BRANCH=None
Change-Id: I54c5f20335a5646d49afcc8d3fa2eb90ca9349d0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274434
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
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When a USB-PD debug accessory is plugged, set the default data role to
UFP (USB device) on Ryu.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=none
TEST=On Ryu, plug a SuzyQ and connect with ADB using a A-A cable.
Change-Id: Ifa62b097532880ab5cadb7f2ab7774eec752f1e6
Reviewed-on: https://chromium-review.googlesource.com/277276
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
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Without this change, after a while, the data from the accelerometer is
garbled, weaker than expected.
BUG=chromium:494270
TEST=Check that with this change, the accelerometer vector is always
around 1G.
BRANCH=smaug
Change-Id: I9bb4acd208e8fa4111fc91e35c4cb5636f9425f4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276666
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Move disabling the TX timer up to as soon as possible after
DMA transmit is complete to avoid potentially clocking another
bit, which could corrupt the end of the transaction.
BUG=none
BRANCH=smaug
TEST=load on glados and use a scope to verify the end of transmit
is clean.
Change-Id: If52ba2475eeb9752da0acc8efc957c1f472bc711
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277298
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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If the AP is already shutdown, apshutdown would previously power the AP
up with a power press. Fix this by making sure we're not already in G3
before triggering the power press.
BUG=chrome-os-partner:40677
TEST=Run 'apshutdown' on glados while in G3, verify that AP does not
power up.
BRANCH=None
Change-Id: I8b898b034dcf40f0acef4fb6098af0aebba566c6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277400
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Change pd_tx_done() to wait specifically for the DMA complete
event using task_wait_event_mask().
This fixes a potential bug where if we get another event, for
example a TCPM event, while waiting for transmit to complete
we restore the pending event after we are done.
BUG=none
BRANCH=smaug
TEST=run on glados and make a bunch of contracts with zinger.
Change-Id: Ie28d97eba3edcc7a98fe842e8b7eb6b9d7707047
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277297
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Change TCPC to not sample CC ADC channels immediately after transmit
because we are likely to get a response immediately after transmit
and this could cause us to sample while traffic is on the line and
cause us to record the wrong voltage.
BUG=none
BRANCH=smaug
TEST=test on glados. put a print when TCPM is notified of CC voltage
change. without this CL, we occasionally get a false CC voltage
change. with this change, CC status stays consistent.
Change-Id: I9199a0ed98632b1f26b2b5b98f34928e4de328bf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277296
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Disabling CC TX_DATA needs to be very fast to avoid clocking out
an extra garbage bit at the end of transmit. This change fixes
pd_tx_disable() to disable the TX_DATA line as fast as possible.
BUG=chrome-os-partner:40920
BRANCH=none
TEST=test on glados with scope attached to CC. note before this
change we occasionally get a garbage bit at the end of CC transmit.
With this change, it looks clean.
Change-Id: I86b47881e3846b2e3dd4fc2afcf2d28386a068a6
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277295
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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When we are going to S5 with a debug accessory plugged, we cannot
transition through the 'PD_DRP_FORCE_SINK' else we would
disable/re-enable the USB muxes triggering disconnections/glitches on
the USB debug console.
So, rework the management of the dual role toggling special case
(used to detect debug accessories) : remove the special DRP state and
re-write the conditions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41399
TEST=on Ryu, connect to the EC console through Suzy-Q and issue
the "apshutdown" command, then see the EC USB console is randomly
disconnected/re-connected or acting up.
Change-Id: Id44a9360a836e7c10a30f5afb2971bc7c3d01a5c
Reviewed-on: https://chromium-review.googlesource.com/277275
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
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The case closed debugging feature is using the USB controller, so it
needs to disable the low power STOP mode of the MCU which is
incompatible with USB communication.
As the possibility of doing PD communication when a PD debug accessory
is plugged "re-appeared", just set/use the USB_PD sleep disable bit with
the debug accessory rather than creating a new one.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41399
TEST=on Ryu, connect to the EC console through Suzy-Q and issue the
"apshutdown" command, then see the EC USB console is still alive.
Change-Id: I8668b28220202ce6419f18cff13d57d410e3e9f3
Reviewed-on: https://chromium-review.googlesource.com/277116
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
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If task_get_current() is called early during initialization when we have
not yet done a context switch, our current_task pointer is invalid. Add
an assert to detect this case and put it behind CONFIG_DEBUG_BRINGUP, a
new config that's intended to enable possibly-costly pre-production
debugging.
BUG=chrome-os-partner:40677
TEST=Manual on glados. Define CONFIG_DEBUG_BRINGUP, then call i2c_write from
board_init and verify the new assert fails. Remove the i2c_write and verify
the new assert passes.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6014ccf739dcc4c8f4f960be2b89f01e423b65b5
Reviewed-on: https://chromium-review.googlesource.com/273541
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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We normally do not charge from non-dedicated chargers. The process of
determining whether a charger is dedicated or not involves PD protocol
communication, so it can take some time to reach a determination. If no
battery is attached, the charger is likely our only source of power, so
don't cut it off.
BUG=chrome-os-partner:41258
TEST=Attach donette to glados system with no battery, verify that glados
boots to EC console and doesn't reset or panic.
BRANCH=None
Change-Id: I7c9cfcbd37b37ef16010cf1f246d8fddba6f6283
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277074
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Enable charger detection through the pericom chips.
BUG=chrome-os-partner:40920
TEST=Manual on Glados. Plug 1A Apple charger, verify that port is
selected and charge limit is set correctly on both ports. Also verify
that Zinger still charges correctly.
BRANCH=None
Change-Id: I7e462194560965b6140446f3444be225e5503616
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276886
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Page Boundary.
If SPI Flash write is at an offset within the page and the length
is greater than remainder of the page, the Flash page gets
corrupted as addressing wraps to the beginning of page and
previously written data gets overwritten. This change splits SPI
Flash writes in such cases into two operations in different pages.
BUG=None
BRANCH=None
TEST=During Software Sync, Depthcharge sends Flash write chunks that
cross page boundary. With this change, the RW parition does not get
corrupted. This can be confirmed by executing a successful
"sysjump RW" after a Software Sync.
Change-Id: I46349eea0d8e927353de7cb55a61e9960291adb6
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/275760
Reviewed-by: Shawn N <shawnn@chromium.org>
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Previously we supported using a single pi3usb9281 chip, or using two
chips on the same i2c bus behind a mux. Now that we need to support a
third configuration of multiple chips on different busses, it makes
sense to be able to configure the configuration freely at the board
level.
BUG=chrome-os-partner:40920
TEST=Manual on samus_pd. Plug USB charger, verify detection is correct
on both charge ports.
BRANCH=None
Change-Id: I120dcb1c3ceb6f013b92407effcd8cb66e7ffcce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276511
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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If host running flash_ec has multiple servo's connected it must use
the USB serialname to identify the proper FTDI device to run flashrom
on correctly. CL adds serial param to flashrom call to do just that.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=none
TEST=manual, successfully write glados EC w/ multiple servo V2's
connected to the same host.
Change-Id: I35c7d170f9bb80e96f69efae634cf70893eeef63
Reviewed-on: https://chromium-review.googlesource.com/276761
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Add command to read the sensors events FIFO from the AP:
FIFO_INFO: get information on the FIFO state
FIFO_READ: read and update the consumer pointer
FIFO_FLUSH: insert a flush meta event and force a interrupt.
A new MKBP event is added to tell the host the FIFO needs processing.
BRANCH=smaug
TEST=Test on ryu
BUG=chrome-os-partner:39900
Change-Id: I11c0cf8cdc3087eb9e323f7d6780e6cf3a16257f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276264
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BRANCH=samus
BUG=none
TEST=compiles
Signed-off-by: Todd Broch <tbroch@chromium.org>
Change-Id: Id925acbafcb49dbf503f666a7edb79b7eb25fecd
Reviewed-on: https://chromium-review.googlesource.com/276554
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
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Change pd_transmit() to wait specifically for the TX complete
event using task_wait_event_mask(). This fixes a bug that if
another event, it will now restore that event instead of
consuming it.
BUG=chrome-os-partner:40920, chrome-os-partner:41290
BRANCH=smaug
TEST=load onto glados and zinger and attach them a bunch of
times and get stable contract with no hard resets.
Change-Id: I36514ea45b5e2b5fd42acdad94e5786da5bd90b6
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276745
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Add task_wait_event_mask() function to core/cortex-m0, core/host
and board/zinger/runtime in order to delay a task until a specific
event occurs.
BUG=none
BRANCH=smaug
TEST=make -j buildall
Change-Id: Ic89487fcae5352eec53b745179c7f0d5893ad3e0
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276744
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Add spi_enable() before SPI transaction. This fixes a problem where protect
host cmd ended up messing up SPI controller state.
Change-Id: Ief61f279cbd0a90e55ce87d0c350072dc8616c31
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276338
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
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The in_stream and out_stream interfaces were a first attempt
at providing an abstraction for multiple stream like devices
(usart, USB, I2C/LPC host interfaces...). But, by baking
the queue into the device it proved to be hard to use and
required additional resources (task or deferred hook) to handle
passing data from one stream to another.
Since then the queue policy and producer/consumer interfaces
have replaced the stream interfaces. This CL removes the old
stream interfaces and updates the only users (deleting the
test echo code from the discovery-stm32f072 board and updating
the mcdp28x0 driver to use the queue interfaces).
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ic0d2abf81eafc4fb2e61172540151f2d0ba45caf
Reviewed-on: https://chromium-review.googlesource.com/276163
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
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According to the datasheet, PIN should not be set in the CTRL register.
BUG=none
TEST=Verify with I2C analyzer that no error is observed.
BRANCH=none
Change-Id: Ifed58b413151b40ed951cb71b1164432fea28eca
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276672
Reviewed-by: Shawn N <shawnn@chromium.org>
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Add battery cutoff functionality to glados.
BUG=none
BRANCH=none
TEST=use console cutoff command to verify that it cuts off
battery and plug in zinger to verify that it comes out of it
when AC is applied.
Change-Id: I71ae113c398278ad9f67f3a4cedf6885754a5a72
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276690
Reviewed-by: Rong Chang <rongchang@chromium.org>
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Move the task responsible for detection of USB chargers to common code
to reduce code duplication.
BUG=chrome-os-partner:40920
TEST=Manual on samus_pd. Plug USB charger, verify detection is correct
on both charge ports.
BRANCH=None
Change-Id: I362f8b5b51741509e459c66928131f1f6d2a3b1d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276210
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Change battery temperature ADC into an input with a
pull-up and use it for battery detection.
BUG=none
BRANCH=none
TEST=boot with and without battery and check gpio
accurately reflects battery status.
Change-Id: Id30a6c2d7eaad2e6f3c69be4bab33dbcf0682e29
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276650
Reviewed-by: Rong Chang <rongchang@chromium.org>
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Per discussion in CL:274728, hardware revision numbers are integer. So
the previous rev1.5 becomes rev2. And the previous rev2 is now rev3.
BRANCH=none
BUG=none
TEST=none
Change-Id: Ic7a1a60ce0b17a3469965cdca99332df0243ce2a
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276577
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Now that we've removed boards from ToT, also delete board-specific
code used only by the removed boards.
There are still more things to remove (unused charging chips, LED
drivers, COMx support). More CLs coming.
BUG=chromium:493866
BRANCH=none
TEST=make buildall -j
Change-Id: Ie6bdeaf96e61cadd77e3f6336c73b9b54ff4eabb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276524
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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When EC boots up on type-C port 1 VBUS power, it shouldn't turn off
CHARGE_L control.
BRANCH=none
BUG=chrome-os-partner:41167
TEST=manual
remove battery, plug type-C charger to port 1.
check charging LED.
Change-Id: I360715b2f81df5eba0901b854d2dd8e2f0a23651
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276589
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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