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* it8380dev: change PNPCFG base address to 4E/4FDino Li2015-08-041-2/+2
| | | | | | | | | | | | | | | | | Always reserved 2E/2F for super I/O. This can avoid conflict with super I/O base address. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make buildall -j Change-Id: I67a37355e320e289fb1f58c7356a1592f7645d21 Reviewed-on: https://chromium-review.googlesource.com/290087 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: fix keyboard no break codeDino Li2015-08-041-0/+10
| | | | | | | | | | | | | | | | | Wake up task to send the remaining scan codes after OBE(host read data) or IBF(host send command/data). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EC complete sending scan codes. Change-Id: Ie71140bbdfe5fcaccd5d16fd35b426004c218ba8 Reviewed-on: https://chromium-review.googlesource.com/290088 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* tcpc: fix rx buffer overrun bugAlec Berg2015-08-041-2/+6
| | | | | | | | | | | | | | | Fix buffer overrun bug when retrieving a PD message. Bug was introduced in CL:289005 BUG=chrome-os-partner:43482 BRANCH=none TEST=tested on samus. plug and unplug zinger on both ports and make sure PD MCU never crashes. Change-Id: I9d2dec0cab07f389fd935d616ab7443da412d4bd Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/290417 Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_charger: configure boards to disconnect USB when UFP.Alec Berg2015-08-044-0/+4
| | | | | | | | | | | | | | | | Configure boards whose chipset cannot be a USB UFP to disconnect USB lanes when the data role is UFP. BUG=none BRANCH=strago TEST=make -j buildall. tested on glados by adding ccprintf to usb_charger_set_switches(). verified when we are DFP, USB 2 switches are connected and when we are UFP, they are disconnected. Change-Id: Ic8c817a0cc21b56ee67239e8cc81d5cbbda8d4de Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/290422 Reviewed-by: Shawn N <shawnn@chromium.org>
* flash_ec: add support for SWD, nrf51, and hadokenMyles Watson2015-08-046-3/+71
| | | | | | | | | | | | | | | | | | | BUG=none TEST=manual BRANCH=none flash_ec --board=hadoken flash_ec --board=npcx_evb flash_ec --board=samus Use openocd in SWD mode to flash the nRF51 chip. Use warm_reset to exit DEBUG mode. Change-Id: Iaf2827d4ce5be6d61431a3de7ab4f86aa4adde02 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/287039 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_charger: cleanup: move setting usb 2 switches to usb_chargerAlec Berg2015-08-0412-99/+40
| | | | | | | | | | | | | | Move function to set D+/D- switches from board directory to usb_charger module. BUG=none BRANCH=strago TEST=make -j buildall Change-Id: I5c5997c799cecea90448444863167af860a8f3e1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/290421 Reviewed-by: Shawn N <shawnn@chromium.org>
* oak: updates GPIO setting for rev3Ben Lok2015-08-042-36/+56
| | | | | | | | | | | | | | | | | | Modify the GPIO seeting according to the Oak rev3 schematic. BRANCH=none BUG=none TEST=manual 1. define CONFIG_BOARD_OAK_REV_2 in board.h make -j BOARD=oak 2. define CONFIG_BOARD_OAK_REV_3 in board.h make -j BOARD=oak both cases should be built successfully. Change-Id: I0336624a5a2d356a4c2eb9ffb812ebffb4f5f7c3 Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/289475 Reviewed-by: Rong Chang <rongchang@chromium.org>
* flash_ec: Set a 10-minute timeout for flashing ECTom Wai-Hong Tam2015-08-041-5/+12
| | | | | | | | | | | | | | | | | | | | | | The flash_ec script is called by the lab infrastructure to flash the EC firmware of DUT. To prevent the EC flashing tool hanged forever (may be caused by some bugs), set a 10-minute timeout to force it to be killed. BRANCH=none BUG=chromium:514810 TEST=Patched the change to servo v3. Triggered flash_ec to flash EC on Jerry. Set the timeout to a small value to force to kill itself. test2: ./flash_ec --board=hadoken # or samus, anything using openocd remove the USB cable half way through (openocd hangs) ps au | grep openocd Change-Id: I39ad8659b41764fd0dba30a86eca301fbbc5243f Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289247 Commit-Queue: Myles Watson <mylesgw@chromium.org>
* it8380dev: modify sspi moduleDino Li2015-08-045-29/+42
| | | | | | | | | | | | | | | | | We need to modify SSPI module to fix compile fail due to SPI flash common code changed. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console "spi_flashinfo" OK Change-Id: I83bb645eff1e5874d849056df518eea92340c39e Reviewed-on: https://chromium-review.googlesource.com/290089 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* npcx: Fix termination of chip revisionRandall Spangler2015-08-041-1/+2
| | | | | | | | | | | | | | | | system_get_chip_revision() would return a string which lacked the terminating null. Increase the string length and enforce termination. BUG=chromium:511405 BRANCH=none TEST=version; should show chip revision without garbage chars at end Change-Id: Icb9e36c5bfdf7de7400e5316934ccf28b4b57898 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/290392 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com>
* glados: Add bd99992gw temperature sensorsShawn Nematbakhsh2015-08-032-1/+26
| | | | | | | | | | | | | BUG=chrome-os-partner:42156 TEST=Manual on Glados. Boot to S0, run "temps". Verify that temperatures start around 28C and begin to increase after system is powered-on for a long duration. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3bebba4864c8e5b5b23e78947522e58311298bbd Reviewed-on: https://chromium-review.googlesource.com/289936 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* driver/temp_sensor: Add support for BD99992GWShawn Nematbakhsh2015-08-036-0/+408
| | | | | | | | | | | | | | | Add support for ADC / thermistor reads on the BD99992GW PMIC. BUG=chrome-os-partner:42156 TEST=Manual on Glados with subsequent commit. Boot to S0, run "temps". Verify that temperatures start around 28C and begin to increase after system is powered-on for a long duration. BRANCH=None Change-Id: Ic15f41046130317a0e0c3bce4a923ba624328c0d Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289935 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* oak: Request different DP pin modes including multi-function.Ben Lok2015-08-031-5/+17
| | | | | | | | | | | | | | | | | Refer to commit 63786f24, apply same change to Oak. BRANCH=none BUG=none TEST=manual, 1. hoho + oak, pin mode = 'C' 2. dingdong + oak, pin mode = 'E'. 3. apple type-C HDMI multiport + oak, pin mode = 'D' and USB device enumerates as SuperSpeed. Change-Id: I14c6e7ffbe62a329be43f4157ca065db9142b44e Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/290014 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* oak: power: Set 10s for long power key press to force shutdownYH Huang2015-08-031-5/+5
| | | | | | | | | | | | | | | | | In order to pass the test case "firmware_ECPowerButton", I change the value of DELAY_FORCE_SHUTDOWN from 11s to 10s. The test case holds down power button about 10s to shut down without powerd. BRANCH=none BUG=none TEST=manual run "firmware_ECPowerButton" test case. Change-Id: I3da93769f1cb52b04c447df9a7795d3c28ab2bf0 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/282153 Reviewed-by: Rong Chang <rongchang@chromium.org>
* pd: don't enable try.src when battery is not present or too lowAlec Berg2015-08-023-17/+48
| | | | | | | | | | | | | | | | | | Don't enable try.src when battery is not present or <1% because try.src will temporarily cut off power to system. BUG=chrome-os-partner:43413 BRANCH=samus TEST=tested on samus using "battfake" ec command. when battery <1%, verified that try.src is disabled and when battery >=1% and the AP is on (dual-role toggling is on), then try.src is enabled. verified boot without battery succeeds on samus and glados. Change-Id: I64816bb7c9669bfeca61687bcd9a48da32e67945 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289854 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpc: add RX message buffer and don't send goodCRC when fullAlec Berg2015-08-013-39/+101
| | | | | | | | | | | | | | | | | | Add RX message buffer to the TCPC (currently two deep). If the buffer is full and message is received, don't send goodCRC. BUG=chrome-os-partner:43482 BRANCH=none TEST=tested on glados. saw that with back to back PD packets, we send goodCRC to both packets and process them in order, taking about 7ms per packet. also tested buffer size of 1 and verified that with back to back PD packets, we don't send goodCRC to second packet. Change-Id: I7f44b3c3a186ae61be8ca03017deec6e6b6c6f9f Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289005 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: initial tpm state machine supportVadim Bendebury2015-08-011-22/+232
| | | | | | | | | | | | | | | | | | | | | | This patch implements FIFO mode state machine transitions as described in Table 22 of the PC Client Platform document. The 'go' command is still not being handled, as processing needs to run on a task, not on interrupt context. FIFO block integrity is somewhat verified by comparing the actual block size to the length value in the block body. BRANCH=None BUG=chrome-os-partner:43025 TEST=not much. Observed trunksd happily initializing the session and sending the Startup command. The target reports: fifo_reg_write: received fifo command 0x0144 Change-Id: I76d8b0fc3a52db2cc487c781fe92799df0ee259e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288365 Reviewed-by: Utkarsh Sanghi <usanghi@chromium.org>
* tasks: Remove most task_start_called() calls.Aseda Aboagye2015-08-016-17/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Now that HOOK_INIT hooks are called from a task switching context, most calls to task_start_called() should no longer be needed. This commit removes them. BRANCH=None BUG=chrome-os-partner:27226 TEST=make -j buildall tests TEST=Flash EC image onto samus and verify EC boot, AP boot, keyboard, lid, and tap-for-battery all functional. TEST=Flash EC image onto samus_pd and verify charging still works. TEST=Flash EC image onto ryu(P3) and verify that EC boot. TEST=Added ASSERT(task_start_called()) to the places where I removed task_start_called(). Booted samus, samus_pd, cyan, and ryu with AC inserted and verified that no ASSERT's were hit upon boot. Change-Id: Ic12c61862e85ca3a0a295beedbb4eeee6d5e515b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/285635 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* motion_sense: Move angle calculation under LPC_MODEGwendal Grignou2015-08-012-5/+15
| | | | | | | | | | | | | | | | When LPC mode is used, there is an assumption that the first 2 sensors are accelerometers, and the optional 3rd is a gyro. Put the code that fill lpc_data with #ifdef. Prevent lpc space corruption if more than 3 sensors are present. BRANCH=smaug TEST=Compile. Smaug works BUG=None Change-Id: I12c9b823efb57d7b190a1813228f6f02fa0bebcb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/290073
* skylake: Inhibit AP power-on until charge current limit is setShawn Nematbakhsh2015-08-012-0/+25
| | | | | | | | | | | | | | | | | | Inhibit AP power-on through the BATLOW pin, even if the system is unprotected, until our charger and current limit are initialized. Note that this feature is only functional on glados v2 since other skylake boards do not have BATLOW connected. BUG=chrome-os-partner:41258 TEST=Manual on glados v1 with rework. Remove battery and attach Zinger. Verify EC powers on and AP doesn't boot. Run `powerbtn`, verify that AP boots. Remove all power and attach battery, verify that EC powers on and AP boots. Also verify compilation on glados v2. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13 Reviewed-on: https://chromium-review.googlesource.com/287378
* oak: power: change power state while losting POWER_GOOD signalYH Huang2015-08-011-16/+76
| | | | | | | | | | | | | | | | | Check IN_POWER_GOOD signal in S0 and go to S3 if IN_POWER_GOOD is lost. Finally it will go to S5(G3). Check suspend and power good signal after POWER_DEBOUNCE_TIME to avoid transient state. BRANCH=none BUG=none TEST=manual Test power related commands such as "shutdown -P now" or "apshutdown". Change-Id: Ia06fc7d8334c0dfbb0263474f57e4dca7313d331 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/282680 Reviewed-by: Rong Chang <rongchang@chromium.org>
* glados: Free up program memory spaceShawn Nematbakhsh2015-08-011-0/+4
| | | | | | | | | | | | | | Remove the timerinfo console command and console help to free program memory space. BUG=None TEST=Build-only BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6685bb7c83030c21bd975b64f217553d5a11c16b Reviewed-on: https://chromium-review.googlesource.com/289922 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Fix dedicated SPI port accessShawn Nematbakhsh2015-08-012-2/+8
| | | | | | | | | | | | | Correct spi_rx_option table, and use correct port for kunimitsu. BUG=chrome-os-partner:42304 TEST=Burn + boot glados BRANCH=None Change-Id: Ic52ecb48102a74d3c17ab06b6da24ee40659ef86 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289868 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* glados: Buffer AC status to the PCHDuncan Laurie2015-08-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | The AC presence input from the charger only goes to the EC and it needs to provide this signal to the PCH. At init time it is set to the current value and whenever the status changes it will be updated. This is used by PCH internal logic to determine whether to transition into Deep S3/S5 as those are not intended to be used when running on AC power. This is similar to how it worked on Samus except since the EC is off in G3 we don't need to force it low in that state and since there are not yet any additional hacks/workarounds here we can just do the work in a simple HOOK_AC_CHANGE handler. BUG=chrome-os-partner:41885 BRANCH=none TEST=boot on glados and verify PCH_ACOK is asserted when the device starts to charge and is deasserted when no cable is connected. Change-Id: Id7e6ca674e35c98594d09b86ab5bdf518f8b3984 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288922 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* ryu: remove SH UART debug and leftoversVincent Palatin2015-08-013-40/+4
| | | | | | | | | | | | | | | | | | | Remove the last pieces of external Sensor Hub support: - Sensor hub UART exported over case closed debugging - Sensor hub related GPIOs Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:38333 TEST=plug Suzy-Q to Smaug and test debug UARTs and SPI flashing Change-Id: I47b42f63647735bae37b9256e2704303c48b5854 Reviewed-on: https://chromium-review.googlesource.com/290115 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: dynamic switch between SPI and I2C sensors configurationGwendal Grignou2015-08-013-21/+52
| | | | | | | | | | | | | | | | | boards version 6 / 7 / 8 have an I2C bus to sensors. board version 0+ has a SPI bus to sensors On board v0, enable 3rd SPI port and use it to accel the accelerometer. BRANCH=smaug BUG=chrome-os-partner:42304 TEST=Check accel on SPI enabled Ryu board, on v7 and v0 boards, check closed case debugging and type-C features Change-Id: Ic8de2bb0f9d8a15f86a2c1ea98ef27613f090b22 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289960
* driver: bmi160: Allow Dynamic selection of SPI or I2C transportGwendal Grignou2015-08-012-76/+81
| | | | | | | | | | | | | | | Using the LSB bit of motion_sensor addr field, we can select at run time if a sensor is using SPI or I2C. When the hardware stabilize, this CL can be removed. BRANCH=smaug TEST=Check that same image works on both i2c and SPI devices. BUG=chrome-os-partner:42304 Change-Id: I9aef9a4dc739366a3d4e2f6fafe063ecfb5199c6 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289925 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* board: ryu: Enable SPI access to AccelGwendal Grignou2015-08-013-12/+33
| | | | | | | | | | | | Enable 3rd SPI port and use it to accel the accelerometer. BRANCH=smaug BUG=chrome-os-partner:42304 TEST=Check accel on SPI enabled Ryu board. Change-Id: If17eff36e2a3ea0fe59d6677aa41ba5f802e33b6 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288516
* driver: bmi160: Improve FIFO handlingGwendal Grignou2015-08-012-25/+60
| | | | | | | | | | | | | | | | | | | | - Add 3ms after write, found issue with SPI writes. - Do not check FIFO if all sensors are disabled. It contains garbage (0x848484....) - Do not check FIFO length. It can be 0 even if there is data in the fifo. - Remove forever latch and do not reset Interrupt in the handler, we are using level interrupt. - Flush and exit when the FIFO is in a bad state. BRANCH=smaug BUG=chrome-os-partner:43339,chrome-os-partner:39900 TEST=Ran CTS tests. Check sensor is stable. Change-Id: I5cbae819e780b4d50d02829fd8e1178cf34c3f84 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289839 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* motion_sense: Fix invalid optimizationGwendal Grignou2015-08-011-9/+14
| | | | | | | | | | | | | | | | We need to call irq_handler and load_fifo even if the first sensor is disable. Nothing is done on otherwise. Move code to recalculate sample rate to the right place. BRANCH=smaug TEST=Check data is collected when accel is disabled. BUG=chrome-os-partner:39900 Change-Id: Ia6025a670abaf2e71ccbe784bce24e08becf399e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289838 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: Increase CHIPSET stack sizeGwendal Grignou2015-08-011-1/+1
| | | | | | | | | | | | | | We are very close from the current limit (456 bytes). Increase the limit to 640 bytes. BRANCH=smaug TEST=Hit the limit while debugging, check the new limit. BUG=none Change-Id: I6673000bcac48b88599082eb797f0782c4fee454 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289837 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver: bmi160: Fix bugs found testing SPIGwendal Grignou2015-08-013-13/+26
| | | | | | | | | | | | | | | | | | SPI being much faster, need to add right sleep to wait for sensor to change state from suspend. Set the ODR before the range, an issue I did not have with i2c. Fix test used when FIFO is disabled. BRANCH=smaug BUG=chrome-os-partner:42304 TEST=Check sensors are coming and rate/range are correctly set. Change-Id: I5bf655626f1f4232478a04d1d4e1a0d443efbf0f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288517 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver: bmi160: Add SPI access supportGwendal Grignou2015-08-013-21/+90
| | | | | | | | | | | | | Add interface to access the sensor using SPI interface. BRANCH=smaug TEST=compile and work on new Ryu board BUG=chrome-os-partner:42304 Change-Id: I987259a7e378de8ada3b3b55b3662e5028ea31b2 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288515 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: spi: Add lock around spi_transactionGwendal Grignou2015-08-011-0/+6
| | | | | | | | | | | | | | Like the implementation for mec1322, add a lock around spi_transaction. It prevents 2 tasks from accessing a given bus at the same time. BRANCH=smaug TEST=Check the BMI160 FIFO corruption disappeared in SPI mode. BUG=None Change-Id: I9e8a9e39ca96ea56692e3125930ab05ae6ef143f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289856 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: make i2c transactions faster by not sleeping taskAlec Berg2015-08-011-36/+29
| | | | | | | | | | | | | | | | | | Modify i2c driver on mec1322 to change from sleeping and waking on i2c interrupt, to just doing a blocking wait for i2c transfer to complete. This greatly improves the i2c transaction time on fast busses. BUG=chrome-os-partner:43416 BRANCH=none TEST=test on glados. test can talk to battery and PD MCU. Use logic analyzer to see delay between bytes during an i2c transfer. The delay goes from ~70us to ~4us. Change-Id: Iee2a903d27b2e50e54d64bd6d5ed4920293fe575 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289667 Reviewed-by: Shawn N <shawnn@chromium.org>
* oak: fix default input current limitRong Chang2015-07-311-3/+4
| | | | | | | | | | | | | | | | | | | Oak takes power from type-C charger. The default input current limit should set to 512mA default, not the maximum current for battery charging. BRANCH=none BUG=none TEST=manual load on oak and plug an empty battery. check EC uart console on PD state change when plug type-C charger. Signed-off-by: Rong Chang <rongchang@chromium.org> Change-Id: I113fea5ff1e8afc053f76c21820f202e4b3edfec Reviewed-on: https://chromium-review.googlesource.com/287610 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* stm32: Enable 3rd SPI interfaceGwendal Grignou2015-07-308-22/+40
| | | | | | | | | | | | | | | | Remove assumption of only one SPI master going to the SPI flash. SPI3 can be used as second SPI master. Define a new module type, SPI_FLASH, that can be turned on/off when flash is not in used without impacting other SPI masters. BRANCH=smaug BUG=chrome-os-partner:42304 TEST=Test on Ryu board. Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288514
* accel: mechanical changes from i2c_addr to addrGwendal Grignou2015-07-3011-119/+120
| | | | | | | | | | | | | | | Encode both the I2C address and SPI GPIO CS in addr field. Mechanical change to rename i2c_addr into addr. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: I1c7435398deacb27211445afa27a08716d224c06 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288513 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
* common: change interface to SPI flashGwendal Grignou2015-07-3030-183/+351
| | | | | | | | | | | | | | | | Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
* Makefile.rules: Fix build timestamp.Aseda Aboagye2015-07-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The ec_date.h file had incorrect dependencies. $(objs) had no meaning outside of the building the object files as it gets privately overidden with the corresponding target objects (RO, RW, libsharedobjs). This caused ec_date.h to only be generated once from a clean. This commit fixes that by adding all of the RO and RW objects as dependencies (with the exception of version.o). BUG=chrome-os-partner:43373 BRANCH=None TEST=Built ryu, checked build timestamp in build_info. Touched a file, rebuilt, verified that build timestamp was updated. TEST=make -j buildall tests Change-Id: I0ab107efc1a504b4f871ebcf595754db1d414c7a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/289338 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* stm32f05: decrease default system stack sizeAlec Berg2015-07-291-0/+4
| | | | | | | | | | | | | | | Decrease default system stack size on stm32f05 which only has 8k of RAM. BUG=none BRANCH=none TEST=tested on glados. just ran glados_pd and plugged various peripherals into type-C port and saw nothing unusual. Change-Id: Ic051a1387903662414c8e4fdc431e6ecfd7ad57f Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289555 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Driver: Add macros to conditionally compile the console commandsVijay Hiremath2015-07-2913-5/+38
| | | | | | | | | | | | | | Added macros to conditionally compile the console commands to save the memory. These macros can be enabled/disabled in the board specific files. BUG=none TEST=make buildall -j BRANCH=none Change-Id: I108a072c333762cd24ea973612202c9cc4d40914 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/288950 Reviewed-by: Shawn N <shawnn@chromium.org>
* glados: implement and enable fast charging profilesAlec Berg2015-07-292-0/+178
| | | | | | | | | | | | | | | | Implement and enable custom charging profiles on glados to allow us to charge faster. BUG=chrome-os-partner:42864 BRANCH=none TEST=load on glados and charge at room temp. verify using "charger" command that the battery current matches the expected fast charging current for the given temp range. Change-Id: I7b213fd1724e9df09ada89ca27b05e0540b4de2a Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288208 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* host_command_pd: loop over sending PD status host commandAlec Berg2015-07-292-69/+85
| | | | | | | | | | | | | | | | | | | | | | | | Modify host_command_pd.c to loop over sending of PD status host command and processing the response as long as the alert GPIO is active. This fixes a potential bug that if the alert line is held low for more than one PD status host command, then we would not process the return status. Also, fix a bug in which we could call alert() for a non-existent port. BUG=none BRANCH=strago TEST=verified on samus and glados. connected charger and verified that we negotiate a contract and set appropriate input currnet limit. Change-Id: I3b2db87b51f55fc2b20a4695bd466ff8bb09ea55 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288819 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: David James <davidjames@chromium.org>
* cyan: Increase chipset stack size.Divagar Mohandass2015-07-281-1/+1
| | | | | | | | | | | | | | Chipset task is overflowing and causing runtime crash. Increasing the chipset task stack size by 128 bytes. BUG=chrome-os-partner:43329 BRANCH=none TEST=Build/flash EC and boot the platform to OS. Change-Id: I4e444cc48979c74810851ab2625b982fdabdeb73 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://chromium-review.googlesource.com/289112 Reviewed-by: Shawn N <shawnn@chromium.org>
* acpi: Ensure continuity of memmap data with a read cacheShawn Nematbakhsh2015-07-2810-105/+76
| | | | | | | | | | | | | | | | | | | | | For multi-byte ACPI memmap reads, we previously had a mutex to ensure data continuity. A better approach is to use a read cache. Since the kernel will enable burst mode before reading a multi-byte memmap variable and disable it afterward, we can populate the cache on the first read after enabling burst. This solution removes deadlock bugs, is contained entirely in acpi.c, and saves a deferred function. BUG=chromium:514283 TEST=Manual on Glados. Add prints in acpi_read, verify that multi-byte reads come from cache and non-burst reads continue to function as before. BRANCH=Cyan Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I74e4927bf2b433e31a9ff65d72820fa087c51722 Reviewed-on: https://chromium-review.googlesource.com/288871 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: keep 32KHz on for ROSC accuracyKyoung Kim2015-07-281-7/+1
| | | | | | | | | | | | | | | | | | 32KHz osc is necessary to key ROSC in +-2% accuracy. If 32KHz osc is off/on during the heavy sleep, UART produces garbage characters to Tx port until its clock to be stabilized. BUG=none TEST=Cyan BRANCH=none Change-Id: Ie045b9f152eb7dc8d888a2840babefac68081cef Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/288421 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* mec1322: Power state transition in case of apshutdownKyoung Kim2015-07-281-0/+21
| | | | | | | | | | | | | | | | In case of 'apshutdown', SOC loses power immediately while EC is waiting for SOC's PMC_SUSPWRDNACK signal forever. BUG=chrome-os-partner:43038 TEST=Cyan BRANCH=none Change-Id: I34321d00a89011e90222ea5916a42e9a51d4f4b0 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/288203 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* pd: enable try.src for necessary boardsAlec Berg2015-07-274-0/+4
| | | | | | | | | | | | | | | | | Enable Try.Src for Glados, Kunimitsu, Strago, and Oak so that they default to sourcing power when connecting to other dual-role devices. BUG=none BRANCH=strago TEST=make -j buildall Tested on glados by plugging in charger, hoho, and another dual-role device and making sure we resolve roles appropriately. Change-Id: I9393e30b35620eeda3ef1ef56366a97e59ba8054 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288247 Reviewed-by: Shawn N <shawnn@chromium.org>
* kunimitsu: disable asserts to save flash spaceAlec Berg2015-07-271-1/+2
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make -j buildall Change-Id: I8909001a093ebfd4ea482984855931b0764e2552 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288770 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
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