| Commit message (Collapse) | Author | Age | Files | Lines |
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BUG=None
TEST=None
BRANCH=None
Change-Id: I711c89d47e613c6a15531d3b751cb01f5acb4225
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303935
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Add a build option CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF to perform a
battery cut-off when we reach the battery critical low level.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=none
TEST=Discharge a Ryu device down to the critical level, see the message
and verify we cannot restart with the power button. Also check that
plugging the charger revives the device and starts charging.
Change-Id: Ic132a658de5c5131a6a1dd1ce343196b68d480f6
Reviewed-on: https://chromium-review.googlesource.com/303549
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 80b3c99319771312d5733b126b6b3eb839addde9)
Reviewed-on: https://chromium-review.googlesource.com/303812
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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BUG=none
TEST=Manually tested on Kunimitsu & Strago.
Removed the ALS sensor from DUT, using "taskinfo" console command
observed that the ALS task is not running.
BRANCH=none
Change-Id: I96cb720bd8d70033d433cdc2cd9cea9b56a3b389
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/301753
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Do not charge above 48 C.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:45631
TEST=none
Change-Id: I43260ab6079732ab3779d77ed64e3d872c5da4bd
Reviewed-on: https://chromium-review.googlesource.com/302442
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 071b068816722958cebf326857b68b4bb06ecb5b)
Reviewed-on: https://chromium-review.googlesource.com/302475
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
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Added code to enable the system power monitoring functionality to get the
details of the system power consumption.
And also added EC console command "psys" to get the system power consumption.
BUG=none
TEST=Manually tested on Kunimitsu.
Power = Voltage * Current, reading is equal to the power readings
from the psys command.
BRANCH=none
Change-Id: I62519ac96800363b67cab23cd9eb0dcac229cb47
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/302472
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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When building with -j, it's easy to miss errors. If you don't
have your shell configured to warn you about nonzero exit, you
may not even notice that "make buildall -j" failed. To make it
more obvious, we'll do one level of recursion for that target.
That will ensure that the last line of output is always a
pass/fail message.
BUG=none
BRANCH=none
TEST=make buildall -j (with and without errors)
Before this CL, a successful "make buildall -j" ends with this:
MV ec.bin
OBJCOPY ec.hex
LD RW/ec.RW.elf
NM RO/ec.RO.smap
OBJCOPY RO/ec.RO.flat
NM RW/ec.RW.smap
OBJCOPY RW/ec.RW.flat
CAT ec.obj
OBJCOPY ec.bin
COPY_RW ec.bin
MV ec.bin
buildall completed successfully!
(cr) ((fa7baa6...)) ~/trunk/src/platform/ec $
while a failing one looks like this:
MV ec.bin
OBJCOPY ec.hex
LD RW/ec.RW.elf
NM RO/ec.RO.smap
OBJCOPY RO/ec.RO.flat
NM RW/ec.RW.smap
OBJCOPY RW/ec.RW.flat
CAT ec.obj
OBJCOPY ec.bin
COPY_RW ec.bin
MV ec.bin
(cr) ((fa7baa6...)) ~/trunk/src/platform/ec $
Did you see the difference? I suspect some people miss it.
With this CL, a failing "make buildall -j" looks like this:
NM RW/ec.RW.smap
OBJCOPY RW/ec.RW.flat
CAT ec.obj
OBJCOPY ec.bin
NM RW/chip/mec1322/lfw/ec_lfw-lfw.smap
OBJCOPY RW/chip/mec1322/lfw/ec_lfw-lfw.flat
COPY_RW ec.bin
MV ec.bin
COPY_RW ec.bin
MV ec.bin
OBJCOPY ec.bin
COPY_RW ec.bin
MV ec.bin
make[1]: Leaving directory '/mnt/host/source/src/platform/ec'
Makefile.rules:93: recipe for target 'buildall' failed
make: *** [buildall] Error 2
(cr) (stopit) ~/trunk/src/platform/ec $
Change-Id: Id9b47d2869f61e8e3e44b3c618399ca9223f0a71
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303811
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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BUG=None
TEST=`make BOARD=wheatley -j`
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Icd0f27dfa8c05983e67faeb923bd9d0ff048299b
Reviewed-on: https://chromium-review.googlesource.com/303129
Commit-Ready: Shawn N <shawnn@gmail.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
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[chip config]
1. No hardware specific udelay().
2. Enable watchdog.
[watchdog]
3. Watchdog period is "CONFIG_WATCHDOG_PERIOD_MS" of config.h.
4. Watchdog auxiliary timer period is "CONFIG_AUX_TIMER_PERIOD_MS".
[task and irq]
5. Write 1 to clear interrupt pending status, no |.
6. A global variable for store interrupt number of software interrupt.
[uart]
7. Always reset UART module before config it.
[hwtimer]
8. Use more external timers for HW timer module.
[task]
9. Fix task profiling.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=[watchdog]
1. console "waitms 1100", only pre-watchdog warning message.
2. console "waitms 1600", warning message and watchdog reset.
[hwtimer]
3. console commands "gettime", "timerinfo", and "forcetime".
4. enable hook debug and there is no delayed by more than 10%
warning message over 48 hours.
5. There is no watchdog reset too.
[task]
6. console 'taskinfo'
Task Ready Name Events Time (s) StkUsed
0 R << idle >> 00000000 32.927724 308/512
1 HOOKS 00000000 0.034267 372/768
2 R CONSOLE 00000000 0.116763 468/768
3 HOSTCMD 00000000 0.000641 372/512
4 KEYPROTO 00000000 0.000042 212/512
5 KEYSCAN 00000000 0.000908 356/512
IRQ counts by type:
38 2932
155 1
158 261
160 67
Service calls: 87
Total exceptions: 3348
Task switches: 167
Task switching started: 0.001999 s
Time in tasks: 33.282819 s
Time in exceptions: 0.164717 s
Change-Id: I234085cec231cd855d2a5e639ea1b0966c61d796
Reviewed-on: https://chromium-review.googlesource.com/296939
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Old flash_used: 0x0000000000010008
New flash_used: 0x000000000000f708
BUG=None
TEST=`make BOARD=lucid -j`
BRANCH=None
Change-Id: I774ca0243daebc110a4d28001643967a9c5a25d3
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303401
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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BUG=chrome-os-partner:45010
TEST=Manual on glados / glados_pd. Verify that PD power drops by ~60%
when PD MCU is reset and no charger is plugged.
BRANCH=None
Change-Id: Id5a6a8a0f770efe86a21f1b98a967f9b28bbf697
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303405
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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According to the stm32 databook, we cannot enter deep sleep when an i2c
slave interface is addressed until it sees a stop condition.
BUG=chrome-os-partner:45010
TEST=Enable deep sleep on glados_pd, verify that the PD state machine
doesn't toggle between disconnect and debounce (no console spam)
BRANCH=None
Change-Id: I2016c30bccec916d1c22df93303acf50331bd318
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303404
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Add i2c slave sleep mask bit so that deep sleep can be inhibited from
the i2c slave interface independently of the i2c master interface.
BUG=chrome-os-partner:45010
TEST=`make buildall -j`
BRANCH=None
Change-Id: I21755f72a24fedf332e707abf609dc5f8b57e5be
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303403
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Modified drivers:
1. register.h: Add marco field operation funcs for muti-bits field of register.
2. adc.c/fan.c/pwm.c: Simplify field operations by marco funcs.
3. adc.c: Add support for ADC_CH3/4
4. pwm.c: Add PWM_CONFIG_DSLEEP_CLK flag
6. fan.c: Support multi-fans mechanism
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Iaaeb6c4ae8d55b4245a1cefb9c20feae4c0fdec2
Reviewed-on: https://chromium-review.googlesource.com/300673
Commit-Ready: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BUG=chrome-os-partner:40788
TEST=make buildall -j
BRANCH=none
Change-Id: I4fb248da4656374e1218af98678cfb694f4c9176
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/302674
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This is to revert https://chromium-review.googlesource.com/#/c/298067 and
add BOARD_KUNIMITSU_V3 build flag to always enable CHARGE_EN to get proper
VBUS_DET assertion.
When proper hardware is available, this should be removed.
BUG=none
BRANCH=none
TEST=Verified both port is able to charge with zinger on kunimitsu.
Change-Id: I331fd4575d7cef50bd9c1e1118284d5a71364aee
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/303075
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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When a PD charger is found, we typically update charge manager
voltage / current limits to what we want to request, set a 500mA ceiling,
and then wait for negoiation to complete. If it completes as expected,
we simply remove the 500mA ceiling.
When we're already negotiated with a port and we receive a new power
request, we may switch to a different voltage / current limit. If we do
so, charge manager won't get updated with the existing design because we
don't get new source cap information. Therefore, update charge manager
whenever we receive PD_CTRL_PS_RDY as a sink. Typically, the update will
have no effect because we'll be writing identical values. In the new
power request case though it will serve to inform charge manager of the
new mode.
BUG=chrome-os-partner:45932
TEST=Manual on ryu. Insert zinger, run `pd 0 dev 5` followed by `bq` to
verify 3A limit is set as expected.
BRANCH=ryu
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I8cc3ac0a3eb603cdeb45ea437906303abcaedac0
Reviewed-on: https://chromium-review.googlesource.com/302844
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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cl:302176 did not fully fix the issue:
- sampling rate would be unnecessary truncated to integer.
- Because the sensor can slightly oversample (15Hz -> 25Hz, 10Hz ->
12.5Hz), we would skip samples for long period of time.
In both cases we skip samples in low speed tests, noticed by CTS tests.
BUG=b:24367625
BRANCH=smaug
TEST=Before we would fail some
android.hardware.cts.SingleSensorTests#testMagneticField_X,
Now pass.
Change-Id: Ic555e2add47ba89a0a0657f5eb492a5e7ca441d5
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303010
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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This patch brings in the enhanced signer utility published along with
FPGA version 20150925_21715, and the image.cc file updated to fix the
bug where it was not picking up the initialized data segment from the
elf file.
The new signed image header format, among other things, describes
memory areas as read-only and read-execute, which allows the bootrom
to configure the MMU appropriately.
Makefiles had to be modified to reflect the fact that the signed image
now depends on .elf, not on .raw, and that building the signer
requires more source files. Note that some signer features are not yet
being utilized (like processing xml files describing fuses or
retrieving keys from gnubby), the source are kept for completeness.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=build the cr50 image and boot in on the FPGA board using the
spiflash utility outside chroot. Observe the target starting the
console session.
Change-Id: Ib59b8ebbeb98a8146d4d997e1f78178c4fbc031a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303070
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
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This patch upgrades the hardware definition to the latest released
FPGA image, which is reported as follows:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
m3.0.0> info
IDCODE: 2ba01477
DPCTRL: f0000000
m3.0.0> Note: MD5Sums match: 77e8a79e
m3.0.0> Note: CPU0 halted at @ a76
m3debug serial: 0x0
PROJECT: haven revB1
DATE(yyyymmdd): 20150925
TIME(hhmmss): 21715
XML MD5SUM: 0x77e8a79e
HDR MD5SUM: 0xfd9218ab
P4 last CL: 73753
Xml file name include/havenTop.xml
m3.0.0>
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This latest FPGA image includes a more sophisticated bootrom,
requiring a differently signed firmware image. The signer update is in
the next patch.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=verified that the image boots fine when signed by the updated
signer (which comes in the next patch).
Change-Id: I9a5d8e9e786dfa905619f1c629fe75b82c565490
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302803
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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After fixes CL:300630, motion_lid test is fixed:
motion_sense task was exiting during the tests.
BRANCH=smaug
BUG=chrome-os-partner:42855
TEST=motion_lid test now pass.
Change-Id: I7bc464fb2766684093de9b3e479fb5ac3718df04
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302861
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Some sensors are in forced mode, motion sense must be scheduled at
their ODR. However the host may not want the data right away,
so motion task may not wake up the host that often.
Add a new variable motion_int_interval that defines the maximum interval
between FIFO host event.
BRANCH=smaug
BUG=chrome-os-partner:43800
TEST=Check that light sensor is polled at ODR frequency.
Check that when AP does not want any event, no FIFO host event are
requested.
Check CTS tests work as before.
Reenable motion_lid unit test.
Change-Id: Ie25e6cbe28fed899073856057855ffa03c0cd9fd
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/301134
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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When flashrom performs a flash read following an erase and we do not
wait in between for the erase to complete, we read 0x00 instead of
0xFF. Flashrom detects this and does not proceed further. Inserting
a wait after erase solves this issue.
Also added a wait following a flash write operation to preempt future
issues, and moved spi_flash_wait() calls from Host Command APIs to
lower level spi_flash_* functions.
BUG=chrome-os-partner:43160
BRANCH=none
TEST=Manually tested on Kunimitsu FAB3.
flashrom -p ec -w ec.bin is successful
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Change-Id: I00925aa2da3709a6f3e73a40543b079112906e0a
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/302683
Reviewed-by: Shawn N <shawnn@chromium.org>
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Added VRMODECTRL for VCCIO
BUG=none
TEST=Fab3 with new LSW for VCCIO
BRANCH=master
Change-Id: Ibe5350b535037e8101d2a77dca091479480e58e7
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/302686
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Fix bug where sometimes on suspend tap for battery would never work,
but open a resume and suspend again it would work fine. Problem is
that if suspended when accel circular buffer index is 1, then
we would never run the detection algorithm, because the check for
if the history buffer has been initialized is incorrect.
This also fixes the algorithm so that on suspend, it requires the
full sensor history buffer be filled up again before starting to
detect the double tap.
BUG=chrome-os-partner:45930
BRANCH=samus
TEST=go in to suspend when history_index is 1 and verify that tap
for battery works. wrote following console command to pause the
circular buffer at a specific index.
static int pause_index = -1;
static int check_pause;
static void gesture_chipset_resume(void)
{
/* disable tap detection */
check_pause = 1;
}
DECLARE_HOOK(HOOK_CHIPSET_RESUME, gesture_chipset_resume,
GESTURE_HOOK_PRIO);
void gesture_calc(void)
{
if (check_pause) {
if (pause_index < 0 || history_idx == pause_index) {
ccprintf("Paused at %d\n", pause_index);
tap_detection = 0;
pause_index = -1;
check_pause = 0;
}
}
...
static int command_tap_pause(int argc, char **argv)
{
char *e;
int v;
if (argc == 2) {
v = strtoi(argv[1], &e, 0);
if (*e)
return EC_ERROR_PARAM1;
pause_index = v;
}
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(tappause, command_tap_pause,
"",
"", NULL);
Change-Id: I2ba4ab2c807ec6ac1885a4829efedac3c83b32f1
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302648
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
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RAM need not be preserved between jumps from the loader to RO/RW images,
so there is no need for a separate region of loader RAM. Remove
redundant CONFIGs which define this unneeded region.
BUG=None
TEST=Verify glados boots and sysjumps successfully.
BRANCH=None
Change-Id: I2567f17a973c6f9f00bcfd97a4581d6c4b6fd6f0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302586
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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stm32ts60 support is incomplete and largely not validated, so remove
support for the part.
BUG=chrome-os-partner:45362
TEST=`make buildall -j`
BRANCH=None
Change-Id: Ib4c426a2cb2337b4deadeeab8bd195cac1ef81ff
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302497
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Increase the change of false positive, but make double feels like Samus:
- increase time beetwen tap to 500ms
- decrease tap threshold to 100mg (actually 62.5mg)
- increase ODR during TAP.
BRANCH=smaug
BUG=b:24440423
TEST=check Ryu and Samus side by side, their tap behavior is more
similar.
run cts -c android.hardware.cts.SingleSensorTests
Change-Id: I260ad95136cb2be71ef4d71efc4bee0b28afa8e0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302627
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Sandwich wake up event between timestamp.
Otherwise HAL will think the event came from a long time ago.
With two timestamp, the wake event timestamp will be - more - accurantly
set at the time it occurs.
BRANCH=smaug
BUG=chrome-os-partner:45704
TEST=Pass com.android.cts.verifier.sensors.SignificantMotionTestActivity
Change-Id: I6be76820d71d2571d069542564f569a623001190
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302642
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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cl/296213 had another bug that prevent Significant motion gesture to be
set: In set_activity, activity is a number, not a bitfield.
BRANCH=smaug
BUG=chrome-os-partner:45704
TEST=With ectool motionsense set_activity and list_activity,
check we can set/reset the significant motion activity.
Change-Id: Iff921f3f5edcee74ed3540139f13da301f149173
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302641
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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cl:298688 was wrong and oversampling calculation, used to drop
events that AP does not want was incorrect.
We were comparing mHz with Hz.
BUG=b:24367625
BRANCH=smaug
TEST=Before, we would fail all
android.hardware.cts.SingleSensorTests#testAccelerometer tests where
frequency was lower than 100Hz. After, we pass thoses tests.
Change-Id: I487feb4e235a21f78d367397b5890ebcc5864b22
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302176
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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This commit adds the "hibdelay" command which will set the time before
the EC hibernates.
BUG=chrome-os-partner:45608
BUG=chrome-os-partner:44831
BRANCH=None
TEST=Build and flash samus EC with hibernation delay host command
added. Use ectool to set the hibernation delay and verify that the
hibernation delay was changed.
CQ-DEPEND=302197
Change-Id: I91141ee48a648c1052f0a3930a810ea4f551e0a4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/302198
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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gpio_config_module() and gpio_config_pins() had very similar code. This
commit moves the functionality of gpio_config_module into
gpio_config_pins. That is, gpio_config_pins() can now configure an
entire module. This is accomplished by passing in GPIO_CONFIG_ALL_PORTS
as the port parameter.
BUG=chromium:533539
BRANCH=None
TEST=Build and flash on samus. Verify that lightbar, charging, power
button, sensors, all functional.
TEST=make -j buildall tests
Change-Id: I7c9122ebf7b0e2716af2d55b842c4806d8099a63
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/302479
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Add initial board driver for wheatley platform
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I9dccc284e1de10855079611be8593641d837cd64
Reviewed-on: https://chromium-review.googlesource.com/298743
Commit-Ready: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Currently, the only way to prevent a system from hibernating is via the
EC console command "hibdelay". This commit adds the host command
equivalent so that it can be set elsewhere. The host command takes the
amount of time in seconds to delay hibernation by and responds with the
current time in the G3 power state, the time remaining before
hibernation should be invoked, and the current setting of the
hibernation delay.
BUG=chrome-os-partner:45608
BUG=chrome-os-partner:44831
BRANCH=None
TEST=Build and flash on samus. Issue the host command from EC
console. Verify that the hibernation delay was updated by checking with
the hibdelay command.
Change-Id: I34725516507995c3c0337d5d64736d21a472866c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/302197
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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For signed EC RW images (CONFIG_RWSIG), there's no point in
embedding the public key or signature into the image itself since
it will just be replaced by the signer (either as the next step
in the build process, or after the fact for MP releases). This
takes that out and just points to where the pubkey and signature
will be placed.
BUG=none
BRANCH=none
TEST=make buildall
I also checked the signatures with
futility show -t build/*/ec.bin
They still look good, and the one signed image I booted (Cr50)
works as before.
Change-Id: Ib39b7c508914851f81a1bebb2450e08ef0def76c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302630
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This just removes a couple places where a perfectly good CONFIG
macro is simply renamed to something else.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I97a4abe95736504fe97c468336426d0ecc48d62c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302597
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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1. No need for loader data ram
2. 97K code size
3. shifting down RO/RW image location in RAM by 1Kbyte.
(loader code space: 4k to 3k)
BUG=none
TEST=1. build image with big code additions.(like low power idle patch)
and check if there is flash size related error message.
2. check if EC's RO image can boot from loader.
3. use EC console command, "sysjump RO/RW" and check if it works.
4. Verified in Cyan and Kunimitsu.
BRANCH=none
Change-Id: Ie4daf44cdba944e3e58894ca80183fcdb0fdbc7c
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/302149
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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PMIC configuration for VCCIO decay and mask PowerGood of some rails
BUG=none
TEST=Fab3 with new LSW for VCCIO
check if VCCSTG is off / on as SLP_S0 is off and on.
is pressed.
BRANCH=master
Change-Id: I00a131171354b3579d40309af700794a6b151f9d
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/302148
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This makes sure to clear all segments before turning on lightbar
for tap for battery. Without this, the previous colors are stored
and flash briefly before starting the tap for battery pattern.
BUG=chrome-os-partner:45835
BRANCH=smaug
TEST=tested on ryu. go to s5, type 'lightbar seq tap' and see that
the tap sequence starts without first blinking google colors.
note that this doesn't affect samus because for samus in s5, the
lightbar is not powered, so when we do tap for battery, we first
power the lightbar and the registers are cleared.
Change-Id: Ic7ae8c580005e786ba35656d8feeedac56e35cfd
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302147
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 962d0b2595b1dbb5ef162b7e6b4db7ce8a65e6c5)
Reviewed-on: https://chromium-review.googlesource.com/302447
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Fix max brightness for Ryu. The max brightness must be less than
0x80 because the top bit in the lightbar current registers is
reserved. Writing the top bit seems to have undefined behavior.
This fixes the hiccups in the tap for battery sequence which was
ramping brightness to above 0x80 and producing weird results.
BUG=chrome-os-partner:45835, chrome-os-partner:44029
BRANCH=smaug
TEST=test tap for battery looks smooth.
test that the google colors match the desired current levels:
> lightbar
...
15 0f 06
16 0f 20
17 16 08
18 06 21
19 26 11
1a 1d 0b
Change-Id: Iecf1c770f986064b9b4d2d3d54fab0ea1242af01
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302146
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 133dab0c36160d0e54820cce9e97071df34340f8)
Reviewed-on: https://chromium-review.googlesource.com/302446
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1. ret always evaluated to INVALID_PARAM and so SET_ACTIVITY bailed out
early and returned an error to host command.
2. No need to verify sensor id since SET_ACTIVITY / LIST_ACTIVITIES
identify the correct sensor to operate on.
BUG=chrome-os-partner:45710
BRANCH=None
TEST=Compiles successfully. Disable double-tap works as expected.
Change-Id: I58ae9cd5009fadedb3ea78a4eec0452124747707
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/301990
Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2a3a120c8f7cca1e032f4be2a198748f0e8b5fb1)
Reviewed-on: https://chromium-review.googlesource.com/302409
Commit-Ready: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
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Swap the charge detector i2c ports since the association between pericom
chips and ports seems backward.
BUG=chrome-os-partner:45118
TEST=Plug usb2 keyboard into usb-c port through A-C adapter, verify
keyboard is functional.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I7c78dc5f915126bb61cf27543ea1626c831e5981
Reviewed-on: https://chromium-review.googlesource.com/300643
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Ryan Lin <ryan.lin@intel.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Do not charge below 5 C or above 50 C.
Still charge at 0.1C between 5 C and 10 C.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:45631
TEST=none
Change-Id: I6788088054ef4a5eb176eb2185b5e1c576128e09
Reviewed-on: https://chromium-review.googlesource.com/302232
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Since CONFIG_RO_SIZE and CONFIG_RW_SIZE now exist (which may
theoretically be different sizes), it is no longer useful to globally
define the size of an image.
BUG=chromium:535027
BRANCH=None
TEST=`make buildall -j`. Also, verify glados / glados_pd continue to
function as expected.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie29959923bc5d02b4d7d6d507ff2191bcb7d24c8
Reviewed-on: https://chromium-review.googlesource.com/301743
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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Code has been added to not send data to AP ring when the
AP does not want data, but we should still enable the BMI160 FIFO if the
EC wants the data.
BRANCH=smaug
BUG=chromium:513458
TEST=Disable sensor at AP (sysfs frequency) enable in EC (accelrate).
Check with accelinfo we are collecting sensor info.
Change-Id: I962fecad0e8cea899e4d788d25982e8bc7e7fb88
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/301795
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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We have been using the time of compilation to determine the
version string. This CL will keep doing that if the git repo has
uncommitted changes, but if the repo is clean we'll just use the
author date of the last commit. This ensures that the same source
will produce bitwise-identical builds (assuming no toolchain
changes, of course).
BUG=chrome-os-partner:45616
BRANCH=none
TEST=manual
cd src/platform/ec
make buildall
mv build build.one
make buildall
md5sum build{,.one}/*/ec.bin | sort
Observe that successive builds produce identical binaries.
Change-Id: Ie2ef44b216586097589c9c15f12e05c87a53f991
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302140
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Make sure to restore boot_mode gpio for all MCUs. Previously,
only usbpd_boot_mode was restored, but not ec_boot_mode which
is used on lucid.
BUG=none
BRANCH=none
TEST=flashed lucid (ec_boot_mode), glados_pd (usbpd_boot_mode),
and zinger (boot_mode) and verified that the boot_mode gpio was
restored to off at the end of flashing.
Change-Id: Ib6fcddcac6d00465e31a0e710bae3b8318bac659
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/301338
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
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Similar to i2c_xfer: allow access to a SPI device registers.
We assume the protocol use is set MSB bit to the offset for read
operation.
id is the index of the device in spi_devices.
BRANCH=smaug
TEST=Read/Write SPI registers.
BUG=none
Change-Id: Id4aaffbb6f514fd47086aee240b556ea23298d33
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289857
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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The board-specific board.h defines things like this:
#define CONFIG_RO_SIZE 1000
#define CONFIG_RW_SIZE 1000
#define CONFIG_SHAREDLIB_SIZE 200
And in the linker scripts we define some preprocessor macros like
so:
#define FW_SIZE_(section) CONFIG_##section##_SIZE
#define FW_SIZE(section) FW_SIZE_(section)
So that we can say things like this:
FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
Note that we have to use FW_SIZE, not FW_SIZE_
The difference is only noticeable when SECTION is #defined. If
${CFLAGS} has
-DSECTION=RW
Then the expansion is this:
FW_SIZE_(SECTION) => CONFIG_SECTION_SIZE
FW_SIZE_(RW) => 1000
There's no difference in the output for this particular CL, but
we should use the correct macro anyway to avoid confusion.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I61edc76a1aaeb1c675b384371700f37dda39ed47
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302150
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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spi_devices array needs the SPI master port used.
It is defined as CONFIG_, use it.
BUG=none
BRANCH=smaug
TEST=Check the sensors still work.
Change-Id: I6ce978caa32f4135dced59417a81ae280777fe57
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302021
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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