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* motion: Remove duplicate shutdown codeGwendal Grignou2015-10-284-16/+8
| | | | | | | | | | | | | | | | | Call shutdown() entry point at init() and remove duplicate code. shutdown would init the sensor so they would be ready if needed. Set S5 flag to include G3 (hard off) state, not only S5 (soft off). BUG=chrome-os-partner:45722 BRANCH=smaug TEST=When doing a RO->RW transition while AP is in G3, check the sensors are initialized properly. This issue was found while testng the magic sequence code. Change-Id: I647f83580240bf5ba0c340fca3184220abe4c12e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308561 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* driver: si114x: Fail init of proximity sensor if light sensor fails.Gwendal Grignou2015-10-282-1/+4
| | | | | | | | | | | | | | | | If init of the light sensor fails (for instance, the chip is not present on the i2c bus), we need to fail the init of the proximity sensor. Otherwise, the EC will report an unexistent sensor to the AP. BRANCH=smaug BUG=chrome-os-partner:46638 TEST=check the proximity sensor is not reported if sensor is disconnected from the main board. Change-Id: Ie6b1d74eaac4d6c38d52641626966b5d3ce63bd3 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308560 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* driver: bmi160: Add magic sequence to unlockGwendal Grignou2015-10-271-1/+12
| | | | | | | | | | | | | | | | | | | | | | If init() is interrupted while we are setting the link to the compass, the BMI160 may be in paging mode and will only answer to registers 7Eh and 7Fh. Other registers access will return 00h. To get out of this state, run the sequence to move back from the paging mode in the error handler. If successful, a subsequent call to init() will work. BRANCH=smaug BUG=chrome-os-partner:45722 TEST=use a special firmware that exists in the middle of the compass init sequence. Check that the FIFO and all other registers return 0. Issue 'accelinit 1' (to reset the Gyro): the command succeeds and the accelerometer is operational again (double tap works). Check the sequence can be issued after sysjump to RW/RO. Change-Id: I3455a8cbdcf1c88699ae90f7c09e4438e1268d47 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308184 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Remove cyan ec configurationBernie Thompson2015-10-2710-789/+0
| | | | | | | | | | | | | | We no longer need to build cyan on ToT, so we can remove it. BUG=chrome-os-partner:44576 TEST=None BRANCH=None Change-Id: Ifaad4570cb8e1c427e0c341073e4bacd29462974 Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/309000 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charger: Add LIMIT_POWER charger param for low bat + weak chargerShawn Nematbakhsh2015-10-277-3/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for two new configs to specify critical energy battery percentage and critical external charger power. When we are under both thresholds, set the LIMIT_POWER charger parameter to inform the AP that it should conserve power to avoid brownout, and consider jumping to EC RW to negotiate PD. In addition, modify the existing CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON to allow power-up regardless of power level if a 15W+ charger is attached, since there is a reasonable chance it may speak PD and provide sufficient power to boot the AP. BUG=chromium:537269 TEST=Manual on Glados. Set CHG_MW thresh to 20000, BAT_PCT to 50. Verify that LIMIT_POWER charger param is set until Zinger negotiates to 20V. Also veify that system can boot with Donette. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic963c82fea4ad10e8a5d7e476c5ce3e5ae525dad Reviewed-on: https://chromium-review.googlesource.com/306774 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* i2c: get battery information from charge stateMary Ruthven2015-10-276-4/+90
| | | | | | | | | | | | | | | | | | ARM systems currently use SBS kernel driver which talks to the battery through I2C passthu in the EC. Instead when asking for battery information try getting it from the charge state machine first, and then try the battery if charge state does not have the information. This reduces latency by cutting out the battery response time. BUG=chromium:484841 BRANCH=none TEST=check that power_supply_info works properly on Jerry Change-Id: If4da15ccabe412adc31fc94b189089ebb3e9265c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307905 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* chell: Set SPI flash chip to W25X40Duncan Laurie2015-10-271-1/+1
| | | | | | | | | | | | | | Chell was still set to use W25Q64 instead of the W25X40 that is actually on the board. BUG=chrome-os-partner:46289 BRANCH=none TEST=successfully run "flash_ec --board=chell" Change-Id: If21e5f9a00600c97d81d2bb2a8700801ae5c2fd6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308727 Reviewed-by: Shawn N <shawnn@chromium.org>
* flash_ec: Add support for flashing chell PDDuncan Laurie2015-10-271-2/+3
| | | | | | | | | | | | | Add chell_pd to the STM32 list and the USBPD override list. BUG=chrome-os-partner:46289 BRANCH=none TEST=successfully run "flash_ec --board=chell_pd" Change-Id: Ic4ddbe51a0586c563211fd76f20a85428e565546 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308726 Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: gpio - remove comment about E4Dino Li2015-10-251-2/+0
| | | | | | | | | | | | | | | | | E4 pin has two output options, INTC WKO25 and WKO114. We can use any of them. So we enable E4's output to INTC WKO114. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make buildall -j Change-Id: I1c24d3f5aa7c5ca0fc90fcafc3f0a5edc237ce53 Reviewed-on: https://chromium-review.googlesource.com/307215 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: Increase DLM sizeDino Li2015-10-253-10/+22
| | | | | | | | | | | | | | | | 1. Total DLM size is 48KB. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=DLM 0x84000 ~ 0x8BFFF read/write OK. Change-Id: I2340aeefca60ad59062254ddd363c703c30cfd24 Reviewed-on: https://chromium-review.googlesource.com/307006 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix clock moduleDino Li2015-10-2512-37/+399
| | | | | | | | | | | | | | | | | | | | 1. Implement deep doze mode for CONFIG_LOW_POWER_IDLE. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=test the following items in deep doze mode. 1. WUI interrupts wake-up OK. (For example, power button, lid, uart rx, keyboard ksi, and so on) 2. LPC access interrupt wake-up OK. 3. Enabled Hook debug, no warning message received (48hrs). Change-Id: I8702a112632cb6c1c0fa75d682badf272130a7d4 Reviewed-on: https://chromium-review.googlesource.com/307060 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* glados: oak: reboot EC if PD MCU crashesAlec Berg2015-10-235-21/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If PD MCU crashes, it will go back to RO code and stay there until the next AP boot. So, if EC detects PD has crashed, then EC should panic reboot with debug message that it detected a PD crash. PD MCU crash is detected by EC by seeing the PD MCU transition from RW to RO, without it setting the flag that it got there from a sysjump. This CL also makes minor changes to oak_pd and glados_pd board.c files to make them identical, other than the few minor real differences between them. BUG=none BRANCH=none TEST=tested on glados using pdcmd console command on EC to test sysjumps and reboots: sysjump to RW: pdcmd 0xd2 0 2 0 sysjump to RO: pdcmd 0xd2 0 1 0 cold reboot: pdcmd 0xd2 0 4 0 Verified that PD can jump back and forth between RO and RW without EC panicing. Verified that if PD MCU is in RW and reboots, then the EC will panic and print 'PD crash'. Verify if PD MCU reboots while in RO, without ever going to RW first, then EC does not panic. Change-Id: Id3191f4005e70a6c61a9322bf535b4374e85eb9a Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308586 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: remove unnecessary delay in phy initAlec Berg2015-10-231-1/+1
| | | | | | | | | | | | | | Remove unnecessary 250ms delay in USB PD phy init BUG=none BRANCH=none TEST=test on glados and samus. verify we negotiate with zinger after EC or PD reboots. Change-Id: I561e41fb0b8bbfeacdd7d6a9ceaf67a1606f65e5 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308535 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: fix lid close detectionVincent Palatin2015-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now we are using LID_OPEN *and* BASE_PRES_L for lid close detection, we need an interrupt on both to debounce arbitrarily long delay between the transitions of the 2 GPIOs. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:46189 TEST=manual: activate manually LID_OPEN and BASE_PRES_L hall sensors in very slow sequences and see the proper "lid close"/"lid open" traces, whatever sequence I do. Reviewed-on: https://chromium-review.googlesource.com/308513 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 659d826b4efcd391eced3d4dda319d502d028457) Change-Id: I2ee91370205a4bfc0f4b4d224cb55207f745af25 Reviewed-on: https://chromium-review.googlesource.com/308515 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* ryu: do not pull EN_PP3300Vincent Palatin2015-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Modify the former workaround for board revisions missing an external pull-up to 1.8V on EN_PP3300 : the 100kOhm resistor between GPE13 and EN_PP3300 is still stuffed even on boards which don't need the workaround, so tri-state the pin to avoid driving the net. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:46799 TEST=probed EN_3300 voltage level. Change-Id: I48f2b2fa9a716cdbe07fbc8a006ba4d3fcfaa63d Reviewed-on: https://chromium-review.googlesource.com/307868 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 53e49d6d6541183349bb7267fa5ec2b1db250d99) Reviewed-on: https://chromium-review.googlesource.com/308514 Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* common: lightbar: Add histeresis to prevent flickeringGwendal Grignou2015-10-236-23/+96
| | | | | | | | | | | | | | | | | | | | | | | When ALS is enabled, if light is around one threshold (say 40 lux), the lightbar will flicker between readings. Add a histeresis to prevent the flickering. The current setting is: setting ^ (dim) 2 | ------+---->---+ 1 | +----<---+--->---+ (bright) 0 | +---<---+--------- +-------+--------+-------+--------> lux 20 40 60 BRANCH=smaug BUG=chrome-os-partner:44400 TEST=check in a dark room (30~40 lux) there is no flickering. Add unit test. Change-Id: I4018e2c2ed764abf9c9ed28e2d50a3e94a7d5f75 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308205
* board: ryu: Compass and Gyro stays up in S5Gwendal Grignou2015-10-231-2/+2
| | | | | | | | | | | | | | | | | Gyro and compass is suspended but still powered on. Therefore they don't need to be reinitialized. Note that their init() does not do much, most is done when initializing the accelerometer part of the BMI160. BRANCH=smaug BUG=none TEST=Check that Gyro: MS Done Init... message are not present when powering up the system in a loop. Change-Id: If92727830c32407df49213db46b1d5f1cb0369af Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308204 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Remove CONFIG_PORT80_TASK_EN from boards.Aseda Aboagye2015-10-238-8/+0
| | | | | | | | | | | | | | | | | | There is no port 80 task for the MEC1322 anymore, therefore no board should be using this define. I forgot to remove these at the time. BUG=None BRANCH=None TEST=make -j buildall tests CQ-DEPEND=CL:308450 Change-Id: Ie44474470edb40bc94ec95be9663b509e0ba299a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/308451 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lars: remove port80 taskAlec Berg2015-10-231-2/+1
| | | | | | | | | | | | | | The port80 task has been removed recently and replaced with a timer interrupt (CL:305591). Fix lars to match the new scheme. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I602ef1306b9889732e77cbb32753ca0286123e2b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308450 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* glados: chell: add VCONN swap abilityAlec Berg2015-10-234-0/+20
| | | | | | | | | | | | | | | Add VCONN swap ability and accept VCONN_SWAP requests as long as we have the ability to provide VCONN. BUG=none BRANCH=none TEST=test on glados. ask for vconn swap and make sure vconn swap is successful. Change-Id: I7340e6253dcde4cdbe333a9622d7826e7ccbe6b4 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308238 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: change battery and variable sink cap for voltage inaccuracyAlec Berg2015-10-2310-20/+18
| | | | | | | | | | | | | | | Change battery and variable sink capabilities for all boards to account for +/-5% voltage inaccuracy. BUG=none BRANCH=none TEST=test glados with third party variable power supply and make sure it see's our sink capabilities as 4.75V-21V. Change-Id: I2481ccbe6c47bfed1a6b8b237329e70bd0f8e4ac Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308237 Reviewed-by: Todd Broch <tbroch@chromium.org>
* pd: send soft reset on boot if VBUS is presentAlec Berg2015-10-234-49/+41
| | | | | | | | | | | | | | | | | | | | | | On boot, if VBUS is present, then when PD protocol gets to SNK_DISCOVERY state, if it times out waiting for source cap, then send attempt to send a soft reset first instead of directly sending a hard reset. This allows us to not lose VBUS in the case that we were in a stable contract as a sink before this boot (for example a sysjump or EC reboot). BUG=chrome-os-partner:44085, chrome-os-partner:44952 BRANCH=none TEST=test on glados and samus. test by sysjumping between RO and RW with zinger plugged in and no battery, and verify that we don't lose power. also test rebooting with a battery and verify we don't lose power. also tested with a third party PD charger. Change-Id: Ib7ce46d8b9843db66805ba3237d8919d611324e0 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308201 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: revise suspend gpio setting for rev4YH Huang2015-10-231-0/+4
| | | | | | | | | | | | | Revise gpio setting of suspend signal for rev4 hardware. BUG=chrome-os-partner:46579 TEST=run "make BOARD=oak -j" and enable SW sync in bootloader EC SW sync works fine. Change-Id: I8864dfaa8ae7ef9a47d0a08499d88eb8999160c5 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/308351 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: stm32f0: implement i2c_set_timeoutRong Chang2015-10-232-8/+16
| | | | | | | | | | | | | | | EC communicates with PD through I2C host command. This CL adds i2c_set_timeout implementation. BRANCH=none BUG=chrome-os-partner:41608 TEST=manual build and load on oak, check PD host command. Change-Id: I05259b40223b435eaf2a0c38954573e97ea4b32b Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306909 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Cr50: Support USB on 15MHz FPGA imageBill Richardson2015-10-222-13/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest Cr50 FPGA release runs at 15MHz, but supports USB operations. This CL includes changes to make that work. Specifically: * Enable the security features and select the correct PHY * Adjust the turnaround time for the slower clock speed * Handle the SET ADDRESS command specially for this SoC * Remove all printfs from interrupt handlers (but add #ifdef code to print debug messages later if desired). BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual test of Cr50 USB: 1. Plug into a USB jack on a Linux host. 2. In src/platform/ec/extra/usb_console, run make ./usb_console -p 5014 -e 1 3. Type something, hit return 4. See whatever you typed come back with swapped case 5. ^D to quit Change-Id: I848e96d19df056a453d30d4b5537481046fe852d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308062 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Lars: Init boardRyan Zhang2015-10-2213-1/+1590
| | | | | | | | | | | | | | | | | Preparing for new board, Lars Copy kunimitsu setting to init board. BUG=none BRANCH=lars TEST=Run "make -j BOARD=lars", "make -j BOARD=lars_pd" and "make buildall -j" to build code and ec.bin can be generated. Change-Id: Ic0ab3e57679fc7ea98a7b73527ce2276e706db1d Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/305128 Commit-Ready: 志偉 黃 <David.Huang@quantatw.com> Tested-by: 志偉 黃 <David.Huang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* flash_ec: Use the chip name to check stm32 boardTom Wai-Hong Tam2015-10-221-28/+27
| | | | | | | | | | | | | | | | | FAFT and the lab infra calls the flash_ec by giving the chip name as an argument, instead of the board name. The script should use the chip name to check if it is a stm32 board. BUG=chromium:546063 BRANCH=none TEST=Call the script: flash_ec --chip stm32 --image /tmp/ec.bin Change-Id: I8e9a029fb6e0aca5ea0f65876f48f6f465664c1c Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307822 Commit-Ready: Wai-Hong Tam <waihong@chromium.org> Tested-by: Wai-Hong Tam <waihong@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* tcpc: re-initialize tcpc if it reboots while tcpm is runningAlec Berg2015-10-226-28/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | On TCPC startup, set an alert to notify TCPM that we have been reset. When TCPM gets this notification, it should re-send initial TCPC parameters. If we were in a stable contract as a sink, make sure we don't reset connection. If not, then reset PD protocol state machine to the default state. This fixes a bug where if the TCPC reboots while the TCPM is still running, then the TCPC would not get re-initialized and therefore no PD communication would not work. This also fixes it such that if we are in a stable contract as a sink and the TCPC reboots, then we don't lose power. BUG=chrome-os-partner:46676 BRANCH=none TEST=tested on glados. reboot PD MCU with and without a charger plugged in and verify that PD communication works after the reboot. verify that with a charger, we don't lose power. also tested with a hoho plugged in during reboot. Change-Id: I84fec4577b0daf5891bd8461d3f3d925014a5ecf Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307187 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Support FPGA image m3.dist_20151021_054409Bill Richardson2015-10-229-2514/+2915
| | | | | | | | | | | | | | | | This enables support for a new FPGA image with tighter timing constraints. Some USB functions perform better using this model. There are also changes to the signing code. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall Change-Id: I608c2424d76b4ea566bf56fa0fed3810436216bb Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308063 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ps8740: Make revision check a minimum instead of explicit valueDuncan Laurie2015-10-211-1/+1
| | | | | | | | | | | | | | With a new PS8740 chip revision 0xb the explicit check for 0xa is failing. Change this to allow revisions >= 0xa to pass. BUG=chrome-os-partner:46728 BRANCH=none TEST=boot on chell and confirm lack of mux init errors Change-Id: I0847bb9953920569922183ed4c83da2370ef40e4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307932 Reviewed-by: Shawn N <shawnn@chromium.org>
* flash_ec: Add chell and lars boardsDuncan Laurie2015-10-211-0/+2
| | | | | | | | | | | | | Add chell and lars to the mec1322 board list. BUG=chrome-os-partner:46289 BRANCH=none TEST=flash_ec --board=chell Change-Id: Ia89e4914086d01150fab8abe2877a7583cf0af44 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307931 Reviewed-by: Shawn N <shawnn@chromium.org>
* Kunimitsu: Add support to enable L3GD20H gyrometerVijay Hiremath2015-10-212-0/+46
| | | | | | | | | | | | | | | BUG=none TEST=Enabled the config to test the L3GD20H sensor. Able to read the gyro data from "accelinfo" console command. Rotated the sensor in X,Y,Z axis, respective axis values change. BRANCH=none Change-Id: Ib1b06bffaf4f5f33d87b9062a1eb22658d3c9987 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/307234 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* kunimitsu: enable USB-A port power controlKevin K Wong2015-10-212-4/+5
| | | | | | | | | | | | | | | dumb mode is used since kunimitsu ec only have control over the two usb-a ports' power enable/disable functionality. BUG=none BRANCH=none TEST=verified with "ectool usbchargemode <port 0-based> <0=dis, 4=en>" and check with DMM to see if +5V is toggled when enabled/disabled. Change-Id: I122c99b4067a873313b892715078188e800b979a Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/307476 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* common: Add lightbar dimming based on outside light.Gwendal Grignou2015-10-206-7/+97
| | | | | | | | | | | | | | | | Unless the lid is closed, the ALS is used for lightbar dimming. Change the google colors depending on the light sensor result. BUG=chrome-os-partner:44400 BRANCH=smaug TEST=Check all 3 levels of brightness of the lightbar. Check value using "adb shell ectool lightbar" Check double tap color are not affected and is using full brightness. Change-Id: I7b5e2890c3557f1dd3ae719f5f82ffb5fe7b24fb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/301216 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lightbar: define primary colorsGwendal Grignou2015-10-201-9/+18
| | | | | | | | | | | | | Use defines for color entries 4 - 7. BRANCH=smaug BUG=none TEST=compile Change-Id: I2fe9b286adbb4e2cc471320ccd3d0437b451a7cc Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306787 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* driver: Add L3GD20H gyrometer basic driver supportBolat Dinc2015-10-205-0/+546
| | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:40465 BRANCH=None TEST=Added Gyro config to test L3GD20H Gyro sensor in Kunimitsu. Able to read the gyro data from "accelinfo" console command. Rotated the sensor in X,Y,Z axis, respective axis values change. Fits into the existing accel/gyro framework. Change-Id: I19369560ddad5160c2fc9c7ef9823bd37b5389fa Signed-off-by: Bolat Dinc <bolat.dinc@intel.com> Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/264650 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* oak_pd: reduce image size and build full RO and RWAlec Berg2015-10-202-8/+22
| | | | | | | | | | | | | | | | | | | | | | | Modify oak_pd to build a full RO and RW binary. Note that in order to fit RO and RW into the small flash size, this CL removes the console task and adds one-way debug printfs to save space. For debugging purposes, you add the console back in by uncommenting the CONSOLE task in ec.tasklist. This will build an RW image only that has a full console. BUG=chrome-os-partner:41959 BRANCH=none TEST=load on oak_pd and verify host commands from EC work and charging with zinger works. also test that software sync works. Change-Id: I54f7263599684cab333c62796edf57837fe43469 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307032 Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Kunimitsu: Enable motion_sense_taskstabilize-smaug-7566.Bli feng2015-10-191-0/+1
| | | | | | | | | | | | | | | | More code space is available so enable motion task. It helps reduce sensor power consumption. BUG=none TEST=make buildall -j BRANCH=none Change-Id: Ifc41ab3fe72a9d2b4669fea035aa6199be43e860 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/306789 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc: Remove unnecessary NPCX_EC_FLASH_SIZE definition in npcx.Mulin Chao2015-10-192-18/+11
| | | | | | | | | | | | | | | | | | | Remove NPCX_EC_FLASH_SIZE definition and replace it with CONFIG_FLASH_SIZE. Due to inconsistence between NPCX_EC_FLASH_SIZE and CONFIG_FLASH_SIZE, some flash commands such as flasherase will cause unexpected results. Modified drivers: 1. config_flash_layout.h: Remove NPCX_EC_FLASH_SIZE definition. 2. flash.c: Replace NPCX_EC_FLASH_SIZE with CONFIG_FLASH_SIZE. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Idca286eef5bb014d5c4cd689c39635e09f40ee03 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/307004 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Abort curr DMA xfer in dma_disable_all().Aseda Aboagye2015-10-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | When we call dma_disable_all(), we should abort any current transaction on a channel in addition to disabling the channel. Simply disabling the channel will ignore any future requests, but a DMA operation may be ongoing. Lastly, soft-reset the block so that it's a clean state next time we want to use it. BUG=None BRANCH=None TEST=Enable CONFIG_REPLACE_LOADER_WITH_BSS_SLOW on GLaDOS and add a few items to the section. 'sysjump' between RO and RW a few times without encountering a forced hard fault. TEST=make -j buildall tests Change-Id: Ia05702b928fbb12265b16d785b6e6dac09807582 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/306915 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: move tpm2 stubs.c file to this repositoryVadim Bendebury2015-10-192-1/+580
| | | | | | | | | | | | | | | | It makes much more sense to keep the stubs locally: they use this platform's hardware, there is no need to edit two packages when a stub is replaced with a real implementation. CQ-DEPEND=CL:306709 BRANCH=none BUG=chrome-os-partner:43025 TEST=the code still builds Change-Id: I7a0e180627950cee8cc51600dfffd1a9180a3bcf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307043 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* port80: Remove HAS_TASK_PORT80.Aseda Aboagye2015-10-192-68/+0
| | | | | | | | | | | | | | | | | | | | | | The only boards that had a port 80 task were the ones using the MEC1322. Since that EC now has a dedicated timer interrupt configured for port80 writes, we can remove this code that was providing the port 80 task. Additionally, the config option CONFIG_PORT80_TASK_EN is removed. BUG=chrome-os-partner:46062 BRANCH=None TEST=make -j buildall tests CQ-DEPEND=CL:305591 Change-Id: I145d989b8872240e749ef77aabe0ae76fc94d443 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305791 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Change the Port 80 task to a timer IRQ.Aseda Aboagye2015-10-1910-14/+91
| | | | | | | | | | | | | | | | | | | | | | The port 80 task just polls every 1ms until disabled when the system goes into suspend. Therefore, this commit configures a 1ms timer interrupt that will be used for the port 80 writes instead of using an entire task. This saves task stack space as well as context switches. BUG=chrome-os-partner:46062 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS and verify using the `port80' console comamnd that there are bytes in the port80 history. TEST=make -j buildall tests Change-Id: I65b48217a638c1f6ae1ac86471f9a98e0ec4533a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305591 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* glados_pd: reduce image size and build full RO and RWAlec Berg2015-10-193-4/+25
| | | | | | | | | | | | | | | | | | | | | | Modify glados_pd to build a full RO and RW binary. Note that in order to fit RO and RW into the small flash size, this CL removes the console task and adds one-way debug printfs to save space. For debugging purposes, you add the console back in by uncommenting the CONSOLE task in ec.tasklist. This will build an RW image only that has a full console. BUG=chrome-os-partner:41959 BRANCH=none TEST=load on glados_pd and verify host commands from EC work and charging with zinger works. also test that software sync works. Change-Id: I57895d12a1776a865aac1735aeb0aa8897f1779e Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306784 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f05x: Use correct erase block size of 1kBAlec Berg2015-10-191-1/+1
| | | | | | | | | | | | | | Change erase block size to the correct 1kB. BUG=chrome-os-partner:41959 BRANCH=none TEST=with following CL, test software sync to PD MCU on glados. Change-Id: I6252e6344e50f00249ab105a90febd15599c936f Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307042 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* glados_pd: oak_pd: add and enable option for i2c slave onlyAlec Berg2015-10-197-4/+11
| | | | | | | | | | | | | | Add CONFIG_I2C_SLAVE_ONLY for boards that only operate as a slave on i2c. BUG=chrome-os-partner:41959 BRANCH=none TEST=make BOARD=glados_pd and see 2kB flash savings Change-Id: I30831ce48b391d985c25e266229d5c6f2312042b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306783 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add synchronous debug printfAlec Berg2015-10-1912-48/+128
| | | | | | | | | | | | | | | | | | Allow use of a synchronous debug printf instead of using the full console task to save space. This can be turned on with CONFIG_DEBUG_PRINTF, and will provide essentially a one-way console for debugging. This is essentially expanding upon the debug_printf work done for zinger. BUG=chrome-os-partner:41959 BRANCH=none TEST=tested with following CLs on glados_pd by verifying we get a one-way console. Change-Id: If028b5d873261890de5b270bbc00e06bdcaa7431 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306782 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Provide interface to random number generatorVadim Bendebury2015-10-173-8/+50
| | | | | | | | | | | | | | | | | | | | | It needs to be possible to retrieve an arbitrary number of random bytes, which is accomplished by this _cpri__GenerateRandom() implementation. Also, this patch rearranges the board initialization code to initialize both interrupts and the TRNG. CL-DEPEND=CL:306781 BRANCH=none BUG=chrome-os-partner:43025 TEST=ran a couple of tests retrieving random numbers from TPM, observed randomly looking values generated (this is not a validation of the TRNG implementation). Change-Id: I6314cdf5e6e96443b3fadb7f1502fc8477c41d0f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306780 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: enable modificaton of flash bank 1Bill Richardson2015-10-171-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Security settings prevent flash updates by default. This allows erase and writes to flash bank 1 (0x80000 - 0xbffff). Note that this doesn't allow for execution of any code you might put there. That requires additional steps which are not part of this CL. BUG=chrome-os-partner:44745 BRANCH=none TEST=manual Pick an unused section of flash and use the flasherase and flashwrite commands to test it. The flashwrite command fills a buffer with bytes, counting up (0x00, 0x01, 0x02, 0x03, ...), then writes that buffer to the address given. Note that the "md" command uses the absolute address, while the flash commands use the offset address within the flash memory. For example: > md 0xbb000 16 000BB000: ffffffff ffffffff ffffffff ffffffff 000BB010: ffffffff ffffffff ffffffff ffffffff 000BB020: ffffffff ffffffff ffffffff ffffffff 000BB030: ffffffff ffffffff ffffffff ffffffff > flasherase 0x7b000 0x800 Erasing 2048 bytes at 0x7b000... > md 0xbb000 16 000BB000: ffffffff ffffffff ffffffff ffffffff 000BB010: ffffffff ffffffff ffffffff ffffffff 000BB020: ffffffff ffffffff ffffffff ffffffff 000BB030: ffffffff ffffffff ffffffff ffffffff > flashwrite 0x7b000 0x800 Writing 2048 bytes to 0x7b000... > md 0xbb000 16 000BB000: 03020100 07060504 0b0a0908 0f0e0d0c 000BB010: 13121110 17161514 1b1a1918 1f1e1d1c 000BB020: 23222120 27262524 2b2a2928 2f2e2d2c 000BB030: 33323130 37363534 3b3a3938 3f3e3d3c > md .b 0xbb000 16 000BB000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f > Change-Id: Ia9fb6415bcc65ab92cab8132d8cf615215804a6d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306687 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Kunimitsu: PMIC: Keep the emergency reset time to defaultVijay Hiremath2015-10-171-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Keeping the emergency reset time to default (31s) as the EC/PCH can handle the 8sec emergency shutdown. Reverting the below patch. https://chromium-review.googlesource.com/#/c/298148/. BUG=none BRANCH=none TEST=Manually tested the following. 1. Hold the powerbutton for >4s && <31s device enters to S3, S5 & SOC G3. 2. Hold the power button for >31s deive enetrs to S3, S5, SOC G3 & PG3. 3. From the Kernel console entered "stop powerd", hold the power button for >10s && <31s device enters to S3, S5 & SOC G3. Change-Id: I6db44bb4b9f6d64ff3b1d7677c54401971b534c3 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/306733 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
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