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* cr50: make use of byteorder routinesstabilize-7647.74.Bstabilize-7647.72.Bstabilize-7647.32.Brelease-R48-7647.BVadim Bendebury2015-11-154-52/+30
| | | | | | | | | | | | | | | | Use the previously introduced endian conversion routines in the driver and the TPM2 library. Use packed TPM message header structure to make it easy to access unaligned header fields. BRANCH=none BUG=chrome-os-partner:43025 TEST=the tpm startup command still succeeds. Change-Id: I03078481664858a19617e248f98cb20013c27445 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312585
* common: byte order conversion functionsVadim Bendebury2015-11-151-0/+38
| | | | | | | | | | | | | | | | | | | Support for various communications protocols requires the ability to convert between big and little endian representation of integers. This patch moves integer converting functions into the common scope and uses the built in functions available in ARM architecture. Since all today's ec platforms are running in little endian mode, the functions being added assume that the host is little endian. BRANCH=none BUG=chrome-os-partner:43025 TEST=none yet Change-Id: I55ad0c5c3fe9f30cb4ed8ae807b1f5e4a54b8b35 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312584 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* motion: fix oversampling formulaGwendal Grignou2015-11-152-42/+33
| | | | | | | | | | | | | | | | | Overly complex previous formula could lead the EC to throw all samples between 2 timestamps and put 2 event within one timestamp. That would confuse the kernel. If the motion sense task is delayed while this happen, the delta between the 2 samples could be so long that CTS test cts.SingleSensorTests would fail. BRANCH=smaug BUG=b:24367625 TEST=Loops of cts.SingleSensorTests pass. Change-Id: I29e6bf354ccb7ecf741a91116854d6abe07558dc Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312364 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chell: Add keyboard backlightDuncan Laurie2015-11-133-1/+19
| | | | | | | | | | | | | | Add keyboard backlight to PWM2. BUG=chrome-os-partner:47435 BRANCH=none TEST=test keyboard backlight on chell Change-Id: Iab6b1ef95fc1428f0f8ac8b1503956fd990c0b60 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312403 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pwm: Add option for alternate clock sourceDuncan Laurie2015-11-132-3/+13
| | | | | | | | | | | | | | | | | | | | | The PWM clock on some chips can be configured to use different sources, which will have a dramatic effect on the actual PWM frequency. In order to support a variety of devices attached to PWM outputs add an option to select an alternate source. This is then implemented on the mec1322 chip to use the 100kHz clock source for PWM which will allow it to drive a keyboard backlight at appropriate frequencies. BUG=chrome-os-partner:47435 BRANCH=none TEST=verify that kblight brightness can be changed on chell Change-Id: Ibe93a8e029baae5a2d5f520d590b0cc4ab9a7f93 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312509 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: do not try verifying RW integrityVadim Bendebury2015-11-131-1/+0
| | | | | | | | | | | | | | | | The bootloader now verifies the RW integrity, the EC facility needs to be disabled. BRANCH=none BUG=none TEST=the error message "RSA verify FAILED" is not prinetd at startup any more Change-Id: I80a0f9dfb844c80c5bd660eec7e37d9ea60b088c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312299 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* common: lightbar: update leds when neededGwendal Grignou2015-11-131-23/+32
| | | | | | | | | | | | | | | | In S0 state, update leds only when needed: add a variable in get_battery_level to indicate the colors need to be changed. BRANCH=smaug BUG=b:25510300 TEST=Check the traffic on the i2c bus notice less traffic coming from lightbar task in S0. Change-Id: I22dce35edd794424f6fbb607a0dbb495eb308897 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311756 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* motion: minium interval between motion task now a variableGwendal Grignou2015-11-134-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | On Ryu EVT2, where sensors share a 100kb i2c bus with other device, when the sensors set to their maximal frequency and sampling interval set to 5ms, the power management task would wait forever for the i2c lock. Increase the minimal amount of time the task can wait from 3ms to 8ms in that case. This is not an issue for Ryu PVT where the sensors are on a separate SPI bus. However, on EVT, when setting the accelerometer/gyro over 125Hz, EC won't be able to deliver the data in non-batched mode. BRANCH=smaug BUG=b:25510300 TEST=Without this change, an evt2 board would crash when plugging/unplugging the charger while the sensors are set with: echo 200000 > iio:device0/frequency # Accel echo 5 > iio:device0/sampling_frequency echo 200000 > iio:device1/frequency # Gyro echo 25000 > iio:device2/frequency # Mag Change-Id: Idb30da9ab8da61284388db73365c37be3a250dec Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311755 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* motion: cleanup include fileGwendal Grignou2015-11-123-8/+5
| | | | | | | | | | | | | | Use test_export_static for static variable/function that needs to by used by tests/motion_lid.c BRANCH=smaug BUG=none TEST=Compile, make buildall -j Change-Id: I2f3eb72ce319622842885be9125b91e58f47133a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311754 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Lars: update LED controlRyan Zhang2015-11-123-61/+110
| | | | | | | | | | | | | | | | Following Cyan settings of https://chromium-review.googlesource.com/#/c/272815/ BUG=None BRANCH=lars TEST=`make buildall -j` Change-Id: Idb973363b047eb309ef0ddcfe84355f0b0409e2a Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/312151 Commit-Ready: 志偉 黃 <David.Huang@quantatw.com> Tested-by: 志偉 黃 <David.Huang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Add documentation for the TCPC microcontroller implementationMark Hayter2015-11-124-0/+119
| | | | | | | | | | | | | | | | Include text in markdown, png from Willis' block diagram, and the pdf schematic page extracted from the main schematic. BUG=chrome-os-partner:46903 TEST=markdown preview from emacs BRANCH=none Signed-off-by: Mark Hayter <mdhayter@chromium.org> Change-Id: I94d9b48fbe480c6ade837adb3984194fa2c738c5 Reviewed-on: https://chromium-review.googlesource.com/310554 Commit-Ready: Mark Hayter <mdhayter@chromium.org> Tested-by: Mark Hayter <mdhayter@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
* nds32: fix ldsDino Li2015-11-121-0/+1
| | | | | | | | | | | | | | | | | | symptom: .bss.slow won't be cleared during initialization. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=.bss.slow = 0. Change-Id: I6a8b84807b36a64f29732f09f56947e17d5ba898 Reviewed-on: https://chromium-review.googlesource.com/312155 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: modify uart ISRDino Li2015-11-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because UART interrupt is rising-edge triggered, and we need to clear UART IER and restore IER state to make sure interrupt can be triggered again when following situation occur: [ISR start] [process rx] [process tx] [ISR end] RX 0 1 0 1 1 TX 0 1 1 0 0 uart_int_event 0 1 1 1 1 uart_ier 1 1 1 1 1 uart_s1 (0 -> 1) 1 1 1 (keep high) uart_int_event = (RX | TX) uart_s1 = (uart_int_event & uart_ier) UART interrupt = (uart_s1 0->1) Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=fixed. Change-Id: I6498876780aba33795022fa6ecbb77e1c6468146 Reviewed-on: https://chromium-review.googlesource.com/311563 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cortex-m0: Ensure .bss.slow section is cleared.Aseda Aboagye2015-11-121-0/+1
| | | | | | | | | | | | | | | | | | The .bss.slow input section needs to be included before __bss_end, otherwise it won't get cleared to zero. BUG=None BRANCH=None TEST=Build jerry. Verify that __bss_end is at the end of the .bss.slow section. TEST=make -j buildall tests Change-Id: I41d028ee166d05b34a889499cdcb0254341be1b6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/312404 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* util: signer: cr50: use full flash addresses instead of segment addressesVadim Bendebury2015-11-121-18/+18
| | | | | | | | | | | | | | | | | | | | The code mixes up using of full flash addresses and flash segment addresses (full address divided by 16). The vast majority of uses in fact requires full addresses, but all definitions are using segment addresses. This patch converts definitions to full addresses, which improves overall code readability. BRANCH=none BUG=none TEST=verified that the signer signed image still boots properly on CR50. Change-Id: I35663c14357545c08ac1824d653c29cf6c4dda4d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311313 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* util: signer: improve debug output readabilityVadim Bendebury2015-11-122-4/+14
| | | | | | | | | | | | | | Assorted modifications which make it easier to follow debug output, when enabled. BRANCH=none BUG=none TEST=ran signer in verbose mode, observe improved debug output. Change-Id: Ieb2e7012342480217388dd5001b61ea95adf71a4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311312 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* glados/chell: drive PCH_RTCRST lowAaron Durbin2015-11-124-2/+6
| | | | | | | | | | | | | | The PCH_RTCRST signal is active high controlling the gate of a FET. Therefore, it's default state should be low. BUG=chrome-os-partner:47505 BRANCH=None TEST=Built. The FET is unstuffed on both boards currently. Change-Id: Ia0e07e67e6ea4eecf151ac8890ad98c8a337c01e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312061 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* nuc: Fixed wheatley bugs of SERIRQ and AC detection.Mulin Chao2015-11-117-35/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SERIRQ bug: PMC1/2 share the same IRQ number 1 with default setting. Enable it will influence 8042 protocols since KBC has no data but IRQ 1 is issued by PMC. AC detection bug: GPIO definitions between AC_PRESENT and ACOK mismatched. AC_PRESENT will always be high even we don't plug the adaptor. Modified drivers: 1. lpc.c: Remove enabling SERIRQ for PMC1/2 and disable IRQ12 for Mouse. 2. config_flash_layout.h: Modified for adjusting RAM size. 3. gpio.inc: Modified GPIO definitions for AC issue 4. board.h: Modified for adjusting RAM size and add support for ACC 5. board.c: Add support for ACC and adjust ADC max value BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ib330ef4078e4b06f1c01a2a6316e468b43d7a8d9 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/311933 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: port80: Add items to .bss.slow.Aseda Aboagye2015-11-111-3/+3
| | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:46056 BUG=chrome-os-partner:46063 BRANCH=None TEST=Enable CONFIG_REPLACE_LOADER_WITH_BSS_SLOW on GLaDOS. Build, flash, and verify AP and EC boot. Suspend/Resume and verify that port80 data is in the history. TEST='sysjump rw' suspend/resume nad verify that new port80 writes are present in the history. TEST=make -j buildall tests. CQ-DEPEND=CL:311209 Change-Id: Idebb3247b55465f1fbf35a33dff2f00968b8f4ce Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/311365 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add initial dcrypto AES implementation.nagendra modadugu2015-11-117-114/+433
| | | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=none Change-Id: I7c0e8f50fb786d62e4fe13ea19ddce1dba116408 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/309873 Commit-Ready: Nagendra Modadugu <ngm@google.com> Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* console: Add support for using EC-3PO console.Aseda Aboagye2015-11-114-1/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a new CONFIG_* option. To utilise the experimental console, simply define the following config option in the board's board.h file. #define CONFIG_EXPERIMENTAL_CONSOLE This is a temporary option which allows the EC console to be work with the EC-3PO interactive console interface. When this option is enabled, the EC expects commands to packed in a particular format. This is for command integrity and allows the interpreter to perform automatic command retrying in the event that a character is dropped from the sent command. It also removes a lot of the console editing methods since they are now being served by EC-3PO. Once the EC-3PO interpreter is pulled into servod, we can enable this feature by default and the config option can go away. BUG=chrome-os-partner:46054 BRANCH=None TEST=make -j buildall tests TEST=Enable CONFIG_EXPERIMENTAL_CONSOLE on GLaDOS; Flash EC and verify that console works via the EC-3PO interactive console interface. TEST=Build and flash on GLaDOS and verify normal console operation on standard EC UART. CQ-DEPEND=CL:308615 Change-Id: I5e66eb94e31299b27ce029b7f7ce6ba0a7fb6816 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/309991 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Lars: remove compile-time checks related to second PD portRyan Zhang2015-11-114-63/+15
| | | | | | | | | | | | | BUG=chrome-os-partner:47385 BRANCH=lars TEST=`make buildall -j` Change-Id: I4d786e59ffb85911bf1d923a1a37167fea4658fd Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/311510 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Lars: increase RO image sizeRyan Zhang2015-11-111-1/+1
| | | | | | | | | | | | | | Following kunimitsu setting of https://chromium-review.googlesource.com/#/c/310581/ BUG=None BRANCH=lars TEST=`make buildall -j` Change-Id: I4e58c581f7d3dfe4a6064a6d339806d543f41e23 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/311920 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Don't check for sink role if we're always a sourceShawn Nematbakhsh2015-11-111-1/+4
| | | | | | | | | | | | | | | PD_STATE_SNK_READY is defined only for CONFIG_USB_PD_DUAL_ROLE. BUG=None TEST=Compile for snoball BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I365cb698b6107a8b06fac7929370cc9c1a732d4e Reviewed-on: https://chromium-review.googlesource.com/311808 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* common: keyboard_scan: Add items to .bss.slow.Aseda Aboagye2015-11-111-12/+19
| | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:46056 BUG=chrome-os-partner:46063 BRANCH=None TEST=Enable CONFIG_REPLACE_LOADER_WITH_BSS_SLOW on GLaDOS. Build, flash, and verify that AP and EC boot. Perform typing test with no jank or other oddities. TEST='sysjump rw' and repeat the typing test. TEST=Hold down arrow down and issue 'reboot' command. TEST=make -j buildall tests CQ-DEPEND=CL:311209 Change-Id: I35911862af2a4e9feb795b2a9a2aafa97687e2f2 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/311411 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Fix gcc 5.2.1 compile errorsShawn Nematbakhsh2015-11-118-6/+11
| | | | | | | | | | | | | | | BUG=chromium:552006 BRANCH=None TEST=`make buildall -j` and also verify panic reporting works on glados_pd. Change-Id: Ic9f1ec6b5297389df0d46bb38a67c156901ed956 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311253 Commit-Ready: Shawn N <shawnn@gmail.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* util: Add EC-3PO, the EC console interpreter.Aseda Aboagye2015-11-114-0/+2065
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC-3PO is the console interpreter that will one day replace the EC console that we have today. EC-3PO aims to migrate our rich debug console from the EC itself to the host. This allows us to maintain our rich debug console without impacting our EC image sizes while also allowing us to add new features. This commit is the 1st of three phases, the insertion phase. The main goal of this insertion phase is to get EC-3PO in place between servo and the EC UART, while not modifying the behaviour of the console too much. At this point, EC-3PO is capable of the following things: - Replicate command editing. - Save command history. - Performs error checking with console commands. The command editing should be at parity with the current EC console. With EC-3PO, one can have a much longer command history which also persists across EC reboots. And lastly, with a cooperating EC image, EC-3PO can perform error checking with console commands. Automatically retrying console commands if the command was incorrectly received at the EC end. Currently, commands are sent to the EC in a "packed" plaintext form. The next phase will introduce the host command packet communication. console.py is the module that provides the console interface between the user and the interpreter. It handles the presentation of the console including command editing. It also has an accompanying set of unit tests in console_unittest.py. It currently has 1 test suite to test the various console editing methods. interpreter.py is the module that provides the interpretation layer between the EC and the user. It also is responsible for the automatic command retrying. It requires pipe connections to be made to it for command and debug data communication. BUG=chrome-os-partner:46054 BRANCH=None TEST=util/ec3po/console_unittest.py TEST=Flash GLaDOS with a modified EC build. Run console.py passing the EC UART, verify that I can edit commands, send commands, view command history, and receive output from the EC. TEST=cros lint --log-level debug ./util/ec3po/console.py TEST=cros lint --log-level debug ./util/ec3po/interpreter.py TEST=cros lint --log-level debug ./util/ec3po/console_unittest.py Change-Id: I38ae425836efd69044334e1ed0daf3f88a95917c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/308615 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
* pd: set dedicated charger after boot with legacy chargerAlec Berg2015-11-111-5/+10
| | | | | | | | | | | | | | | | | | | | | | Fix bug with the new VBUS_NEVER_LOW flag in which if a BC1.2 charger is attached on boot, we will not set the charger as a dedicated charger and therefore not charge from it, until the charger is disconnected and reconnected. This happens because in SNK_DISCOVERY we will send soft reset first, and then when the charger doesn't respond, we send hard reset. But, registering the charger as a dedicated charger previously only happened when we send hard reset directly after SNK_DISCOVERY state. BUG=none BRANCH=none TEST=tested on glados. sysjump with bc1.2 charger plugged in and make sure we charge from it. Change-Id: Ida89304092a2186bcb2aa885917d706231490288 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311364 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* glados: Add pullup to SPI MISO GPIOShawn Nematbakhsh2015-11-111-1/+1
| | | | | | | | | | | | | | | | When SPI CS is deasserted, SPI MISO is floating, which leads to leakage. BUG=chrome-os-partner:42104 BRANCH=None TEST=Manual on glados. Verify S5 power drops by ~1.5mW and sysjump / EC RW hashing continues to function. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0ba8fcab1618f396adc32984da93e37c5ff770a4 Reviewed-on: https://chromium-review.googlesource.com/311821 Commit-Ready: Shawn N <shawnn@gmail.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* usb_charger: disconnect usb switch until connection is debouncedAlec Berg2015-11-111-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Re-order logic in BC1.2 detection task so that we open the USB switches immediately upon detecting a connection, then debounce the connection, then reset the pericom and determine BC1.2 charger type. This fixes two problems: - Problem where host could enumerate dut, detect disconnect, and then re-enumerate. - Problem where sometimes dut would detect a host workstation as a proprietary charger because we weren't delaying long enough after opening USB switches before triggering pericom reset. BUG=chrome-os-partner:47219 BRANCH=smaug TEST=tested by connecting workstation to ryu (tested both pluggin in A side first and C side first). Without this patch, my workstation often see's disconnect and reconnect. With this change we only get one connect. Change-Id: I07cc3473ff32953fad3cc6d1db01b86b44969c4e Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311804 Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: Modify port 80 service routineEli Hsu2015-11-112-4/+4
| | | | | | | | | | | | | | | | | Change the parameter name. Change the output length of console command - port80. Signed-off-by: Eli Hsu <eli.hsu@ite.com.tw> BRANCH=none BUG=none TEST=console command port80 Change-Id: I8da3f7ec30f16ceea17a8f4fec55162f73a4b28b Reviewed-on: https://chromium-review.googlesource.com/311960 Commit-Ready: Eli Hsu <eli.hsu@ite.com.tw> Tested-by: Eli Hsu <eli.hsu@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charge_state_v2: fix CONFIG_CHARGER_NARROW_VDC optionAlec Berg2015-11-111-1/+2
| | | | | | | | | | | | | | Fix missing {} when CONFIG_CHARGER_NARROW_VDC enabled. Bug introduced in CL:309289. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I8b045b7231ea9916595184e468f93c879f243c42 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311796 Reviewed-by: Shawn N <shawnn@chromium.org>
* chell: Enable reset of EC on PD panicDuncan Laurie2015-11-111-0/+1
| | | | | | | | | | | | | | Enable the option to reset the EC when the PD panics. BUG=chrome-os-partner:46289 BRANCH=none TEST=verify that if PD is in RW and reboots then the EC will panic and print "PD crash". Change-Id: I69ab08914aef08b5ef0eaa447c142444113c526c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311308 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* chell: Fix hibernate by not touching PMIC reset pinDuncan Laurie2015-11-111-0/+2
| | | | | | | | | | | | | | | | This pin is active high to reset the pmic so it can't be pulled up without resetting the EC. BUG=chrome-os-partner:47237 BRANCH=none TEST=hibernate on chell Change-Id: I3c09a991825544bd5bf5437f4a802e2dd2990807 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311307 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Cleanup PD port-to-task macrosShawn Nematbakhsh2015-11-1114-25/+20
| | | | | | | | | | | | | | | | | | Cleanup our port-to-task and task-to-port macros to allow cleanly adding a third port. BUG=chromium:554243 BRANCH=None TEST=Manual on glados / glados_pd. Verify that both USB-C ports are functional for charging. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib833de0dfaa9490f4de8efb08d2cdddd86d57896 Reviewed-on: https://chromium-review.googlesource.com/311785 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Cr50: Tweak debug message for clarityBill Richardson2015-11-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until we update the naming for our various images in the Makefiles, let's change the bootloader message slighty, so that instead of seeing two "RO" images: CR50 RO, 20151104_41733@78962 Valid image found at 0x00044000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: RO, cr50_v1.1.4008-957a842 2015-11-07 00:28:37 wfrichar@wintermute4.mtv. corp.google.com] [0.000897 Verifying RW image...] we see the bootloader, and then what we've been calling the RO image, and then the RW image: cr50 bootloader, 20151104_41733@78962 Valid image found at 0x00044000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: RO, cr50_v1.1.4008-957a842 2015-11-07 00:28:37 wfrichar@wintermute4.mtv. corp.google.com] [0.000897 Verifying RW image...] BUG=none BRANCH=none TEST=make buildall, try it No new functionality, just a different message on the console. Change-Id: Ia8dce600c7d159416dc6dabbbf0c0cc4129a988d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311831 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Fix uart_tx_flush() to really flushBill Richardson2015-11-101-2/+3
| | | | | | | | | | | | | | | | | | We were just checking to see if the UART TX unit was idle. We also need to be sure there aren't any bytes in the TX FIFO that haven't been clocked out yet. BUG=none BRANCH=none TEST=make buildall, manual Before, "crash watchdog" would truncate the trace dump as it rebooted. Now it doesn't. Change-Id: Icff828445801ce61a0a8f296b3d3e9fb300b7efc Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311299 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Workaround for watchdog permission problemsBill Richardson2015-11-102-9/+20
| | | | | | | | | | | | | | | | | | | | When we lower the runlevel for security purposes, the standard ARM watchdog interrupt is no longer enough to cause a full reboot. We'll manually trigger a system reset instead. For now, it's a soft reset. Should it be hard? BUG=chrome-os-partner:47289 BRANCH=none CQ-DEPEND=CL:310975 TEST=make buildall, manual From the console, run "crash watchdog". After a second or to, the watchdog trace dump appears and the system reboots. Change-Id: I99fcaf19b32728563e3b051755d65267cc11156c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311298 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* it8380dev: modify hwtimer's commentDino Li2015-11-101-1/+1
| | | | | | | | | | | | | | Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make buildall -j Change-Id: Id161c84437e8d6edc2ec1a4cde292f642d08b853 Reviewed-on: https://chromium-review.googlesource.com/311333 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: util: fix iteflashDonald Huang2015-11-101-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for flash the ite ec from usb gpio port Signed-off-by: Donald Huang <donald.huang@ite.com.tw> BRANCH=none BUG=none TEST=Test OK on ITE8390CX from both GPIO PORT (C1,C2) (H5,H6) You can run "make -j BOARD=it8380dev" to build ec.bin and flash the ec.bin via "sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin" /* ==SNAPSHOT START== */ (cr) (br-iteflash) donald@donald-nb ~/trunk/src/platform/ec $ sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin Waiting for the EC power-on sequence ...CHIPID 8390, CHIPVER 82, Flash size 256 kB Done. CHIPID 8390, CHIPVER 82, Flash size 256 kB Erasing chip... /100% Writing 262144 bytes at 0x00000000 Done. /* ==SNAPSHOT END== */ Change-Id: I422db6f7007622f8be624a534a482e24d53a061a Reviewed-on: https://chromium-review.googlesource.com/311205 Commit-Ready: Donald Huang <donald.huang@ite.com.tw> Tested-by: Donald Huang <donald.huang@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Donald Huang <donald.huang@ite.com.tw>
* cr50: make customized RO workVadim Bendebury2015-11-105-40/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch completes introduction of building of proper RO and RW images for cr50. A few small mods were required: - both RO and RW images have to be signed, using the same dedicated signer, but with different keys, dev_key.pem is not needed any more. - the RW image offset is not at the half of available flash, a chip specific value of 16K is used instead. The suggested new image layout is as follows: +----------------------------------------+ | 1KB RO signature header. | +----------------------------------------+ - - | 15KB RO image. | - - +========================================+ | 1KB RW-A signature header. | +----------------------------------------+ - - - - | 239K RW-A image. | - - - - +========================================+ - - | 16 KB NVRAM, shared | - - +========================================+ | 1KB RW-B signature header. | +----------------------------------------+ - - - - | 239K RW-B image. | - - - - +========================================+ BRANCH=none BUG=chrome-os-partner:43025 TEST=The combined image (build/cr50/ec.hex) is successfully loaded and started by the spiflash utility from the latest FPGA tarball. Corrupting a byte in the generated image in the RW section causes failure to verify. Change-Id: I41a05168b0d4e9f88efa1003f261b6dd03972a24 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311422 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: allocate signature headers in both RO and RW imagesVadim Bendebury2015-11-102-0/+4
| | | | | | | | | | | | | | | | With the proper RO in place, RW must be signed in the same manner, as RO. This patch makes sure that there is room in the RW header for the signature. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches applies the RO successfully boots up the RW. Change-Id: I1538195e0181c23c874ddd300887cf5da8c5a867 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311421 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: RO Loader implementationVadim Bendebury2015-11-1012-5/+858
| | | | | | | | | | | | | | | | | | | | | | | This code is a port of the sample loader application included in the FPGA update. Only the pieces relevant to straight verification and boot were ported. The loader generates a hash, inputs to which are the image body, state of fuses and state of flash INFO region, and the output is the value, which will unlock the region for execution, if it is correct. Only one image load is attempted, the image is supposed to be located in the flash at the offset of CONFIG_RW_MEM_OFF. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches applied the RO image successfully verifies and starts up the RW image. Change-Id: I26e1fbdaeb8b23d519c1a328526a3422231bb322 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311316 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* common: export the linker generated addresses of image sectionsVadim Bendebury2015-11-101-0/+5
| | | | | | | | | | | | | | | The values are there, we just need to be able to access them from the code to be able to calculate how much of the flash space needs to be made accessible for the image to run. BRANCH=none BUG=none TEST=used by later patches Change-Id: I4eb59525a50177cc7cc725871c3eab2ff390667b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311319 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: util: signer: make signer header definition usable on the targetVadim Bendebury2015-11-102-19/+17
| | | | | | | | | | | | | | | | | | | | The signer running on the build host and the loader running on the target must be in sync as of the structure of the signature header. To be able to use the same definition in both programs, remove the system includes from the .h file which needs to be shared. Rearrange includes in image.cc to follow the coding conventions. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches applied the code successfully boots, which indicates that the signer is in fact working properly. (See the top patch for testing details). Change-Id: I6bc9c57ebea55ac256fcdac8338c5566f16b6371 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311420 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* cr50: signer: test private key for development environmentVadim Bendebury2015-11-101-0/+39
| | | | | | | | | | | | | | | This key is meant to be used by the RO image when verifying the RW. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches in place (in particular, this key's public counterpart used in chip/g/load/verify.c), the RW is successfully verified by RO. Change-Id: Iddcc21d88518e402da614d20d913aeed162b0042 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311315 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* util: signer: fix nonzero offset binary image signing bugVadim Bendebury2015-11-101-1/+1
| | | | | | | | | | | | | | | | | | When signer code was ported and enhanced to work with binaries (in addition to hex), a bug was introduced, where the signed image is considered to always to be based at the bottom of the flash. In fact the image could be anywhere in the flash, the actual address derived from the input elf file should be used. BRANCH=none BUG=chrome-os-partner:43025 TEST=verified that when enabled, RW image is signed properly (build/cr50/RW/ec.RW.flat starts with a signature). Change-Id: I194bd02f932529165adcbebf4bcbd9020fc261dc Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311314 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: re-generate register descriptionsVadim Bendebury2015-11-102-21/+25
| | | | | | | | | | | | | | New aliases are created automatically, there is no need to include them in registers.h manually any more. BRANCH=none BUG=none TEST=built and ran cr50 successfully Change-Id: I9c12c9a66d231723f8c986dd0c598f1e03aaca3a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311372 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* util: enhance cr50_regs to generate modified base address namesVadim Bendebury2015-11-101-1/+6
| | | | | | | | | | | | | | | | | | | | | | Register descriptions generate by the hardware tools always use the block index when naming the base address of the bock, but the macros compiling addresses out of register names do not use the index if there is just one instance of the block in the design. The problem is addresses by aliasing these definitions in registers.h in the chip directory. This patch automates this aliasing and ensures that the generated file has the aliases included, no need to add them manually to registers.h. BRANCH=none BUG=none TEST=re-generated cr50_regs.h, observed proper aliases created, built and ran cr50 with the new registers file. Change-Id: If037e082841a1510f7cad66737fd8b775dc667ea Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311371 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* common: charge_state_v2: Add items to .bss.slow.stabilize-7628.BAseda Aboagye2015-11-091-5/+5
| | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:46056 BUG=chrome-os-partner:46063 BRANCH=None TEST=Enable CONFIG_REPLACE_LOADER_WITH_BSS_SLOW on GLaDOS. Build, flash, and verify AP and EC boot. Plug in charger, issue 'battery' command. Verify charging still works and command shows reasonable data. TEST='sysjump rw' and repeat the above tests. TEST=make -j buildall tests CQ-DEPEND=CL:311209 Change-Id: I0661c32b641299d4be685156a4ac725267804a3e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/311401 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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