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* vboot_hash: Save stack space when checking image sizestabilize-7834.66.Brelease-R49-7834.BShawn Nematbakhsh2016-01-151-1/+5
| | | | | | | | | | | | | | | | | Use a static buffer rather than 256 bytes of stack when scanning for the end of an image. BUG=chrome-os-partner:49396 TEST=Verify "ectool echash abort; ectool echash start 0xfffffffe 100" doesn't panic on glados. BRANCH=glados Change-Id: Ia864fe77134533bce079dab3b253142b14410ded Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322283 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* glados / kunimitsu: led: battery LED blinking on low batteryli feng2016-01-152-4/+8
| | | | | | | | | | | | | | | | | | If no charger connected, battery LED blinks when battery is low/critical; and it should stop blinking once system is in S5/G3. BUG=chrome-os-partner:48718 BRANCH=none TEST=Verified on Kunimitsu when OS shutdown system due to critical battery and enter S5/G3, battery LED stops blinking. Change-Id: I9349a9938a548ce675999579f749bd5dae3c399f Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/321794 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Driver: ISL9237: Configure Prochot# Debounce time to maximumVijay Hiremath2016-01-152-1/+13
| | | | | | | | | | | | | | | | | | | Configured the Prochot# Debounce time to maximum (1ms) to avoid false triggers on the Prochot pin. BUG=none TEST=Manually tested on Kunimitsu, Prochot pin in not triggered when the battery current ripples or the adapter current ripples are less than 1ms. BRANCH=none Change-Id: I3ccebcfbced2285dcacff8a3750090c0500a102c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/322292 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc: Support hibernate_wake_pins on wheatley, npcx_evb and npcx_evb_arm.Mulin Chao2016-01-149-73/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb and npcx_evb_arm. For better power consumption, we disable ADC, tri-state spi pins, all inputs of wake-ups to prevent leakage current caused by input floating and set necessary GPIOs' states in hibernate function. Modified drivers: 1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate. 2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate. 3. wheatley/board.c: Add hibernate_wake_pins array for hibernate. 4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting GPIOs' status related to board for better power consumption. 5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt will disable before it is called. 6. register.h: Add WKINEN definition and declarations used for hibernate. 7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs' state and wake-up inputs before entering hibernate. 8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field. 9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/321466 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash_ec: Allow dfu updates without servo consoleNick Sanders2016-01-141-3/+6
| | | | | | | | | | | | | | | | | | | | | | flash_ec is used for both ec chips accessed over servo, and standalone stm32 devices. It's not necessary to have a servo conencted to update the standalone devices over usb. This is useful for servo v4 and servo micro. BUG=chromium:571477 TEST=Verify servo micro/discovery can be flashed without servo v2. BRANCH=none Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I9deee1616d93feeac4d6675bc3a4f573d4906f7b Reviewed-on: https://chromium-review.googlesource.com/321925 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@google.com> Reviewed-by: Wai-Hong Tam <waihong@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* Kunimitsu: Increase 5V rail in PMICKyoung Kim2016-01-141-0/+10
| | | | | | | | | | | | | | | Fix for 5V voltage drop on USB daughter board BUG=chrome-os-partner:49222 BRANCH=master TEST=monitoring 5V rails in daugher board when 1A load to USB port. Change-Id: I7a5138e11101994e3e335e5cc16068985fd3366a Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/321430 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Skylake: prevent EC from continuing execution after turning 3.3V_DSW off.Kyoung Kim2016-01-135-0/+10
| | | | | | | | | | | | | | | | | | Without this patch, EC continues to execute including board_pmic_init() and its i2c transaction can be disturbed in the middle without proper i2c stop and following new i2c transaction might fails. BUG=none BRANCH=master TEST=none Change-Id: Iaa39d3531faa5af24c1c4b445de014c9e263a021 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/321342 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Kunimitsu/Lars: for PMIC, check i2c response before further initializationKyoung Kim2016-01-132-6/+20
| | | | | | | | | | | | | | | | | There is no indication that PMIC is ready for communication EC should check i2c response from PMIC first before initializing rest of registers. BUG=None BRANCH=master TEST=check if there is message, "PMIC init failed", in EC log. Change-Id: Ic790edf3639acfb2b5357e2638c88dc8d59bebf0 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/319631 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* util: ec3po: Change console permissions to 666.Aseda Aboagye2016-01-121-0/+5
| | | | | | | | | | | | | | | | | Updated the permissions of ec_uart_pty to match the permissions of the other PTYs. BUG=None BRANCH=None TEST=cros_workon hdctools ec-devutils, run servod, ls -l on ec_uart_pty from dut-control, verify that permissions are 666. Change-Id: I71c72645c5a435fea562084185b80ff6d31652b4 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/321371 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* Initial RSA implementation.stabilize-7821.Bnagendra modadugu2016-01-1112-61/+1431
| | | | | | | | | | | | | | | | | | | | | Includes support for encrypt / decrypt, and sign / verify; padding schemes OAEP / PKCS1; supporting bignum library. RSA key sizes must be a multiple of 32-bits (with the top bit set). Keying material, input and output buffers are required to be word-aligned. BRANCH=none TEST=added encrypt/decrypt sign/verify tests, compatibility with openssl tested BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I6bc324c651e3178bb45bb75ab5935d9bc07efbce Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/316942 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* util: ec3po: Add support to disconnect from UART.Aseda Aboagye2016-01-112-5/+171
| | | | | | | | | | | | | | | | | | | | | | This commit adds support for the EC-3PO interpreter to disconnect and reconnect to the EC UART. This is handy so that other tools that need to use the raw UART directly can do so without interference from EC-3PO. BUG=chromium:571170 BRANCH=None TEST=For both enhanced and non-enhanced EC images, issue disconnect command and verify that no debug prints were emitted and no commands were sent to the EC. Then issue reconnect and verify that the console works as normal and that no commands were buffered. TEST=./util/ec3po/run_tests.sh Change-Id: Ic572e25d24d5e45fbe2eeb84a534235c4ec98d38 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/321084 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* sb_firmware_update: Use any available host protocolShawn Nematbakhsh2016-01-111-1/+1
| | | | | | | | | | | | | | | | Don't restrict host protocol to LPC since newer boards only support COMM_DEV. BUG=chrome-os-partner:44052 TEST=Verify SB FW update is successful on Ultima. BRANCH=None Change-Id: I64f0c3ff278fe464cc71661454734c4cac5e88a9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321330 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* kunimitsu: increase stack size for PD_C0, PD_C1, and PD_CMDKevin K Wong2016-01-112-3/+9
| | | | | | | | | | | | | | | If I2C unwedge is called, an additioanl 220+ bytes of stack space will be needed. BUG=none BRANCH=none TEST=make buildall Change-Id: Ib0e6716e400e5993df2cdb48186ffc7776d523f0 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/320840 Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Lars: Update PMIC settingsRyan Zhang2016-01-111-0/+10
| | | | | | | | | | | | | | | To increase input voltage in PMIC BUG=chrome-os-partner:49222 BRANCH=lars TEST=`make -j BOARD=lars`, OS start normally. Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Change-Id: I8c4565191374c741dfdf9a078e0da4124731c4ea Reviewed-on: https://chromium-review.googlesource.com/320505 Commit-Ready: Ryan Zhang <Ryan.Zhang@quantatw.com> Tested-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* util: presubmit_check.sh: Fix (again) for ec3po.Aseda Aboagye2016-01-111-1/+1
| | | | | | | | | | | | | | | | | | | | | If a user had already run util/ec3po/run_tests.sh, and then never modified any ec3po files, the presubmit check would list every file in the EC repo that was newer since the the last run. This included files such as build artifacts. BUG=chromium:575032 BRANCH=None TEST=Run ./util/ec3po/run_tests.sh once. Run make -j buildall, try to upload and verify that no nag message to run ec3po tests is presented. TEST=Touch an ec3po file, try to upload, verify that nag message about running ec3po unit tests is presented. Change-Id: I4f09bb76dcd85b570b57030197f4887bed85f1a7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/321134 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* wheatley: replace Makefile with real link file.Mulin Chao2016-01-081-0/+0
| | | | | | | | | | | | | | | | | Replace Makefile with real link file in order to build sources in board folder. Modified drivers: 1. Makefile: change file type to link file BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Iba80166369869d661c8f6da989e3bc1c586047e7 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/320901 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* oak: pd: move power change notification to function board_set_charge_limit.Ben Lok2016-01-082-5/+14
| | | | | | | | | | | | | | | | | | | | | | if CONFIG_USB_PD_TCPM_VBUS is enabled, a race condition may happen: In function pd_set_input_current_limit() and typec_set_input_current_limit(), EC may notify AP power change event before PD send the up-to-date POWER_STATUS TCPC alert to EC. It will cause the AP get the stale power status. Move the power change event notification to board_set_charge_limit(), it will be called after EC receives POWER_STATUS TCPC alert, and sending power change event notification only if the "charge limit" or "charge port" or supplier is changed. BUG=chrome-os-partner:48801 BRANCH=none TEST=make buildall -j; Tested on Oak by plug/unplug AC adapter to type-C ports and verify the UI battery icon shows the correct status instantly. Change-Id: I52f0e268fdebc45e609d843847540ae48cd0a9eb Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/320066 Reviewed-by: Rong Chang <rongchang@chromium.org>
* pd: Add common EC_HOST_EVENT_PD_MCU implementationShawn Nematbakhsh2016-01-078-50/+46
| | | | | | | | | | | | | | | | | | | | | For TCPMs with an off chip TCPC, PD MCU host event status can be handled in a common way. When a status flag is updated (ex. from charge_manager), notify the AP through the host event, and save the status flag for later retrieval. BUG=chrome-os-partner:49124 BRANCH=None TEST=Verify `cat /sys/class/power_supply/CROS_USB_PD_CHARGER1/online` on chell reflects the actual online status of the charger. Also verify UI charge icon tracks the online status correctly. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I63bc70205627474590e38ffd282faedaea3bcc66 Reviewed-on: https://chromium-review.googlesource.com/320796 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* util: presubmit_check.sh: Fix check for ec3po.Aseda Aboagye2016-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | The presubmit check would nag at the user to run the EC-3PO unit tests, even if they hadn't modified any EC-3PO files. This was not my intention. This commit fixes the presubmit check to only check for unit test success if a EC-3PO file is modified. BUG=chromium:575032 BRANCH=None TEST=Remove util/ec3po/.tests-passed; Modify a non-ec3po file, commit, and try to upload. Verify that no nag message is presented. TEST=Remove util/ec3po/.tests-passed; Modify a ec3po file, commit, and try to upload. Verify that a nag message to run unit tests is presented. Change-Id: I86e9f325329b7ad1a4c7c5971b7851e9024e7750 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/320831 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* wheatley: Proposed workaround for RESET_FLAG_RESET_PIN issue on wheatley.Mulin Chao2016-01-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | During pressing VolUp + VolDn + Pwr buttons, Silego polls down both EC_RST_L and ROP_LDO_EN on wheatley. Beside VCC1_RST occurs, power-on reset also occurs simultaneously since EC's power rail is turned off by PMIC for a while. VCC1_RST_STS bit is cleared by power-on reset and it will influence recovery mode detection. The workaround treats no matter power-on or VCC1_RST reset as reset-pin reset. Use BOARD_WHEATLEY to distinguish them. Modified drivers: 1. system.c: Proposed workaround for RESET_FLAG_RESET_PIN issue. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I96198ffb6901f0539755046ca303e94381ae7541 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/320641 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Support rpm mode for fan control.Mulin Chao2016-01-064-196/+176
| | | | | | | | | | | | | | | | | | | | | | | In order to support rpm mode, we use a TICK function (fan_tick_func) to monitor tacho value and adjust PWM duty. In this version, fan driver always enables clock source of MFT to make sure it can present real-time tacho value. For better performance, the feedback value to adjust PWM duty is various. We also change fan & pwm settings for SUNUN 4-pins pwm-type fan. Modified drivers: 1. npcx_evb/board.h: Modified fan_t & pwm_t structures for SUNON fan spec. 2. npcx_evb_arm/board.h: Modified fan_t & pwm_t structures for SUNON fan spec. 3. fan_chip.h: Remove unnecessary default_count field of mft_t structure 4. fan.c: Add support for rpm mode BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I25e7bd2f3f726b40fd4e0d9a1049a4d82bbd830d Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/320510 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charger: Change unlocked battery level ignore conditionsShawn Nematbakhsh2016-01-068-26/+31
| | | | | | | | | | | | | | | | | | | | | | | | x86 systems will auto-power-on when power is applied to the EC. When the battery level is critically low, power-on is prevented, except when the system is unlocked. So, when unlocked, some systems will auto-power-on regardless of battery level, overcurrent the charger / battery, and then repeat forever. Prevent this reboot loop by ignoring auto-power-up when the battery is critically low, regardless of system unlocked status. BUG=chrome-os-partner:48339 TEST=Verify power-up is prevented on no-battery chell w/ donette. Then, run 'powerbtn' on EC console and verify system powers on (and overcurrents). BRANCH=None Change-Id: Ia631b5a8c45b42ec805e4a0c3f827929a0efd236 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319187 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* core: nds32: add task_wait_event_mask() function to nds32 coreDino Li2016-01-053-4/+32
| | | | | | | | | | | | | | | | | | | | | [task] 1. Copy task_wait_event_mask() function of cortex-m0. [system] 2. Include host_command.h for host_command_pd_request_hibernate(). [i2c] 3. Update i2c handler to use task_wait_event_mask. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chromium:435611,chromium:435612 TEST=1. console commands: i2cscan, i2cxfer, and battery. Change-Id: If5bb4407460d28c0b021ab133ca4b635ff7bc3c9 Reviewed-on: https://chromium-review.googlesource.com/320440 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* vboot_hash: check the current hash is for the right regionMary Ruthven2016-01-051-4/+19
| | | | | | | | | | | | | | | | | | | | | With the RO region being added to software sync, up to two hashes will be requested during boot. Currently if vboot_hash has a valid hash when the EC gets an EC_VBOOT_HASH_GET host command then it will return that hash. When the EC gets a request for the RO hash after it has calculated the RW hash it returns the RW hash in the response. This change will add a check that the EC not only has a valid hash, but that it is for the correct region. BRANCH=none BUG=none TEST=Try to get the RO and RW hashes from depthcharge and make sure they match the values gotten using ectool Change-Id: I2449c8d79b4a74f4865dd1234fb253bcdac66a31 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/318861 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Chell: modify led setting for OEM specBruce2016-01-051-8/+1
| | | | | | | | | | | | | | | Modify the led blink white at battery capacity less than 12%. BUG=None BRANCH=None TEST=check the led blink white at battery capacity less than 12% Change-Id: I3494ed7d207e769fe081b4442fd298b4e481e0a7 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/319729 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* util: ec3po: Add served PTY to logging.Aseda Aboagye2016-01-052-2/+12
| | | | | | | | | | | | | | | | | | | | Some devices have multiple ECs (main EC and PD MCU) and therefore there are multiple consoles and interpreters running concurrently. This commit prepends each log message with the served PTY to identify which of the console or interpreter instances the log message comes from. BUG=None BRANCH=None TEST=Ran ec3po in servo for samus. Noticed each debug print with the different PTYs for the main EC as well as the PD MCU. TEST=util/ec3po/run_tests.sh Change-Id: Icc69d2257172f4fedc217572ad0b6d15dac40387 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/320597 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
* util: ec3po: Change interrogation timeouts.Aseda Aboagye2016-01-052-6/+34
| | | | | | | | | | | | | | | | | | | | | | In testing, it was found that certain ECs couldn't respond to the EC_SYN in less than 0.1s. Therefore, this commit changes the interrogation timeouts. For non-enhanced EC images, the timeout has been increased to 0.3 seconds. This is small enough that there's not too much of a delay, but long enough that enhanced EC images can respond in time. With an enhanced EC image on veyron_jerry, EC_ACKs were arriving after ~0.2s. BUG=None BRANCH=None TEST=Flash enhanced EC image on veyron_jerry, start console/interpreter pair and verify that the console is functional. TEST=util/ec3po/run_tests.sh Change-Id: I4931aaee908653ae302a8e57941444e5f0b6ce2b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/320594 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cortex-m: proper handling of input parameters to SVC handlerIcarus Sparry2016-01-052-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | According to section 2.7 of Cortex-M3 Application Note 179: A Cortex-M3 processor can get a "late arriving exception" and this will corrupt the values of the r0, r1, r2 and r3 registers passed in an svc call. http://infocenter.arm.com/help/topic/com.arm.doc.dai0179b/AppsNote179.pdf The fix is to reload the two registers we care about, r0 and r1, from the stack to ensure the input parameters to SVC handler, desched (r0) and resched (r1), are valid. BUG=chrome-os-partner:48499 BRANCH=none TEST=Used assert to verify resched is a valid TASK ID. Change-Id: Ie2229472e709febe16eee3c2cd986e3815fda076 Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com> Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/319849 Commit-Ready: Icarus W Sparry <icarus.w.sparry@intel.com> Tested-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Get more accurate value of deep idle time.Mulin Chao2016-01-053-8/+21
| | | | | | | | | | | | | | | | | | | | | We should consider the interval between the calling __hw_clock_event_set and entering deep idle. In order to get more accurate value of deep idle time, FW should record the time-stamp before entering deep idle and calculate the deep idle time based on it. Modified drivers: 1. hwtimer_chip.h: Add new function declarations for deep idle time caculation. 2. hwtimer.c: Add new functionsfor deep idle time caculation. 3. clock.c: Modified for calculating more accurate deep idle time. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Id037c4dc3564659e4ad493f2fc3ffc5d06c18b06 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/320071 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* util: ec3po: Add presubmit check for ec3po.stabilize-smaug-7800.BAseda Aboagye2016-01-042-0/+26
| | | | | | | | | | | | | | | | | | | | | Added presubmit check to make sure that when any ec3po files are modified, the unit tests should be run as well. BUG=None BRANCH=None TEST=Touched a unit test file, tried repo upload and received an error about running unit tests. Ran run_tests.sh and all tests passed. Tried to repo upload again and this time it succeeded. TEST=Created a failure in one unit test, ran run_tests.sh and verified that the failure was caught and the CL wouldn't pass the presubmit check. Change-Id: I4df4a0fd1107292f693749188491f6286360f557 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/319211 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* keyboard: Fix kbpress after recent keyboard changeDouglas Anderson2016-01-041-1/+11
| | | | | | | | | | | | | | | After commit 98ab7484d331 ("keyboard: prevent races enabling/disabling kb scanning") kbpress was totally broken, which wasn't so good for FAFT. Fix it by making sure we go into polling mode for simulated keyboard presses. BUG=chrome-os-partner:48849 TEST=kbpress works Change-Id: Icd663c2ee7a184e6af4438368595087b35724a4f Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319586 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* wheatley: Add CONFIG_LTO definition to reduce FW size.stabilize-7797.BMulin Chao2015-12-302-1/+2
| | | | | | | | | | | | | | | | | | | Add CONFIG_LTO definition to reduce the size of FW image. Modified drivers: 1. board.h: Add CONFIG_LTO definition. 2. header.c: Add __keep keyword to prevent linker ignore header during optimization. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I6205af37572a68f35f90dbd9b28d86230533ca8b Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/319799 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kunimitsu: add debug assert flagKevin K Wong2015-12-301-1/+0
| | | | | | | | | | | | | | | Restore debug assert flag which was previously removed due to limited code space. BUG=none BRANCH=none TEST=make buildall Change-Id: I9617b1221bc6217e8f8ed745ea0ce12418233440 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/319606 Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* util: npcx: Fix build for ARM host boardsShawn Nematbakhsh2015-12-301-2/+2
| | | | | | | | | | | | | | | | | ecst is used at build / link time, so it should be compiled for the build machine architecture, not the architecture of the host board. BUG=chromium:567232 TEST=Verify 'cros_sdk ... cros_run_unit_tests --board=oak' passes with CL:319256. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic7f6aa989d0760eda1fe64221e41d3230c9ab9b9 Reviewed-on: https://chromium-review.googlesource.com/319633 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chell / chell_pd: Use power-optimized GPIO defaultsShawn Nematbakhsh2015-12-242-14/+22
| | | | | | | | | | | | | | | | | Pull floating pins high, don't duplicate external pull ups, and make a few other minor changes. BUG=chrome-os-partner:48109 TEST=Verify chell continues to boot and S5 power is reduced to ~5.5 mW. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iaee0cc926149dae1f4189e6b9e4f7e3a4da6ba1c Reviewed-on: https://chromium-review.googlesource.com/319165 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lucid: add LED supportMary Ruthven2015-12-226-1/+214
| | | | | | | | | | | | | | | Implement LED control for lucid with red, blue, and green LEDs. BUG=chrome-os-partner:48661 BRANCH=none TEST=make sure lucid builds Change-Id: I97ed56daa8fdb40daf8ab06e53913dcff2e41dea Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319224 Commit-Ready: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lucid: implement fast chargingMary Ruthven2015-12-222-0/+150
| | | | | | | | | | | | | | | | | Use custom charging profile to enable charging at a faster rate. BUG=chrome-os-partner:48662 BRANCH=none TEST=load on lucid and charge at room temp. Use "chgstate" command to verify that battery current matches the expected fast charging current for the given temp range and voltage. Change-Id: Ie508d29db091593ff2cfda9d135c73f6a3de5a9a Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319493 Commit-Ready: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lucid: remove some unnecessary features to save spaceAlec Berg2015-12-221-0/+2
| | | | | | | | | | | | | | Remove ADC watchdog and i2cscan console command to save flash space. BUG=none BRANCH=none TEST=make BOARD=lucid Change-Id: I3da8a13fdd962041ccdc830cb1b9b5803917bc2b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319611 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Move rand_bytes implementation from tpm2 to chip/g.nagendra modadugu2015-12-223-21/+35
| | | | | | | | | | | | | BRANCH=none TEST=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 Signed-off-by: nagendra modadugu <ngm@google.com> Change-Id: Ic7a850fdf2594ac1981237edda8dceb16cc7cbe6 Reviewed-on: https://chromium-review.googlesource.com/319155 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* nuc: Enable lower core CLK for power consumptionCHLin2015-12-213-27/+33
| | | | | | | | | | | | | | | | | | | | | Support lower core CLK frequency and configure the baudrate parameter of console UART for current core CLK. Modified drivers: 1. clock.c: Support lower core CLK frequency. 2. uart.c: Add baudrate setting for differenct core CLK. 3. clock_chip.h: Set default core CLK to 16MHz. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Id83ecf92c19bec508ec84e2d271d7e1fa278774f Signed-off-by: CHLin <chlin56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/319030 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: adc: Add support for DMA continuous modeShawn Nematbakhsh2015-12-215-31/+150
| | | | | | | | | | | | | | | | | | | Add support for continuously writing ADC samples to a circular buffer. CONFIG_ADC_PROFILE_FAST_CONTINUOUS should be defined and an appropriate sized buffer must be passed to adc_read_all_channels(). BUG=chromium:569994 TEST=Manual on snoball. Verify 'adc' continues to function (single mode). With pending commit, verify that continuous conversion interrupt is called at appropriate frequency and values look consistent. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I025825d72a698f8f1f4f95a89477df791bd5e67e Reviewed-on: https://chromium-review.googlesource.com/318505 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: adds the SPI master driverEwout van Bekkum2015-12-214-1/+231
| | | | | | | | | | | | | | | | | Adds the SPI master driver with support for both SPI masters with support for using GPIOs as chip selects or using the hardware's dedicated chip selects. Note this has not been enabled in the cr50 board. BRANCH=none BUG=none TEST=verified through use of the SPI_FLASH module on cr51 Change-Id: I88719f8d03e217ab44249172b1340011fdcfdad5 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317329 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: Include host/console commands based on HAS_TASK_HOSTCMD/CONSOLEShawn Nematbakhsh2015-12-182-1/+10
| | | | | | | | | | | | | | | | | | | | | Don't build a table of host / console commands if the HOSTCMD or CONSOLE task is not present. This saves space in the .hcmds / .cmds section and allows the linker to prune command handler functions which will never be called. BUG=chrome-os-partner:41959 TEST=Verify ec.RO.flat shrinks on snoball and glados_pd, and remains the same size on chell and samus. Also verify basic functions are still working on snoball and glados_pd. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I79975c18ec1d87fedda8d1f299f30ffc43c24f69 Reviewed-on: https://chromium-review.googlesource.com/319112 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Lars: Update battery settingsRyan Zhang2015-12-181-9/+10
| | | | | | | | | | | | | | Update battery settings from battery spec. BUG=chrome-os-partner:48571 BRANCH=lars TEST=`make -j BOARD=lars`, OS and EC shutdown normally without AC, Charging normally. Change-Id: I4b8fad8ab993f2ea5190898088bd1bd8c2bd7abb Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/318611 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* ec3po: Add graceful exit.Aseda Aboagye2015-12-172-43/+63
| | | | | | | | | | | | | | | | | | | | | | | | The console and interpreter are usually killed by KeyboardInterrupt whether or not it's run standalone or by servod. This commit tries to make the exit graceful by closing pipes, file descriptors, and exiting each process. BUG=chromium:570526 BRANCH=None TEST=Run ec3po standalone and hit Ctrl+C to kill it. Observe no traceback and no leftover processes. TEST=Repeat above test, but inside servod TEST=cros lint --debug util/ec3po/console.py TEST=cros lint --debug util/ec3po/interpreter.py TEST=python2 -b util/ec3po/console_interpreter.py TEST=python2 -b util/ec3po/console_interpreter.py Change-Id: Ia151b9ede8adf7f8dec6c07277f62d097c13e63e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/319252 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
* Refactor crypto subcommands into their own python module.nagendra modadugu2015-12-173-7/+14
| | | | | | | | | | | | | BRANCH=none TEST=tpmtest.py passes BUG=chrome-os-partner:43025,chrome-os-partner:47524 Signed-off-by: nagendra modadugu <ngm@google.com> Change-Id: I48f426176f17c57c723104d19c963b228f16d985 Reviewed-on: https://chromium-review.googlesource.com/318915 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Implement USB according to Programmer's GuideBill Richardson2015-12-171-213/+649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a rewrite of the Cr50 USB Device Control Endpoint implementation, using the instructions in the DWC USB 2.0 OTG Programmer's Guide (such as they are). Some of the major differences: * Not every USB interrupt indicates the receipt of an incoming packet. Many merely provide updates on packet transfer status, transaction stages, or other activity. We handle those cases correctly. * We may need to start a new Control transaction at any point, even in the middle of an existing transaction. * Large IN data transfers can be handled with one interrupt by chaining multiple together. * Logical separation of the phases of each transaction (Setup, Data, Status). That said, while this CL matches the Programmer's Guide fairly closely, that Guide is pretty crappy and this is just the first commit. There is still a fair amount to do (marked with comments and bug reports). However, it works at least as well as the previous version and is much closer to what the supplier claims is the correct implementation. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') We also connected this device to Windows, and Mac laptops (and a Chromebook) and used a USB bus analyzer to monitor the behavior. It works on machines those, too. Change-Id: Ic515ea83e217a8d0552d61ac5eb19693661fcd15 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/318864 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* nds32: start_irq_handler() use system stackDino Li2015-12-163-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [symptom] The 'vboot_hash_start()' always return busy error and variable 'in_progress' got a strange value(should be 0 or 1). 'start_irq_handler()' causes scratchpad overflow in first context switch. It must be called after SP switch to system stack in ISR. NOTE: The scratchpad is still also need more size even if 'start_irq_handler()' is using system stack. following is detail: 1. uint32_t scratchpad[19] 0x81d34 ~ 0x81d7f [__task_start:] 2. /* put the dummy stack pointer at the top of the stack in scratchpad */ addi $sp, $r3, 4 * 18 -> SP 0x81d7c 3. syscall push return address (-4) -> SP 0x81d78 [ISR:] 4. push r15, fp, lp, and sp (-0x10) -> SP 0x81d68 5. push r0 ~ r5 (-0x18) -> SP 0x81d50 [__switch_task:] 6. /* save ipsw, ipc, r6, r7, r8, r9, r10 on the current process stack */ (-0x1C) -> SP 0x81d34 Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. hash done. 2. console command 'taskinfo'. 3. the scratchpad does not overflow after first context switch. Change-Id: If5d89ff5c945a777010492fcfb54bf41f434ed69 Reviewed-on: https://chromium-review.googlesource.com/317468 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Kunimitsu: enable power threshold checking in power upli feng2015-12-161-0/+2
| | | | | | | | | | | | | | | | | | In 0% battery case, if the charger can provide power at least 15 Watt(CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW), will allow system to boot up. BUG=chrome-os-partner:48339 BRANCH=none TEST=Verified in Kunimitsu system, system with 0% battery can boot up normally once charger power is 15 Watt. Change-Id: I0c7b23d4ac1e7bd2807ceeb068fc9018a99a03c4 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/318891 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: increase retry count in power upli feng2015-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | During power up, system will wait at most CHARGER_INITIALIZED_TRIES delay to check if battery percentage or negociated charger power can meet minimum requirement. In some cases, it takes longer time(observed negotiated to min power took 2 seconds). So increase CHARGER_INITIALIZED_TRIES from 10 to 40 to give total 4 seconds delay. BUG=chrome-os-partner:48339 BRANCH=none TEST=Verified in Kunimitsu system, negotiation to 5V@3A is done within retry/delay. Change-Id: I18c5fc676076f8d37d0a5360543f54aa85f48f77 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/318652 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
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