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* flash_ec: Disconnect EC-3PO interps when flashing.stabilize-7907.BAseda Aboagye2016-02-061-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Since the stm32 MCUs are programmed over the UART, we need to make some changes to allow the interpreter to stop listening to the UART PTY when flash_ec needs those PTYs. Otherwise, the EC-3PO interpreter will interfere with the programming and cause the flash to fail every time. BUG=chromium:571170 BRANCH=None TEST=Use flash_ec to program both veyron_jerry and samus_pd with no interruptions. TEST=Use flash_ec to program veyron_jerry without servod changes with no interruptions. CQ-DEPEND=CL:321084 CQ-DEPEND=CL:318900 Change-Id: I350fdb708d30c4ec6f18e5dc4abd621370522381 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/320629 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* nuc: Add support for CONFIG_LOW_POWER_S0.Mulin Chao2016-02-0610-43/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get better power consumption in S0, we add FW support for CONFIG_LOW_POWER_S0. Before entering deep idle in S0, we must enable Host interrupt to wake up EC if it needs to service LPC bus. This version also add a new bit of sleep_mask (SLEEP_MASK_FAN) in system.h to prevent EC enter deep idle if fan's duty isn't zero. Normally, the freq of PWM fan is 25 kHz. It means we must select apb2 clock as the source clock of PWM fan. Or fan would stop when ec enters deep idle because of no PWM signal. In hwtimer.c, we reset the preload counter to maximum value in ITEI32's ISR since preload counter is changed by __hw_clock_source_set all the time. We also found there're no event set if it's deadline is over 32 bits but current source clock isn't. To prevent ec doesn't wake-up in deep-idle even if ITIM32 expires, FW set an event for ITIM32 after process_timers(). Modified sources: 1. wheatley/board.h: Add CONFIG_LOW_POWER_S0 definition. 2. clock.c: Enable Host interrupt for LPC. 3. clock.c: Disable LP_WK_CTL for better power consumption. 4. gpio.c: Add ISR for Host interrupt. 5. uart.c: Introduce bit 6 of USTAT to make sure transmitting is completed. 6. register.h: Add uart_clear_pending_wakeup function. 7. hwtimer.c: Fixed watchdog issue when ITIM32 is closed to overflow. 8. fan.c: Enable deep sleep if duty cycle is zero. 9. include/system.h: Add SLEEP_MASK_FAN for fan control loop. 10. core/cortex-m/task.c: Add "isb" to flash the garbage data in the instruction pipeline. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ibe3630d0d68cf3f32206adb2afa1b5958916a2be Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/324651 Reviewed-by: Shawn N <shawnn@chromium.org>
* ectool: add inject-keys.pyLuigi Semenzato2016-02-052-0/+238
| | | | | | | | | | | | | | | | | | | A simple wrapper for "ectool kbpress" to do basic automation when working remotely (for instance, logging in). Includes a test script. BUG=b:26349756 TEST=ran on platform in various ways BRANCH=none Signed-off-by: Luigi Semenzato <semenzato@chromium.org> Change-Id: I96fdd99aa228b51cf22f9323facdc4ddb59db9ff Reviewed-on: https://chromium-review.googlesource.com/322286 Commit-Ready: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: Add initialization code required by TPM2 compliance tests.nagendra modadugu2016-02-051-0/+4
| | | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115 TEST=initial TPM2 tests pass Change-Id: Ie614f29e578fb177245c33e6d1a896534a8d6095 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/326180 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: Fix sleep mask for multi-port lock.stabilize-smaug-7897.BMulin Chao2016-02-041-8/+18
| | | | | | | | | | | | | | | | | | | This change use a simple counter to to prevent ec enter sleep if there's any i2c port active. Once there's no i2c port active, we enable sleep bit of i2c in i2c_lock() func. Please note FW disables interrupt during changing counter to prevent preemptive conditions. Modified sources: 1. common/i2c.c: Fix sleep mask for multi-port lock. BUG=crbug.com/537759 TEST=make buildall -j; test on wheatley when CONFIG_LOW_POWER_S0 is deifned. BRANCH=none Change-Id: I17c226108fee0e5d656fa157808179898f9a8dbf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/325256 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Modified the flash driver to retry operations as appropriate.Nadim Taha2016-02-041-38/+75
| | | | | | | | | | | | | | The max retry counts are based on the TSMC specification. This is a necessary change given that we're using their smart program/erase algorithms. BRANCH=none BUG=chrome-os-partner:45366 TEST=Tested RW updates. Change-Id: I18ca09e54ce13f2cf75dac32fb2457d5963ca040 Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/325535 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* kunimitus: add VCONN swap abilityli feng2016-02-032-0/+10
| | | | | | | | | | | | | BUG=none BRANCH=glados TEST=make -j buildall Change-Id: Ifa4273acbeab8b8463eddae2d9dde9c158f337a3 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/325529 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Fix signed vs unsigned typingShawn Nematbakhsh2016-02-033-5/+2
| | | | | | | | | | | | | | | | | | - ec_response_thermal_get_threshold.value is unsigned, so it can not be less than zero. - make power_button_wait_for_release() take a signed int, to match its existing usage. BUG=None TEST=`make buildall -j` BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie5748df3d9904d1e417adc38fee18f8cb3ce9750 Reviewed-on: https://chromium-review.googlesource.com/325840 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* util: ec3po: Add OOBM queue and dynamic loglevels.Aseda Aboagye2016-02-032-0/+25
| | | | | | | | | | | | | | | | | | | | | | This commit adds an Out Of Band Managament queue which will allow the console to receive commands outside of the PTY which it can take action on. The first use of this is to dynamically change the logging level. Prior to this change, changing the log level using dut-control would not affect the log level of the console or interpreter. BUG=None BRANCH=None TEST=Launch modified servod; issue dut-control loglevel:debug, verify that debug messages from both servod and ec3po are emitted. Then issue dut-control loglevel:info and verify that no debug messages from either are emitted. Change-Id: I692824742b018da9540a81305985f6f355f716e6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/325134 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* NPCX: Move control of PD GPIO hibernation state to boardAnton Staaf2016-02-032-16/+9
| | | | | | | | | | | | | | | | | | Use board_set_gpio_hibernate_state to configure the PD GPIO's to support charging while hibernating. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I7b960967670c07f4861a59345bc23c97d3f61cc0 Reviewed-on: https://chromium-review.googlesource.com/325443 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Enforce compilation without system headersStefan Reinauer2016-02-0317-11/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces HOST_CPPFLAGS to be used for all objects being compiled with HOSTCC rather then the target compiler. Since glibc is not linked into the EC, no glibc include files should be included in the EC code base. Hence, create local definitions for clock_t and wchar_t that match what the glibc include would have done, and remove some unneeded includes. Due to very eager optimization, we have to give gcc a little notch to not kick out memset. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:43025 BUG=chrome-os-partner:49517 BRANCH=none TEST=compile tested Change-Id: Idf3a2881fa8352756b0927b09c6a97473358f239 Reviewed-on: https://chromium-review.googlesource.com/322435 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* Chell: Setting battery charging maximum value of temperatureBruce2016-02-032-0/+34
| | | | | | | | | | | | | | | | | | | | | Setting battery charging maximum value of temperature. If battery temperture is over than 45 degree, set charge current to 0 mA, and charge state to idle. Then LED will turn to white in idle state. BUG=chrome-os-partner:49695 BRANCH=glados TEST=check the battery will not charge when battery temperture is over than 45 degree, and LED turn to white. Then temperture is less than 45 degree, the battery will charge and LED turn to amber. Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/323982 Reviewed-by: Shawn N <shawnn@chromium.org> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 4994d85d3b6c589e3ac297697aeb36456f2401a6) Change-Id: Ic7d3fe0c482fab76041c5ae3f35402e529576b1c Reviewed-on: https://chromium-review.googlesource.com/325487
* util: ec3po: Change console permissions to 660.Aseda Aboagye2016-02-031-3/+2
| | | | | | | | | | | | | | | | | 666 gives out permissions to everyone and should be avoided. A similar change is made in servod. BUG=None BRANCH=None TEST=Run console.py and verify that the created PTY has the permissions of 660. Change-Id: Ib58952af5f9681fdc2ef351b2c2ac2ec10109095 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/325493 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: fix unaligned memory accesses in dcrypto/aes.nagendra modadugu2016-02-031-4/+4
| | | | | | | | | | | | | BRANCH=none TEST=new tests under test/tpm2/ pass. BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: Ibfc92eae8238954a861a8e91432f90db6d174ead Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/325495 Commit-Ready: Vadim Bendebury <vbendeb@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* kunimitsu: lars: enable USB PD logging.Todd Broch2016-02-032-0/+4
| | | | | | | | | | | | | | | | | | Enable USB PD logging. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=chrome-os-partner:45933 BRANCH=none TEST=make -j buildall make -j BOARD=kunimitsu tests Change-Id: I05f80712e2efe59a3a3cdf333885b111cc79953b Reviewed-on: https://chromium-review.googlesource.com/325380 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* CR50: fix incomplete hash state initialization.nagendra modadugu2016-02-021-0/+3
| | | | | | | | | | | | | | | | The hashAlg field is expected to be populated by _cpri__StartHash. BRANCH=none TEST=new tests under test/tpm2/ pass. BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I237183c916fa800a82853aee8def7d734f53d6e9 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/325386 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* charger/Kunimitsu: Fix for boot from cut-off batteryVijay Hiremath2016-02-025-22/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Battery in cut-off mode wakes when voltage is applied to the PACK and takes approximately 2 to 3 seconds to initialize before capable of providing the power. Hence made the battery present status to BP_NO in case of cut-off mode. Once the battery is ready new status is updated as BP_YES. When the battery status changes from BP_NO to BP_YES, charger input current is set to board specific charger input current which is not sufficient to boot the AP hence the system reboots. To avoid this issue, added code to write charger manager negotiated current to charger input current when the battery status changes from BP_NO to BP_YES. BRANCH=none BUG=chrome-os-partner:49224 TEST=Manually tested on Kunimitsu. Used console command 'cutoff' to put the battery in cut-off mode. Inserted the adopter to wake the system, system doesn't reboot & the battery charges. Change-Id: Ia5a1457506b4bef0b3dd27993e4b60ae64c8f746 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/322430 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc: Reduce the period of watchdog check timerCHLin2016-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | There is probability to fail in firmware_ECWatchdog FAFT test by using CONFIG_WATCHDOG_PERIOD_MS period for check timer. Use CONFIG_AUX_TIMER_PERIOD_MS instead can fix it. Modified drivers: 1. watchdog.c: change watchdog check timer period from CONFIG_WATCHDOG_PERIOD_MS to CONFIG_AUX_TIMER_PERIOD_MS. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I93e700968751ecd58f032c2f5866cf4f2eb0ffe4 Signed-off-by: CHLin <chlin56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/324712 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: define EMBEDDED_MODE=1 for code under cr50.nagendra modadugu2016-02-021-0/+2
| | | | | | | | | | | | | | | | | | EMBEDDED_MODE was missing from code compiled under cr50/tpm2, which resulted in code under third_party/tpm2 and cr50/tpm2 inferring differing declarations for a given type. BRANCH=none TEST=tests under test/tpm2 pass BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I56935f5ae8fc45e6b7f71eb239b3e0c325086795 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/325471 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* pd: Reinitialize state variables on TCPC resetShawn Nematbakhsh2016-02-021-2/+5
| | | | | | | | | | | | | | | | | Resetting our state to default without also resetting the power role may lead to a state / role mismatch. BUG=chrome-os-partner:49563 TEST=Verify kunimitsu correctly detects charger at either polarity on sysjump. BRANCH=glados Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I239df9793773429e9b84a847e55d6753577fab32 Reviewed-on: https://chromium-review.googlesource.com/325385 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: signer should be a dependency for RW_B target tooVadim Bendebury2016-02-021-0/+1
| | | | | | | | | | | | | | | | | | | The makefile is missing an explicit dependency which ensures that the signer utility is available by the time the RW_B image is built. This works most of the time, but once in a while RW_B gets ahead in the race and the build fails. Adding explicit dependency will prevent this from happening. BRANCH=none BUG=chromium:578761 TEST=make buildall -j still succeeds. Change-Id: I7f5223f51e71b1d78de012bf5d934f1a17c86cc0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/325031 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Don't declare functions inline that aren't always defined as suchPatrick Georgi2016-02-022-3/+3
| | | | | | | | | | | | | | | | | | gcc 5.2 bails out on an inline declaration that isn't followed up with a definition in the same compilation unit. BRANCH=none BUG=chrome-os-partner:49517 TEST=compile tested with coreboot's toolchain. samus, oak and others that failed now build. Change-Id: Ic9c28fc12c80e24ea0dbf85f35846fd6a0b56a2d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/324970 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* chell: Enable S0ix power state supportDuncan Laurie2016-02-012-2/+3
| | | | | | | | | | | | | | | | Enable the config option for S0IX power control and set the GPIO to use power_signal_interrupt_S0. BUG=chrome-os-partner:49274 BRANCH=glados TEST=echo freeze > /sys/power/state Unfortunately currently SLP_S0_L is not asserting so this is difficult to actually test the EC behavior Change-Id: I302da7735c9622975e0386a0b4542f41c7231df9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324567 Reviewed-by: Shawn N <shawnn@chromium.org>
* Fix null pointer check in tokenFilename()Stefan Reinauer2016-02-011-1/+2
| | | | | | | | | | | | | | | | | | | From https://scan.coverity.com/projects/chromium-ec : CID61407: Dereference after null check The home directory that is received from getpwuid() needs to be assigned to home but it wasn't. BUG=none BRANCH=none TEST=build tested Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I36c30906e1388e2f8a0d466d516a5ffa6ae70bf6 Reviewed-on: https://chromium-review.googlesource.com/324637 Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Fixed soft resets on silicon.Nadim Taha2016-02-012-56/+87
| | | | | | | | | | | | | | Fixed the peripheral clock enable definitions and enabled the low speed timers. BRANCH=none BUG=none TEST=Tested soft resets on silicon. Change-Id: Ie63e5732e5bead174abda89e5c5069b818212e9b Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324843 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Removed references to FPGA-only registers from the bootloader.Nadim Taha2016-02-011-6/+2
| | | | | | | | | | | BUG=none BRANCH=none TEST=Booted to an RW image on silicon. Change-Id: Iadca3c05cfd095427867d877e4a916c999a9cdb3 Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324803 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Kunimitsu: Change the battery minimum voltage valueVijay Hiremath2016-01-311-1/+1
| | | | | | | | | | | | | | | | | Charger Low_VSYS_Prochot# threshold voltage assertion is set to 6V hence increased the minimum battery voltage to 6.1V to avoid unwanted Prochot# assertions. BUG=none TEST=Drained the battery to 6.1V, Prochot# pin did not assert. BRANCH=glados Change-Id: Ie5d4decf3327a45d64638771dd8a5fc7017db261 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/324564 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: implement _cpri__StirRandom as a no-op.nagendra modadugu2016-01-293-8/+12
| | | | | | | | | | | | | | | | Stirring the random pool on CR50 is not currently supported, so just implement as a no-op. TEST=none BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I32b0144737139e524d4f71a11cc9d4ad939cd9cb Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/324620 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* it8380dev: util: Enhance iteflashDonald Huang2016-01-291-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add verify function. BRANCH=none BUG=none TEST=Test OK on ITE8390CX. You can run "make -j BOARD=it8380dev" to build ec.bin and flash the ec.bin via "sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin" /* ==SNAPSHOT START== */ (cr) (b-verify) donald@donald-nb ~/trunk/src/platform/ec $ sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin Waiting for the EC power-on sequence ...CHIPID 8390, CHIPVER 82, Flash size 256 kB Done. CHIPID 8390, CHIPVER 82, Flash size 256 kB Erasing chip... /100% Writing 262144 bytes at 0x00000000 Done. Verify 262144 bytes at 0x00000000 -100% Verify Done. /* ==SNAPSHOT END== */ Change-Id: Iac08e2eeb934c3a4a721e17a85de628ea4d9d065 Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/322524 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chell: Trigger PMIC shutdown rather than hibernateShawn Nematbakhsh2016-01-281-9/+17
| | | | | | | | | | | | | | | | | | Shut down all PMIC-supplied power rails rather than initiating EC / PD hibernate. This results in considerable power savings. BUG=chrome-os-partner:48835 BRANCH=glados TEST=Manual on chell. Run "hibernate" on EC console, verify that 3.3V EC DSW rail goes to 0V, and the EC powers up on zinger insert, lid open or power button press. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I7bf0c494ea240183240f5a6abc3d611df8efb45a Reviewed-on: https://chromium-review.googlesource.com/324087 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add hibernate board-level callbackShawn Nematbakhsh2016-01-287-0/+25
| | | | | | | | | | | | | | | | | Allow boards to take action (such as entering a custom low-power hibernate-like state) before putting the chip into hibernate state. BUG=chrome-os-partner:48835 BRANCH=glados TEST=Manual with subsequent commit on chell. Verify board-level hibernate callback is called when "hibernate" is run on EC console. Change-Id: Ie1da044037a74ff8bce5c822f28ce837c62ceec0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324086 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Fixes the SFDP_BITFIELD() macro.Nadim Taha2016-01-291-1/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=<redacted> Change-Id: If6e2732a29e084417ba1d2f80732ac412028342a Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324622 Reviewed-by: Ewout van Bekkum <ewout@chromium.org>
* Fix bug in software sha256_hash()nagendra modadugu2016-01-282-4/+3
| | | | | | | | | | | | | | | | | The implementation for sha256_hash() copied and incorrect number of bytes to the output. This change provides a fix and a test. TEST=added test case BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I74e98c6f5005a14dd5c0ca19ea7540622dd6c7d7 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/324391 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Kunimitsu: Fixing build error when enabled CONFIG_GYRO_L3GD20HAkshu Agrawal2016-01-281-1/+1
| | | | | | | | | | | | | | | Fixing a typo which causes build error when building with GYRO_L3GD20H BUG=None BRANCH=master TEST=build and run with #define CONFIG_GYRO_L3GD20H Change-Id: I04abb4bff9cdf9208ff224de74188315094fb941 Signed-off-by: Akshu Agrawal <akshu.agrawal@intel.com> Reviewed-on: https://chromium-review.googlesource.com/323630 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: adds the ability to configure muxed inout peripheralsEwout van Bekkum2016-01-282-1/+6
| | | | | | | | | | | | | | | | Adds the the code necessary to support muxed inout peripherals on cr50 like SPS and SPI0 by adding a new signnal to pin connection flag. Note these are for direct wired peripherals where no muxing is necessary, the input pads just need to be enabled. BRANCH=none BUG=none TEST=verified pinmux registers through m3 Change-Id: I1a375a3a14fb44fc4f9ced764fd2c54bb2b91e22 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/323848 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* common: Adds a JEDEC SFDP v1.* based Serial NOR Flash driverEwout van Bekkum2016-01-284-0/+1116
| | | | | | | | | | | | | | | | | | | | | Adds a JEDEC SFDP v1.* compatible Serial NOR Flash driver to control multiple Serial NOR Flash devices (NOR EEPROMs, etc.). The SFDP tables are used to discover parts' page sizes and capacities. This driver only supports parts with capacities under 4GiB. If the parts are larger than 16MiB, then the 0xB7 4-Byte addressing mode entry opcode and 0xE9 4-Byte addressing mode exit opcode are required. This driver also assumes that a 4KiB erase opcode of 0x20 is always available. BRANCH=none BUG=none TEST=Tested on cr51 with multiple EEPROMs with various SFDP revs Change-Id: I5c2b757267e23c4f22ac89c6d5048a54b04de0c3 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321922 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Modified the bootloader to check PMU_PWRDN_SCRATCH30 and load the newerNadim Taha2016-01-283-7/+108
| | | | | | | | | | | | | | | | of the two RW images if set. Imported the Haven "signed_header.h" file into chip/g and fixed prior references to the util/ copy. BUG=none BRANCH=none TEST=Went through a full update. Simulated a botched update. Change-Id: I1e4c006ef391270a7e350fea6f43cc1a1b057d0e Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324109 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* common: Adds JEDEC SFDP v1.0 & v1.5 encoding and decodingEwout van Bekkum2016-01-281-0/+807
| | | | | | | | | | | | | | | Adds a header with JEDEC SFDP v1.0 (JESD216) & v1.5 (JESD216A) encoding and decoding support to enable a part agnostic Serial NOR Flash driver. BRANCH=none BUG=none TEST=Tested through the spi_nor driver Change-Id: I00b3f0434bfb8582aebad7cd0682445980b57773 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321921 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* chip: it83xx: fix EC interrupt vector registers issueDino Li2016-01-288-38/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a limitation for EC interrupt vector registers. System may read incorrect interrupt number in ISR so we need to add a workaround to prevent it. The following is a example that got incorrect interrupt number: 1. REG IVCTx = 0x10. (no interrupt pending) 2. EC INT6 interrupt occurs (IVCTx = 0x16) and jump to ISR. 3. Read interrupt vector register to determine interrupt number. 4. Higher priority interrupt of same interrupt group occurs (for example: INT134, IVCTx = 0x96) while the system is reading the interrupt vector register for EC INT6, we may end up with an incorrect interrupt number between 0x16 and 0x96. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. EC interrupts work normally: WUI (GPIO interrupt), timer, uart, LPC, I2C, and PECI. 2. Console command 'taskinfo'. Change-Id: I54e61f417ad506eb3b4cd5d0652f64eed9a28a17 Reviewed-on: https://chromium-review.googlesource.com/322097 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: updates watchdog and hw clock to use hw regdefsEwout van Bekkum2016-01-282-6/+5
| | | | | | | | | | | | | | This commit updates the cr50 watchdog and hwtimer drivers to use the hardware header specified regdefs to determine the frequencies for the cr50 device. BRANCH=None TEST=Verified gettime and watchdog behavior on cr51 BUG=chrome-os-partner:46737 Change-Id: Iec7dc56b160dbec1b71077cecfd5561436d6f3ab Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321867 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* tcpc: add support for TCPC with integrated high-speed muxesVincent Palatin2016-01-274-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | The TCPCI specification defines ane optional register 18h 'CONFIG_STANDARD_OUTPUT' providing a standardized way of steering the high-speed muxes. Implement the feature as a usb_mux_driver, under the conditional flag CONFIG_USB_PD_TCPM_MUX. The USB PD port index should be set in the port_addr field of the 'usb_mux' structure. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:49605 TEST=run pdeval-stm32f072 connected to a Parade PS8751 board and test USB/DP muxing. Change-Id: I7e5f0b8ec70b1910b2cff9d106514baca8c899e5 Reviewed-on: https://chromium-review.googlesource.com/322956 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* GPIO: Remove gpio_get_level_reg functionAnton Staaf2016-01-273-31/+8
| | | | | | | | | | | | | | | | | | | | After talking with Simon Glass about this we concluded that this was an optimization that is not needed, as such, and since it is only used in one location and only available from one chip family I'm removing it. This further simplifies the GPIO API and removes more uses of port/mask pairs. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I40754a385e0a4fa3a56d67fca1dd59fc8f3cc85a Reviewed-on: https://chromium-review.googlesource.com/323827 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* GPIO: Remove GPIO_TO_PORT_MASK_PAIRAnton Staaf2016-01-271-5/+0
| | | | | | | | | | | | | | | | | This macro is no longer used, removing it so that it doesn't get used as we work towards removing port/mask from the public GPIO API. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ic924cd520689c0805a2784be5005dbecfe89f389 Reviewed-on: https://chromium-review.googlesource.com/323873 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* GPIO: Use gpio_reset in a few more placesAnton Staaf2016-01-272-20/+7
| | | | | | | | | | | | | | | | | | The new gpio_reset function simplifies the pattern used in this code, that of returning a GPIO to its original configured state. It also removes a few instances of using port/mask pairs. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I6e411aaf2f0fbc18aca0ed8742c400a0efe5690d Reviewed-on: https://chromium-review.googlesource.com/324059 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* glados / chell: Power Optimize S0ix PMIC VRsShawn Nematbakhsh2016-01-262-0/+24
| | | | | | | | | | | | | | | | Allow VCCIO to decay to 0 and reduce the voltage of V0.85A supply in S0ix. BUG=chrome-os-partner:43908 TEST=Stress-test glados stability coming into and out of S0ix BRANCH=glados Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5aa61164c43ac624cef86f478919294e4cd4e581 Reviewed-on: https://chromium-review.googlesource.com/293345 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* nuc: Fixed the bug of i2c caused by writing START bit in SMBCTL1.Mulin Chao2016-01-261-56/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In rare case, executing i2c_interrupt function will generate unnecessary START condition if START bit is 1 in SMBCTL1. Please see the layout of SMBCTL1 register below. Bit [7] - STASTRE Bit [6] - NMINTE Bit [5] - GCMEN Bit [4] - ACK Bit [3] - EOBINTE Bit [2] - INTEN Bit [1] - STOP Bit [0] - START In order to set or clear bits of INTEN and NMINTE, we need to read SMBCTL1, or the bit2,6 and write back to register. But we will issue unnecessary START condition if bit 0 is 1. (ie. Start condition is not sent yet) Then FW will receive unexpected SDAST interrupt and sometime it collapses state machine when i2c receives NACK condition. The solution is enabling these two bits in i2c_init_bus function. Using task_enalble/disable_irq (NVIC register) to enable or disable i2c interrupts instead. Modified sources: 1. i2c.c: Fixed the bug of i2c caused by writing START bit in SMBCTL1. 2. i2c.c: Add more debug messages for unexpected bus state. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I37dbb0e5b61f4a5ba12f0638535f8031522c1711 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/322883 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip: it83xx: update ec2i moduleDino Li2016-01-262-122/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. The previous EC2I module does not meet section '7.17.5 EC2I Programming Guide'. We need to correct it to prevent conflict with H2RAM (LPC I/O cycles 800h ~ 9ffh) which cause LPC keeps long wait states. NOTE: If EC is using EC2I internal bus to access PNPCFG registers while host accessing EC ram through H2RAM interface at the same time, the symptom will appear. 2. Remove 'CONFIG_IT83XX_PNPCFG_HOST_ACCESS'. We don't allow the host access PNPCFG registers. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. To use console command 'rwreg' to r/w PNPCFG registers and there is no error code return. 2. To create a stress test for this change. - EC use 'ec2i_read()' and 'ec2i_write()' to access PNPCFG registers per-10ms. - run ectool 'version' command per-100ms. Before the change was made, LPC will keep in long wait states immediately. After the change, we run the test of ectool 'version' command over 20000 times. Change-Id: I84e86fc17ef624d4a60a1a051bc301ebdf56a3da Reviewed-on: https://chromium-review.googlesource.com/323563 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* GPIO: Prefer gpio_set_flagsAnton Staaf2016-01-263-46/+38
| | | | | | | | | | | | | | | | | | | Convert some uses of gpio_set_flags_by_mask to plain gpio_set_flags. The result is usually more readable due to being able to use the GPIO_* enum names, and it removes more instances of port/mask implementation details leaking outside the gpio.c chip specific code. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I06a7ad8a53e553a8e432a6abb5b38c25a98df6c6 Reviewed-on: https://chromium-review.googlesource.com/323815 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chell/glados/kunimitsu/tlars: Enable temporary host storageDuncan Laurie2016-01-254-14/+50
| | | | | | | | | | | | | | | Enable the temporary secure storage feature for vboot on skylake. BUG=chrome-os-partner:46075 BRANCH=none TEST=tested on glados and chell with modifed coreboot Change-Id: Ic01888f7578e8e04bb39b38651bb646d1fc20750 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315223 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* ec: Add temporary secure storage for the host during bootDuncan Laurie2016-01-255-0/+183
| | | | | | | | | | | | | | | | | | | This adds a temporary secure storage interface for the EC to be able to store small amounts of data from the host that is locked until the chipset resets. This is used by pre-memory verified boot on x86 systems where we need to know which RW slot to boot and what the hash is to ensure that we can resume from S3 safely. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I5fa91046437479bcae69a8fca4c989b0ef554bbf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315222 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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