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* cr50: enable AP and EC flash accessstabilize-8249.BMary Ruthven2016-04-264-0/+23
| | | | | | | | | | | | | | | | | | | | | The cr50 SPI master can control the external AP and EC SPI ROM. This change adds support for doing spi_transactions, but does not use the SPI transactions for anything except console commands. This support will be used for flashing the AP and EC through CCD. For now AP and EC flash select must be done manually using the spi_flash_select console command. Flash select should be disabled after use, because it will prevent the system from booting. BUG=chrome-os-partner:50701 BRANCH=none TEST=Enable spi_flash commands. Select AP ROM and verify spi_flashinfo, read, erase, and write commands work properly. Select EC ROM and verify the same commands. Change-Id: I16c55015794f8513effe0fa5712488a84bed2627 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339844 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Fix port enable check for low power idleShawn Nematbakhsh2016-04-252-2/+2
| | | | | | | | | | | | | | BUG=chrome-os-partner:52734 BRANCH=glados TEST=Plug 2 PD chargers on sentry, remove the first, verify that SLEEP_MASK_USB_PD is not briefly cleared. Change-Id: I62309194d8b5a694487282434fc63b5f39301ba3 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340564 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* STM32: Support LPUART consoleDaisuke Nojiri2016-04-256-5/+42
| | | | | | | | | | | | | | | This patch adds support for console on LPUART (low power UART). It is wired to the USB type B port on the board, which is also one of the power sources. So, using LPUART simplifies the set up. BUG=none BRANCH=tot TEST=Verified console works on stm32l476g-eval. make buildall Change-Id: Iccf697cfabdcb7e1362d8453708eb79610d2e0cb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340101 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Bring up STM32L476G-EvalDaisuke Nojiri2016-04-2518-16/+508
| | | | | | | | | | | | | This patch adds initial set of files to bring up STM32L476G-Eval board. BUG=none BRANCH=tot TEST=Tested console. make buildall && make tests Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340100 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* STM32: Add dma_select_channelDaisuke Nojiri2016-04-254-0/+38
| | | | | | | | | | | | | | | dma_select_channel selects which stream (peripheral) to be used on a specific channel. Some STM32 chips simply logically OR requests, thus do not require this selection. BUG=none BRANCH=tot TEST=make buildall && make tests. Verified on stm32l476g-eval. Change-Id: I7b64b78bdec80658992f58cb4c94ade972a1081c Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340107 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* snoball: GPIO changes for proto 1Shawn Nematbakhsh2016-04-253-152/+6
| | | | | | | | | | | | | BUG=chrome-os-partner:52690 BRANCH=None TEST=`make buildall -j` Change-Id: I787e8bc2fb5ca04a0879eeec7a8d7169e36b7661 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340445 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* elm: modifications for EVTKoro Chen2016-04-254-16/+25
| | | | | | | | | | | | | | | | This add modifications for EVT, including: - Use SPI for KX022 motion sensor on the daughterboard - remove TMP432 - Use PF2 to control the external power of ANX7688 BRANCH=none BUG=chrome-os-partner:52245 TEST=make BOARD=elm -j Change-Id: I7d4021746bc8a2be0028076a5c3aeefd8736c1b0 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/337338 Reviewed-by: Rong Chang <rongchang@chromium.org>
* Move include/byteorder.h -> builtin/endian.hnagendra modadugu2016-04-222-28/+39
| | | | | | | | | | | | | | | | Move endian routines to builtin/ so that portable third_party code may build without glibc. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=none Change-Id: Icb900d1e9c56dc68ec1ef4b536ebc9dcf6ebcd69 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/340432 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ectool: Revert "ectool: Remove CROS_EC_DEV_IOCRDMEM"Gwendal Grignou2016-04-224-39/+70
| | | | | | | | | | | | | | | | | CROS_EC_DEV_IOCRDMEM must be used on architecture where legacy IO mapped registers are accessed inderectly via EMI. The kernel is taking care of the translation. TEST=Check on reks that we need to use the IOCTL. BUG=chrome-os-partner:52550,chromium:602832 BRANCH=none This reverts commit de45353bbdf0 ("ectool: Remove CROS_EC_DEV_IOCRDMEM"). Change-Id: I8efad56df90c58c25bdc9ccd70a508547e629a77 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340348 Reviewed-by: Shawn N <shawnn@chromium.org>
* Add the memmove() function prototype to builtin/string.hnagendra modadugu2016-04-221-0/+1
| | | | | | | | | | | | | | | | | Add memmove() to builtin/string.h so that portable third_party code may build without glibc. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=none Change-Id: I8c165d71d9c01d2f869329b3600aac0970f41e71 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/340293 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* elm: Modify battery cutoff commandDavid Huang2016-04-211-20/+7
| | | | | | | | | | | | | | | Modify battery cutoff command for EVT BRANCH=elm BUG=chrome-os-partner:52548 TEST=Use "ectool batterycutoff" to check battery enter shipmode. Change-Id: Ia0c620f95d6e94ec658f92c5b56cbab3ae964848 Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/340168 Commit-Ready: 志偉 黃 <David.Huang@quantatw.com> Tested-by: Koro Chen <koro.chen@mediatek.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Add the memcmp() function prototype to builtin/string.hnagendra modadugu2016-04-211-0/+1
| | | | | | | | | | | | | | | | | Add memcmp() to builtin/string.h so that portable third_party code may build without glibc. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=none Signed-off-by: nagendra modadugu <ngm@google.com> Change-Id: Id52c9c76fceac94bf1998958b43f42ad5d5298d3 Reviewed-on: https://chromium-review.googlesource.com/339878 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Bill Richardson <wfrichar@google.com>
* nucleo-f072rb: Add initial set of board filesDaisuke Nojiri2016-04-207-0/+149
| | | | | | | | | | | | | | | This change adds files to support nucleo-f072rb. This board can be used as a DUT to test STM32F072. BUG=none BRANCH=tot TEST=Verified EC console works. Flashed the board by 'make flash'. User LED brinks periodically and when user button is pressed. make buildall && make tests Change-Id: I628f229b62c4b06d19d8245121f79a13e17bc2e9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338461
* kevin: Fix test buildShawn Nematbakhsh2016-04-201-0/+2
| | | | | | | | | | | | | BUG=None TEST=`cros_workon-kevin start chromeos-ec; emerge-kevin chromeos-ec` BRANCH=None Change-Id: Ia2916a9c97f9d981954cdc0506bffb0ee239b256 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339745 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* CR50: add support for RSA key generationnagendra modadugu2016-04-208-25/+1150
| | | | | | | | | | | | | | | | | Prime generation uses a sieve to amortize division with small primes. Otherwise this a standard Miller-Rabin implementation. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I9f84d1f9c911f6146e4bd80296f75157a191552d Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/335222 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* elm: kionix: allow dynamic selection of SPI or I2C transportKoro Chen2016-04-204-8/+68
| | | | | | | | | | | | | | This CL ports c9832e04f1528 to Kionix accel driver. And also enables SPI access of Elm's base kx022. BUG=none BRANCH=none TEST=manual Change-Id: I0c1de028c82fc62a124bb5b930a3882c4b368d71 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/331851 Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* CR50: add support for P256-ECIES (hybrid encryption)nagendra modadugu2016-04-1911-0/+571
| | | | | | | | | | | | | | | | | | Add support for P256 based hybrid encryption, and corresponding tests. Where hybrid encryption is: P256 based DH + AES128 + HMAC-SHA256. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 CQ-DEPEND=CL:336091,CL:339561 TEST=ECIES tests in test/tpm/tpmtest.py pass Change-Id: Ie091e278df72185a6896af0e498925e56404f87e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/337340 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: remove DCRYPTO_p256_points_mul, add DCRYPTO_p256_point_mulnagendra modadugu2016-04-193-48/+23
| | | | | | | | | | | | | | | | | | | points_mul (variable time) is only necessary for ECDSA verification, and is not required as part of the public dcrypto API. Replaced wih (constant time) point_mul, and add corresponding parameter checks to the tpm2 interface call _cpri__EccPointMultiply. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I4ec885c147755e8a645c51b9a461b81c3a3b310f Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/338851 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: add support for RSA key "testing"nagendra modadugu2016-04-197-20/+484
| | | | | | | | | | | | | | | | | | | | | | Implement _cpri__TestKeyRSA, which computes the modulus and private exponent given a pair of primes, or computes the second prime and private exponent given the modulus and one prime. The _cpri__TestKeyRSA call is used to determine whether the components of an RSA key match each other. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I2c68d844f4bab207588cbda5c962b09078519a1a Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/330466 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: move AES CTR implementation to dcryptonagendra modadugu2016-04-193-29/+40
| | | | | | | | | | | | | | | | AES CTR will be necessary to implement hybrid encryption and hence needs to be a part of the dcrypto library. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I5dffe5d3a15748614db36aebdbcd50bde31bfdb2 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/339561 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* snoball: Add support for proto 0.9 boardShawn Nematbakhsh2016-04-197-163/+91
| | | | | | | | | | | | | | | | This board uses a different stm32f0 MCU and has significant architectural changes. BUG=chrome-os-partner:50549 BRANCH=None TEST=`make buildall -j`, verify snoball boots to console Change-Id: I842a3efc5e179b33bbf0441e8d4ea07fa006e3fe Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329439 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: shi: Remove excessively verbose printsShawn Nematbakhsh2016-04-192-14/+18
| | | | | | | | | | | | | | | | | Remove verbose prints (most of which are printed in ISRs) by default to eliminate SHI console spam. BUG=chrome-os-partner:52372 BRANCH=None TEST=Verify console isn't spammy while SHI is in use on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0dbd43e01f37980bc0e9d14fa6349a7ecb8c6f47 Reviewed-on: https://chromium-review.googlesource.com/339493 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: shi: Remove support for V2 host protocolShawn Nematbakhsh2016-04-191-168/+4
| | | | | | | | | | | | | BUG=chrome-os-partner:52372 BRANCH=None TEST=Verify V3 host command interface is still functional. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I75e684f3fbce764965ddac47b8314ed298086d74 Reviewed-on: https://chromium-review.googlesource.com/339472 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: shi: Don't enable GPIO_SHI_CS_L GPIO interrupt until S0Shawn Nematbakhsh2016-04-192-5/+28
| | | | | | | | | | | | | | | | | | Prior to going to S0, GPIO_SHI_CS_L may be low, which can cause glitches in the SHI HW unit. Enable the GPIO interrupt in S0, and disable it when leaving S0. BUG=chrome-os-partner:52222,chrome-os-partner:52217 BRANCH=None TEST=Manual on kevin. Verify 'ectool version' succeeds with subsequent kernel / ectool patches. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie3494122c2486429d3f648ab9220daf5dd34f812 Reviewed-on: https://chromium-review.googlesource.com/338857 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Deferred: Remove hard coded number of deferredsAnton Staaf2016-04-1930-100/+56
| | | | | | | | | | | | | | | | | | | | | | | | Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip: it83xx: add USBPD moduleDino Li2016-04-189-6/+713
| | | | | | | | | | | | | | | | | | | Add USBPD module for it8320 emulation board BRANCH=none BUG=none TEST=manual plug zinger adapter, connect uart console and type commands: pd 1 dev [20|12|5] pd 1 charger pd 1 swap power and check PD states Change-Id: I9ca1822deeb4b4dce1279a09490ed4175890cf3a Signed-off-by: Leon-Lee <leon.lee@ite.com.tw> Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/326230 Reviewed-by: Shawn N <shawnn@chromium.org>
* Deferred: Use deferred_data instead of function pointerAnton Staaf2016-04-1858-195/+230
| | | | | | | | | | | | | | | | | | | | | Previously calls to hook_call_deferred were passed the function to call, which was then looked up in the .rodata.deferred section with a linear search. This linear search can be replaced with a subtract by passing the pointer to the deferred_data object created when DECLARE_DEFERRED was invoked. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None CQ-DEPEND=CL:*255812 TEST=make buildall -j Change-Id: I951dd1541302875b102dd086154cf05591694440 Reviewed-on: https://chromium-review.googlesource.com/334315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: fix usb console LF handlingVadim Bendebury2016-04-181-13/+9
| | | | | | | | | | | | | | | | | | | | | | | It was observed that when connecting to the CR50 console over USB, there the line feed (LF) characters are not supplemented by carriage return (CR), which causes weird console output. Detailed examination has shown that uart_putc() does not do the right thing itself and also bypasses __tx_char() used by uart_puts(), which does the right thing. The simplest solution is to have uart_putc() re-use all the smarts of uart_puts(). BRANCH=none BUG=none TEST=verified that usb console output does not suffer from the "lost CR" syndrome any more. Change-Id: I2a1f84b2524c41eb6e84186141b0b9ac55e87ee0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339217 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* tcpm: update code to support multiple tcpm driverKevin K Wong2016-04-1722-223/+407
| | | | | | | | | | | BUG=chromium:593822 BRANCH=none TEST=make buildall Change-Id: Ic30c1b890da7639aa80a53040ecc5bebfb4be2e8 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336030 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Change SYS_RST output to SYS_RST_L inoutBill Richardson2016-04-163-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This signal should be active low, not active high. In addition, not only can we pull it low but so can other components. If something else asserts it, we need to react. This changes the polarity and sets up the interrupt handler. A future CL will be needed to make the handler do something useful. BUG=chrome-os-partner:52366 BRANCH=none TEST=make buildall; test on Cr50 On the test board, short M0 to ground to trigger the interrupt. Watch the input value with gpioget You can drive the output (and trigger the interrupt) with gpioset SYS_RST_L_OUT 0 gpioset SYS_RST_L_OUT 1 Change-Id: I3556963859601f43f990fc83f26d2cea919383c6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339214 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Remove HOSTCMD taskBill Richardson2016-04-151-1/+0
| | | | | | | | | | | | | | This should have been done along with commit fabb15c70628c44a79. Nothing invokes the hostcmd task, so let's kill it off. BUG=none BRANCH=none TEST=make buildall; test on cr50 Change-Id: I1f86d21b44392708e0ff7cc9173b47edda129e00 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339225 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Add DIO_PULL_UP and DIO_PULL_DOWN flagsBill Richardson2016-04-152-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In board/*/gpio.inc, we can specify pullups and pulldowns on pads connected to GPIOs, like so: GPIO(SOME_BUTTON, PIN(0,0), GPIO_INPUT | GPIO_PULL_UP) This adds flags to do the same thing for pads that connect to internal periperals: PINMUX(FUNC(UART0_RX), A1, DIO_PULL_UP) BUG=chrome-os-partner:51410 BRANCH=none TEST=make buildall; manual test on Cr50 I added these flags to the gpio.inc file and tested the result: PINMUX(FUNC(I2C0_SCL), B0, DIO_INPUT | DIO_PULL_UP) PINMUX(FUNC(I2C0_SDA), B1, DIO_INPUT | DIO_PULL_DOWN) The "pinmux" console command showed that the new flags took effect: Before: 400600a0: DIOB0 0 IN 400600a8: DIOB1 0 IN After: 400600a0: DIOB0 0 IN PU 400600a8: DIOB1 0 IN PD Change-Id: I1d212331431ef67b2f1bcece8729d092b9ad5ba8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339254 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* cr50: Enable RD DetectionMary Ruthven2016-04-151-0/+3
| | | | | | | | | | | | | | | | | When a debug accessory is detected by cr50, the USB controller switches to using the CCD PHY and switches back to the AP PHY when the cable is disconnected. This change also enables controlling the UART TX output for the AP and EC console. BUG=chrome-os-partner:50700 BRANCH=none TEST=Attach suzy Q and verify the PHY is set to B. Detach Suzy Q and check the phy has switched to A. Change-Id: I07f4c4fb7f765788a0914dfc2451a11af8bf0ab2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339211 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: enable AP and EC UART in CCD MODEMary Ruthven2016-04-155-29/+102
| | | | | | | | | | | | | | | | | When the debug cable is plugged in enable the EC and AP UART output. Disable the output when the cable is disconnected so servo can use the UARTs. BUG=chrome-os-partner:52322 BRANCH=none TEST=Verify commands can be sent to the EC UART through usb when suzy q is connected. Verify servo can interact with the EC UART when suzy q is not connected. Change-Id: I2ce0e9da464b24e295e732aa638bfc32323cc72d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338858 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* amenia: update charge LED controlKevin K Wong2016-04-153-50/+44
| | | | | | | | | | | | | used the same charge LED control as kunimitsu BUG=none BRANCH=none TEST=make buildall, verified LED is changing with AC present. Change-Id: I20324b21ee832d1187daac2ca57c61b8851f9de3 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331784 Reviewed-by: Shawn N <shawnn@chromium.org>
* amenia: enable BMM150 compassKevin K Wong2016-04-154-2/+45
| | | | | | | | | | | BUG=none BRANCH=none TEST=accelinfo return data from compass Change-Id: Ib64ca8a06071744294c0bc88bbb18f1445d71780 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331656 Reviewed-by: Shawn N <shawnn@chromium.org>
* amenia: initial board codeKevin K Wong2016-04-1510-0/+1594
| | | | | | | | | | | | | | used board wheatley as the initial code base for amenia BUG=none BRANCH=none TEST=make buildall Change-Id: Ifa561dae01e486058b2a3115bf37075a164369c2 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331652 Commit-Ready: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Cr50: Update the USB VID:PID:subclass constantsBill Richardson2016-04-156-27/+28
| | | | | | | | | | | | | | | | | | | | | | | The device-specific subclass used for Non-HC firmware updates is in the spreadsheet now, so we can rename the macros to be "official". BUG=chrome-os-partner:49962 BRANCH=none TEST=make buildall; test on cr50 make BOARD=cr50 (plus whatever signing magic works for you) make -C extra/usb_updater ./extra/usb_updater/usb_updater build/cr50/ec.bin (sudo if needed) Note that you may need to rebuild ec.bin in order to see any difference after the update. If the A & B images are identical, the RO bootloader always picks A. Change-Id: I385ce89a9abe2059d52da2d82a0b92b9b3e3c93f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339220 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ectool: Remove CROS_EC_DEV_IOCRDMEMGwendal Grignou2016-04-154-70/+39
| | | | | | | | | | | | | | | | | On !LPC EC, we can read memory via CROS_EC_DEV_IOCXCMD ioctl, using command EC_CMD_READ_MEMMAP. On platform that supports direct memory access (lpc), we access the memory directly, bypassing the ioctl. BUG=chromium:602832 TEST=On gnawty and veyron, check 'ectool battery' works. Verify that gnawty use io mapped registers. BRANCH=none Change-Id: I9bfcddcf450bf8df63ead78e1df97dd7392289e6 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338853 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* apollolake: Remove timing delay for SOC_PWROK and RSMRST_NKevin K Wong2016-04-151-10/+3
| | | | | | | | | | | | | | | | | | | | | PMIC already has a built-in 100ms delay for V1P05S when ALL_SYS_PWRGD asserts, hence EC can assert SOC_PWROK immediately. On shutdown RSMRST_N should assert and SOC_PWR_OK should de-assert immediately when PMIC asserts PMIC_RSMRST_N and de-assert All_SYS_PWRGD respectively. Hence removed the unnecessary timing delay for SOC_PWROK and RSMRST_N. BUG=none BRANCH=none TEST=Issued a shutdown command and manually tested on amenia. RSMRST_N asserts immediately when PMIC asserts PMIC_RSMRST_N SOC_PWR_OK de-asserts immediately when PMIC de-asserts All_SYS_PWRGD. Change-Id: I8bb79277a3dcf8545764ba58736f422ac377776e Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/339001 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip: it83xx: Add i2c channel d/e/f functionEli Hsu2016-04-147-100/+668
| | | | | | | | | | | | | | | | | | | | | | | [board] 1. Add i2c channel d/e/f setting. 2. Add i2c channel d/e/f pin definition. [chip] 3. change i2c port number. 4. Add i2c channel d/e/f function. 5. Add i2c channel d/e/f interrupt. 6. Add i2c channel d/e/f registers. Signed-off-by: Eli Hsu <eli.hsu@ite.com.tw> BRANCH=none BUG=none TEST=Test by console command "i2cscan","i2cxfer" and "battery" Change-Id: I928f333ec129924795c3b594ad6a2bfdd0b3d220 Reviewed-on: https://chromium-review.googlesource.com/336560 Commit-Ready: Eli Hsu <eli.hsu@ite.com.tw> Tested-by: Eli Hsu <eli.hsu@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: fix AP UARTMary Ruthven2016-04-141-2/+2
| | | | | | | | | | | | | Change the AP UART TX and RX gpios to match the schematic. BUG=chrome-os-partner:50702 BRANCH=none TEST=verify AP console output can be seen by cr50 Change-Id: I572bf2f664c276f094116e8a72400c9332bc10a7 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338895 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: handle big-endian RSA keysnagendra modadugu2016-04-141-109/+147
| | | | | | | | | | | | | | | | | | | | | | The TPM library serializes RSA keys in big-endian format, while CR50 requires little-endian. Handle endianness by converting from big to little and back to big within the _cpri__* layer. Also modify test code to make copies of static const RSA keys, as these get placed on read-only memory. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:52337 TEST=tests in test/tpm/tpmtest.py pass Change-Id: Id9cfbe8c99ecaeb02744fbc7554cd48a08bab819 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/331740 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* make: allow to see boards failed when making 'buildall'Vadim Bendebury2016-04-142-1/+8
| | | | | | | | | | | | | | | | | | | | | | It is quite annoying to see an error reported by buildall, but not knowing what board(s) actually failed to build. Create file for each board being built, put build progress information in it, and remove it if the board build succeeded. Then, once the build is completed see the failed boards in .failedboards/, if any, and the states they failed at. BRANCH=none BUG=none TEST=verified that the directory is empty after a successful buildall run, and has files named after failed boards in case of build failures. Change-Id: I67eb1671cadf58d9f8feccebfcc860524f33c2a0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338883 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* power/rk3399: Implement chipset reset / shutdown routinesShawn Nematbakhsh2016-04-141-8/+15
| | | | | | | | | | | | | | | | | Implement warm reset and force shutdown routines, which are called from other modules. BUG=chrome-os-partner:51926, chrome-os-partner:51923 BRANCH=None TEST=Verify 'apshutdown' on EC console goes to G3. Verify 'apreset' causes AP reset while staying in S0. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ifb479287f87f31ac49e007c337cc0c24a79898e6 Reviewed-on: https://chromium-review.googlesource.com/338923 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* CR50: add support for HKDF (RFC 5869)nagendra modadugu2016-04-149-0/+298
| | | | | | | | | | | | | | | | | Add support for SHA256 based HKDF key derivation as specified in RFC 5869. This change includes test vectors from the RFC. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I7d0e4e92775b74c41643f45587fc08f56d8916aa Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/336091 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* kevin: Remove KBLIGHT moduleShawn Nematbakhsh2016-04-142-3/+2
| | | | | | | | | | | | | | | | Rename KBLIGHT to BKLIGHT (and remove the unneeded CONFIG) to reflect the actual PWM function. BUG=None BRANCH=None TEST=`make buildall -j` and verify kevin boots to kernel Change-Id: Idf6d21f096e491a62862362862e1e8a481db8987 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338512 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* CR50: handle big-endian ECC parametersnagendra modadugu2016-04-141-34/+98
| | | | | | | | | | | | | | | | | | | | | | | | The TPM library serializes ECC parameters in big-endian format, while CR50 requires little-endian. Handle endianness by converting from big to little and back to big within the _cpri__* layer. Also modify test code to make copies of static const ECC keys, as these get placed on read-only memory. Rename a couple of instances of ec_ with ecc_ to avoid confusion. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:52337 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I607984f004820d5caa85ce13575b8ab501336479 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/331673 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Kunimitsu: remove console commands for code sizeKyoung Kim2016-04-145-4/+10
| | | | | | | | | | | | | | | | | | | | | Remove following EC console commands to reduce code size: - battfake - apthrottle And none of commands above are used in 'auto test'. This is a squash of - https://chromium-review.googlesource.com/337657 - https://chromium-review.googlesource.com/338018 BUG=none BRANCH=firmware-glados-7820.B TEST=make -j buildall Change-Id: I11d2c5514f2714f0a46416feec2b2c47666fb462 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/338893 Reviewed-by: Shawn N <shawnn@chromium.org>
* power: mediatek: correct a typo in set_pmic_pwronKoro Chen2016-04-141-1/+1
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:52343 TEST=power up and should not see "5V power not ready" Change-Id: Ie8e3fd1610ff14356632205d9d81d31a838f9162 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/338886 Reviewed-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Rong Chang <rongchang@chromium.org>
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