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* npcx: i2c: Don't do i2c_unwedge / reset on repeated start requeststabilize-8516.BMulin Chao2016-06-271-2/+5
| | | | | | | | | | | | | | | | | | Checking for bus busy (stop condition sent) should not apply if the caller is requesting a repeated start. BUG=None TEST=Manual on gru. Attach USB PD charger, verify i2c_unwedge is not called. BRANCH=None Change-Id: Idf13bdc530920c8da02c8d0d8064377513a5d144 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356490 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* BD99955: Added support for 'psys' & 'amonbmon' console commandsVijay Hiremath2016-06-2712-18/+216
| | | | | | | | | | | | | | | | | | | | Added console commands for the debugging purpose psys - Can be used to measure the system power amonbmon - Can be used to measure AMON/BMON voltage diff, current BUG=chrome-os-partner:54273 BRANCH=none TEST=Manually tested on Amenia psys - Ran fish task and observed psys value changes. amonbmon - AMON & BMON voltage & current are same as measured across sense resistors. Change-Id: I6653e814d9b00efe7dae9ce1fbd7ddbc2356f8e0 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/353043 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Support DP alt mode of Type-C controllerli feng2016-06-274-10/+38
| | | | | | | | | | | | | | BUG=chrome-os-partner:54413,chrome-os-partner:54649 BRANCH=none TEST=none Change-Id: I32c969a97f84bf4e9953031c69008f8e598b7920 Signed-off-by: li feng <li1.feng@intel.com> Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/355604 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: enable highsec jittery clockMary Ruthven2016-06-272-3/+2
| | | | | | | | | | | | | | | | | The highsec jittery clock was breaking the USB peripheral, because it would use bank values that mapped to frequencies less than 15MHz. This change modifies stepx16 to keep the bankvalues mapped to frequencies above 18MHz to ensure the USB peripheral can work with the high security jittery clock. BUG=chrome-os-partner:53952 BRANCH=none TEST=sudo flashrom -p raiden_debug_spi:target=AP -r test_img.bin Change-Id: If8b45583f2cd9272b6d1e79a06556724c25d6495 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356192 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Set the default idle action to SleepBill Richardson2016-06-251-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Cr50 doesn't have anything else to do and it's been a while since anyone has communicated with it (10 seconds via UART, 1 second via SPI, and the USB bus has stopped sending SOF packets), it enters one of three idle states: wfi = fully powered, just waiting for an interrupt. sleep = low power mode, but RAM is preserved. It resumes quickly. deep sleep = hibernate. RAM is lost, resume is a warm boot You can get/set the idle state with the "idle" console command. BUG=chrome-os-partner:49955,chrome-os-partner:54331 BRANCH=none TEST=make buildall To test it: * I've only tested on the debug board, because I need a serial console (not serial-over-USB) to see if it's asleep or not. * I haven't been able to knowingly force USB Suspend on my workstation, so to fake it I just unplug the USB cables. * Wait 10-12 seconds after typing anything on the serial console, then press a key. If the Cr50 was asleep, the first character will be lost. If it wasn't, you'll see the character echoed immediately. Change-Id: Icc213e50b0c38f8c2b16bcd9960e2e5550b43180 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356123 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Elm: Update battery parameters for SanyoRyan Zhang2016-06-251-5/+5
| | | | | | | | | | | | | BUG=chrome-os-partner:54617 BRANCH=master TEST=`make -j BOARD=elm` Change-Id: Id4bf6180b7776363f470f29d1b7d3d4d8095c659 Reviewed-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/353514 Commit-Ready: Ryan Zhang <Ryan.Zhang@quantatw.com> Tested-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Control power state properly on power button / lid toggleShawn Nematbakhsh2016-06-241-10/+45
| | | | | | | | | | | | | | | | | | | | | | | | - Power up the AP automatically on initial EC power-on. - In S0, wait for 8s power button hold before powering down. - In S3 and lower, power down immediately on power press. - In G3 / S5, power up on lid open. BUG=chrome-os-partner:54582,chrome-os-partner:54511 BRANCH=None TEST=Manual on gru. Verify the following: - AP powers up when battery initially attached. - `reboot` powers up AP after EC reset. - `reboot ap-off` doesn't power up AP. - `apshutdown` + `lidclose` + `lidopen` causes AP power-up. - Holding power for 4s in S0 does not change power state. - Holding power for 8s in S0 causes AP power down. Change-Id: I588056549a972212c28b9aa6a83fe2e0b179baa9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355650 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: write 0 to RBOX_WAKEUP_CLEAR to clear registersMary Ruthven2016-06-241-0/+1
| | | | | | | | | | | | | | | We need to write 0 to RBOX_WAKEUP_CLEAR after writing 1 to clear the rbox wakeup registers. BUG=none BRANCH=none TEST=after init verify 'rw .h 0x40550098' returns 0 Change-Id: Id7eda45f443300e77f293556eece72d52ca28f17 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355283 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Hsiao-heng Lee <kelinlee@google.com>
* kevin / gru: Enable host-controlled USB-C SS muxShawn Nematbakhsh2016-06-243-16/+26
| | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:52639 BRANCH=None TEST=Manual on gru with subsequent commit. Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool usbpdmuxinfo` output: Port 0: DP Port 1: USB Flip DP dongle and verify output changes: Port 0: DP INV Change-Id: I5459cb587badd46c03d1c433f13fdf21a5dc63ed Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355282 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_mux: Add support for host-controlled 'virtual' USB muxShawn Nematbakhsh2016-06-248-4/+147
| | | | | | | | | | | | | | | | | | | | | | | | For designs where the host SOC is responsible for setting the USB-C SS mux, the EC must track the desired mux state and inform the host when the desired state changes. Then, the host must ask the EC for the new desired state and set the mux accordingly. BUG=chrome-os-partner:52639 BRANCH=None TEST=Manual on gru with subsequent commit. Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool usbpdmuxinfo` output: Port 0: DP Port 1: USB Flip DP dongle and verify output changes: Port 0: DP INV Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6a99ce93a76c3197f9195cfaa25c5217d09aeb75 Reviewed-on: https://chromium-review.googlesource.com/355281 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin / gru: Remove console features to save RAM spaceShawn Nematbakhsh2016-06-241-4/+5
| | | | | | | | | | | | | BUG=chrome-os-partner:52876 BRANCH=None TEST=`make buildall -j` Change-Id: I10bebf4c6af4e23f4e07bbb609626424434c721a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355280 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* sb_firmware: update lockfile pathDavid Hendricks2016-06-241-1/+1
| | | | | | | | | | | | | | | This updates the lockfile path for FHS 3.0 since powerd as well as other pieces of software are migrating over. BUG=chromium:616620 CQ-DEPEND=CL:351271 BRANCH=none TEST=compiled Change-Id: I6aa5fa30225e45039316e4a3af0e50cdef0fdf4e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/351345 Reviewed-by: Dan Erat <derat@chromium.org>
* Cr50: Added TPM register write/read to extract FW versionScott2016-06-241-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Created a new TPM register define at the beginning of the vendor defined configuration register space 0xF90 - 0xFFF. Note that this same space is defined for each locality. In order to retrieve the FW version string, the TPM register at offset 0xF90 needs to be written. This will initialize a the pointer index to 0. The same register is then read by the AP and each read will return up to 4 bytes of the FW version string. Once Cr50 detects the string termination character, it stops incrementing the index so that 0s continue to be returned for each subsequent read. In addition there is a max value of reads for the case when the version string is corrupt and doesn't have a '\0' character. BRANCH=none BUG=chrome-os-partner:54723 TEST=Manual Added a routine in /coreboot/src/drivers/spi/tpm.c tpm_init() that does the write/read sequence described above. This test routine produced the folloiwng AP console output: Reading TPM EC Version!! scollyer@ code goes here Read 1: cr50 0x30 Read 2: _v1. 0x2e Read 3: 1.47 0x37 Read 4: 81-1 0x31 Read 5: 3619 0x39 Read 6: 95-d 0x64 Read 7: irty 0x79 Read 7: 0x0 Cr50 FW Version: cr50_v1.1.4781-1361995-dirty Read Count = 29 Initialized TPM device CR50 revision 0 Change-Id: I5d68a037f7a508e3109c35e841dbcb3a893ce22f Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355701 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* tpm: use proper locality zero SPI bus addressesVadim Bendebury2016-06-231-10/+11
| | | | | | | | | | | | | | | | | The "PC Client Protection Profile for TPM 2.0" document defines SPI bus addresses for different localities. That definition is not honored in the cr50 implementation, this patch fixes it: locality zero register file is based off 0xd40000. BRANCH=none BUG=chrome-os-partner:54720 TEST=verified that upstream Linux driver is happy now Change-Id: Ibc01035a5dcc823a0ec82374d758de08a70083b6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355610 Tested-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* ec_commands: Be sure all C code is within #ifnef ACPIGwendal Grignou2016-06-231-2/+2
| | | | | | | | | | | | | | When __ACPI__ is set, only #define are allowed. BRANCH=none BUG=chrome-os-partner:52433 TEST=Coreboot compiles with this code. Change-Id: Iadb3893960f16ff49aa4f4e5871d5d17cbb87642 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355570 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* reef: force PMIC reset on initial bootKevin K Wong2016-06-231-0/+17
| | | | | | | | | | | | | | | | | | | | On EC reset where PMIC_EN will be pulled low, PMIC could get into an unknown state and will not sequence properly on sub-sequent boot. This is a temporary workaround for Reef Proto, a hardware change will be implemented on EVT. BUG=chrome-os-partner:53974,chrome-os-partner:54507 BRANCH=none TEST=Reef powers to S0 and starts coreboot after EC reset Tested with servo cold reset button and console reboot command Change-Id: I32aa004b000895da2c97d1014a8ef48c0a98779d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/354762 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Enable external power interrupt GPIOVijay Hiremath2016-06-233-8/+6
| | | | | | | | | | | | | | | | | BUG=chrome-os-partner:54503 BRANCH=none TEST=Manually tested using console commands on both the ports. a. Issued 'gpioget AC_PRESENT', observed AC_PRESENT is 1 when AC connected & 0 when AC disconnected. b. Issued 'hibernate' & on plugging in the AC, device boots to S0. Change-Id: Iad09914d79cdbd798fb650146321eafed06eb91c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/354721 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: NvMem: Added mutex lock protection for cache memoryScott2016-06-223-52/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added mutex lock for nvmem write/move operations. In the current implementation, there is no single entry point for the platform specific NvMem calls. The mutex lock is coupled with a task number so that the same task can attempt to grab the lock without stalling itself. In addition to the mutex lock, changed where the cache.base_ptr variable is updated. Previously, this was done prior to the partition being copied from flash to the shared memory area. Now, the variable is only updated after the copy so that read operations will always read from the correctly from either flash or from cache memory if a write operation has been started. BRANCH=none BUG=chrome-os-partner:52520 TEST=Manual make runtests TEST_LIST_HOST=nvmem and verify that all tests pass. Tested with tcg_test utility to test reads/writes using the command "build/test-tpm2/install/bin/compliance --ntpm localhost:9883 --select CPCTPM_TC2_3_33_07_01". Change-Id: Ib6f278ad889424f4df85e4a328da1f45c8d00730 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353026 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mkpb: Add MKBP support over ACPIGwendal Grignou2016-06-224-7/+21
| | | | | | | | | | | | | | | | | | | | Add a host event to support MKPB: When sent, the ACPI code will send a notification to the kernel cros-ec-lpcs driver that will issue EC_CMD_GET_NEXT_EVENT. We can allow code (sensor stack for instance) that uses MKBP to work on ACPI based architecture. Obviously, host event over MKPB is not supported. BRANCH=none BUG=b:27849483 TEST=Check we get sensor events on Cyan through the sensor ring. (cyan branch) Change-Id: Iadc9c852b410cf69ef15bcbbb1b086c36687c687 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353634 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rk3399: kevin: Adding get_rtc_alarm functionality.Shelley Chen2016-06-212-6/+67
| | | | | | | | | | | | | | | | | | | | | | Adding ability to get # seconds before rtc alarm goes off. BUG=chrome-os-partner:52218 BRANCH=None TEST=ectool rtcgetalarm w/o setting returns Alarm not set. ectool rtcsetalarm 30; ectool rtcgetalarm to make sure counting down to 0. After alarm goes off, rtcgetalarm should return alarm not set again. rtcsetalarm 30; rtcgetalarm to check alarm is set. rtcsetalarm 0; should disable alarm. Use rtcgetalarm to ensure that alarm is disabled. Change-Id: I176b12fe2dda08eedd23ea33dc64785f09f1d9ae Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353331 Reviewed-by: Shawn N <shawnn@chromium.org>
* build: Skip cr50 board in `make buildall` if private folder not presentShawn Nematbakhsh2016-06-211-0/+4
| | | | | | | | | | | | | | BUG=chromium:621993 BRANCH=None TEST=`make buildall -j` from public checkout succeeds. Also verify cr50 still built from private checkout. Change-Id: I982806e282146aab76154b51c366226d3d1aed14 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/354540 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Elm: update LED controlstabilize-8481.BRyan Zhang2016-06-201-9/+39
| | | | | | | | | | | | | following Change#227416 to meet client's spec. BUG=chrome-os-partner:54263 BRANCH=master TEST=`make -j BOARD=elm`, check factory force IDLE, works good Change-Id: I1f0abdcbd56eeab379a6258869ccc133ff80736d Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/353521 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: vbnvcontext: Fix misaligned accessShawn Nematbakhsh2016-06-201-11/+18
| | | | | | | | | | | | | | | | | | | | We have no guarantee about the alignment of our input buffer so don't use 32-bit access. BUG=chrome-os-partner:54561 BRANCH=None TEST=Manual on gru. Enable CHROMEOS_VBNV_EC, verify exception isn't encountered on host command 0x17. Also verify call to system_set_vbnvcontext followed by system_get_vbnvcontext results in same data being read back. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I4df636b70c71a43a2dd6f584ee965135e90b4351 Reviewed-on: https://chromium-review.googlesource.com/354132 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kevin: add CHARGER_NARROW_VDC to prevent DC-DC stoppingWonjoon Lee2016-06-191-0/+1
| | | | | | | | | | | | | | | | BD99955 DCDC wiil turn off Vsys voltage under VSYSVAL_THL_SET or VREF_BAT<VBAT if Charging Voltage set under actual battery voltage or VSYSVAL_THL_SET. BUG=chrome-os-partner:53777 BRANCH=none TEST=boot-up without battery. using zinger or oem supplier used kevin rev2, rev3 Change-Id: I03c5c52790b2d481be3fa942054516fbefa3ce98 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/348563 Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: Add pull down on UART TX signalsMary Ruthven2016-06-191-5/+9
| | | | | | | | | | | | | | | | | We need to have an internal pull down so the UART TX signals will be pulled low when servo is disconnected. BUG=chrome-os-partner:54547 BRANCH=none TEST=On gru test that servo detection works. Change-Id: I7d549766273862eb23c0645b887f3db4a0adbab1 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353764 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kevin / gru: Enabling charging at up to 20VShawn Nematbakhsh2016-06-191-3/+2
| | | | | | | | | | | | | | | BUG=chrome-os-partner:54551 BRANCH=None TEST=Manual on kevin. Verify negotiation to 20V when zinger is plugged. Also verify "pd 0 dev 12" and "pd 0 dev 5" cause 12V/5V to be requested from zinger. Change-Id: I0298d535b791fa0c6f8ca077a6fd09a27e8ce77b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353804 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec_commands: use hex to make EC_PWM_MAX_DUTY clearerBrian Norris2016-06-171-2/+2
| | | | | | | | | | | | | | | Some comments in upstream Linux review have suggested this be hex. Makes sense to me. BUG=chromium:621123 TEST=build BRANCH=none Change-Id: Ib7143acc96a2fe593d5e02ad0fba3a501bd8cea2 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353681 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* driver: si114x: Handle overflow properly.Gwendal Grignou2016-06-171-12/+16
| | | | | | | | | | | | | | Overflow happens when raw value from ADC is greater than 0x7FFF. When it happens, skip the result. BRANCH=ryu,jerry TEST=Without this code, the proximity sensor would show 22000in instead of staying close to 0 when thumb is near sensor. BUG=chrome-os-partner:53851 Change-Id: Id2182acbbf7b00157d9fee5d28bb61df4f166246 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/348300
* pd: Set PD_FLAGS_VBUS_NEVER_LOW after tcpm_initKoro Chen2016-06-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | When we jump from RO to RW, tcpc_vbus declared in tcpci.c is initialized to 0. So even if we had VBUS present before, PD_FLAGS_VBUS_NEVER_LOW is not set and soft reset cannot be used later when source cap is timeout. This causes power loss and reboot when we boot up system without battery. Set PD_FLAGS_VBUS_NEVER_LOW after tcpm_init() so we can refresh tcpc_vbus from TCPC first. BUG=chrome-os-partner:53496 BRANCH=none TEST=test on elm. Remove battery and boot up successfully only with AC. Use "sysjump rw" command and ec won't reboot by pd hard reset. Change-Id: Id4737f076a9572cb540310f9fdce062198257967 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/352833 Reviewed-by: Rong Chang <rongchang@chromium.org>
* Revert "elm: get VBUS statue from GPIO"Koro Chen2016-06-173-7/+2
| | | | | | | | | | This reverts commit abe2a55191dbcdf8c92bfea64601b607471d75be due to it triggers Issue 54108. Change-Id: I19c89511e31b056285680e3afff95f44b4d932a6 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/352832 Reviewed-by: Shawn N <shawnn@chromium.org>
* gru: Add battery status LED controlShawn Nematbakhsh2016-06-163-3/+132
| | | | | | | | | | | | | | | | | | | | | | | | Implement the standard LED control scheme for gru, using a single PWM to set the battery status LED color rather than the traditional GPIOs. BUG=chrome-os-partner:54379 BRANCH=None TEST=Manual on gru. Verify LED is green when charging w/ nearly full battery, off when discharging w/ nearly full battery, amber when charging otherwise. Also verify LED control host commands work as expected: ectool led battery green=1 // green ectool led battery amber=1 // amber ectool led battery red=1 // red ectool led battery red=0 // off Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I184e72c552e6d2196aef2724af9292806e0ea8c0 Reviewed-on: https://chromium-review.googlesource.com/352520 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* usb_updater: allow to define target environmentVadim Bendebury2016-06-161-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | It is necessary to be able to build usb_updater for both host and board environments. When building for board environments the appropriate compiler and binutils are defined in the environment. Allow the environment definitions to take precedence over local definitions. BUG=none TEST=inside and outside chroot: . ran 'make clean; make; verified that command can be run on the host. inside chroot: . ran 'emerge-kevin ec-utils' and verified using the 'file' utility that the executable in /build/kevin/usr/sbin/usb_updater is built for arm Change-Id: If2ac4a4e7f7ece188eba5ff917a510363c6d1990 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353165 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: remove the fuse override in rboxMary Ruthven2016-06-162-15/+1
| | | | | | | | | | | | | | | | FUSE_CTRL_OVERRIDE overrides all rbox fuse values with the values in RBOX_DEBUG not just the ones that are explicitly set. This change removes the override from rbox. BUG=chrome-os-partner:54238 BRANCH=none TEST=on gru and kevin check that pressing 'c' registers on the EC. Change-Id: I655e9ca96e52359a7d36e0d691f838c335df8cb8 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353033 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
* Enable 1 slot of secure temporary storage in reef.Ravi Chandra Sadineni2016-06-161-2/+2
| | | | | | | | | | | | | | BUG=chrome-os-partner:53877 BRANCH=None TEST=Boots successfully without any error in retrieving hash code. Change-Id: Ia6ff6b702c8ac15ce8ab546595c36ce148bf6480 Signed-off-by: ravi chandra sadineni <ravisadineni@google.com> Reviewed-on: https://chromium-review.googlesource.com/352826 Commit-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org> Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ravi Chandra Sadineni <ravisadineni@chromium.org>
* bd99955: Improve interrupt / USB charger task wake schemeShawn Nematbakhsh2016-06-163-83/+56
| | | | | | | | | | | | | | | | | | | | | | | | | Previously our charger ISR called a deferred task which woke our charger task. We can skip the deferred task and just wake our charger task directly. The other meaningful change here is to assume that we're using the charger for VBUS detection / BC1.2 if we have a usb_chg task, which holds true for all of our current boards with this charger. BUG=None TEST=Manual on kevin with subsequent commit. Verify charger connect / disconnect detection works properly on both ports, with zinger, donette and generic DCP charger. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iad4f3ea90947b50859c549b591675e325717209f Reviewed-on: https://chromium-review.googlesource.com/352822 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* elm: anx7688: make anx7688 always onKoro Chen2016-06-161-17/+10
| | | | | | | | | | | | | | | | | This makes the boot time less painful since it requires a long delay for FW loading after power on this chip. This also makes it easier to upgrade FW as we don't need to power on the chip before doing upgrade. BRANCH=none BUG=chrome-os-partner:52815 TEST=plug and unplug dongle and check DP output plug/unplug adapter and check pd 0 state Change-Id: Ia344c748697a3b1d06c9b442e1bf1d7227861f9b Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com> Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/347181 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* elm: anx7688: add anx7688 hpd driverRong Chang2016-06-1610-48/+324
| | | | | | | | | | | | | | | | | | | | ANX7688 is a TCPCI compatible port controller with HDMI to DP converter. The HDMI converter needs a reset every time after enabling its function. BRANCH=none BUG=chrome-os-partner:52815 TEST=manual boot elm proto plug and unplug dingdong and check DP output plug/unplug adapter and check pd 0 state Change-Id: I774421d7b0b8d2cfd31e860fcd4eaed08ee48ac7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com> Reviewed-on: https://chromium-review.googlesource.com/340371 Commit-Ready: Koro Chen <koro.chen@mediatek.com> Tested-by: Koro Chen <koro.chen@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kevin / gru: Enable charger interrupt and connect USB data switchesShawn Nematbakhsh2016-06-152-2/+15
| | | | | | | | | | | | | | | | | | | | Enable charger interrupt for VBUS / BC1.2 detection on kevin / gru. Also, keep our USB data switches connected while we figure out how to implement USB mux control. BUG=None TEST=Manual on kevin with subsequent commit. Verify charger connect / disconnect detection works properly on both ports, with zinger, donette and generic DCP charger. BRANCH=None Change-Id: I602e7bd3180110d351ec4c2916a6b8612c7e5f82 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/352821 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shelley Chen <shchen@chromium.org>
* USB Serial: Add README and update CCD docsAnton Staaf2016-06-152-12/+23
| | | | | | | | | | | | | | | | | | | | The README points the reader back to the docs directory where the CCD documentation lives. I've added information about the install script, and about how the raiden module identifies a CCD serial console. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I8714dffcad0b8c30f46529a8f2d670b5d432cda6 Reviewed-on: https://chromium-review.googlesource.com/352787 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: refactor debug_printf() for use as a library functionnagendra modadugu2016-06-153-18/+29
| | | | | | | | | | | | | | | | | | | | | loader/key_ladder.c depends on debug_printf(). Refactor the printf function so that key_ladder.c need not depend on main.c. This change being made in preparation for a future change which introduces a dependency between RW and key_ladder.o BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=build succeeds Change-Id: I5c9bf7bd6dd9f76ab6410e6e797973bdb072ec16 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/351760 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: give ecc and rsa keys distinct derivation templatesnagendra modadugu2016-06-152-4/+35
| | | | | | | | | | | | | | | | | | | This change implements distinct key derivation trees for ECC and RSA key generation. The seed used for derivation is HMAC(primary_seed, ALG), where ALG is either "ECC", or "RSA". BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=all tests in test/tpm_test/tpmtest.py pass Change-Id: Iee85731bdac02b7b1061e9220786bee52dbf6289 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/351750 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* USB Serial: Add fallback rule and scriptAnton Staaf2016-06-153-7/+114
| | | | | | | | | | | | | | | | | | | | | | This rule makes it easier to use CCD devices when the raiden module can't be installed for some reason. The rule informs the usbserial module that it should handle anything that looks like a simple serial port for any CCD compatible USB devices. The install script now detects failure when building and installing the raiden module and offers the --fallback option in that case. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I617bbdfb4c5cb9e9803f4088c651f84e3f72bd28 Reviewed-on: https://chromium-review.googlesource.com/351873 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: tcpci: Don't wait forever for init() on i2c errorShawn Nematbakhsh2016-06-152-5/+15
| | | | | | | | | | | | | | | | | | If i2c communication with the TCPC is failing after 300ms+ then it's likely going to fail forever, so return an error to allow the PD task to continue initialization. BUG=chrome-os-partner:53815 BRANCH=None TEST=Manual on reef. Disconnect TCPC, attach charger to other port, and verify charge manager correctly sets current limit based on detection. Change-Id: I2c12320971a77504292f75393791e609e34897b4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/352501 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: Support different PLL frequencies setting (24/48/96 MHz)Dino Li2016-06-148-36/+161
| | | | | | | | | | | | | | | | | | | | | | | Default setting is at 48MHz. For PLL frequency at 24MHz: 1. USB module can't work, it requires 48MHz to work. 2. SSPI clock frequency is divide by two. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. uart, i2c, timer, and pd modules are function normally at different PLL frequency settings. 2. use 'flashrom' utility to flash EC binary with different PLL settings. Change-Id: Iabce4726baff493a6136136af18732b58df45d7f Reviewed-on: https://chromium-review.googlesource.com/347551 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Fixed host access pending bit issue in INT11 ISR.Mulin Chao2016-06-141-10/+10
| | | | | | | | | | | | | | | | | | | | Since the pending bit of host access interrupt is set frequently if PCH accesses KBC/PM_Channel/Shared Memory through LPC after entering S0. It's better to add checking enable bit of MIWU of it in case huge latency between gpio interrupt and serving its own ISR in INT11's ISR. Modified sources: 1. gpio.c: Add checking enable bit of MIWU of host access in INT11 ISR. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: I1ae57173eb208fa78218bc01cfbc91f9a29c5c81 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/352362 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* amenia: Support DP alt mode of Type-C controller in amenia.li feng2016-06-144-2/+39
| | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=On Amenia TR1.2, tested with HDMI to Type-C dongle. Both Analogix and Parade ports have HDMI on extended display. Change-Id: Ifb95c289019063a8a24d135e3b3a09cb4d446210 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/348881 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* driver/tcpm: add Type-C controller ps8751 DP alt mode APIli feng2016-06-144-0/+82
| | | | | | | | | | | | | | | BUG=chrome-os-partner:49431 BRANCH=none TEST=On Amenia TR1.2, verified display port outptu is enabled on exteneded display. Seperate patches are needed for testing. Change-Id: I5ca54c91c566725c612a01a51f1af32e2a819e2d Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/351319 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* gru/kevin: Turn PP1800_PMU on earlier in sequenceDavid Schneider2016-06-141-2/+2
| | | | | | | | | | | | | | | PP1800_PMU impacts the initial centerlogic voltage due to DVS circuitry. Since there's no other sequencing dependency, turn it on earlier. This fixes centerlogic from initially starting too high (1.5V). BUG=none BRANCH=none TEST=Watch PPVAR_CENTERLOGIC and confirm that it starts at the target voltage Change-Id: Icac076a7e8aef978401452a98d9f6bc8b373d94f Signed-off-by: David Schneider <dnschneid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/352247 Reviewed-by: Shawn N <shawnn@chromium.org>
* BD99955: Use only one USB charger task for both the portsVijay Hiremath2016-06-146-35/+62
| | | | | | | | | | | | | | | | | | | | | There is only one charger IC and one interrupt PIN for both the ports and also from the ISR it's not possible to decode from which port the interrupt is triggered hence a deferred function is used to trigger the wake event for the ports. As there is no additional benefit of having an extra task, added code to use only one USB charger task for both the ports. BUG=chrome-os-partner:54272 BRANCH=none TEST=Manually tested on Amenia. BC1.2 detection is success and the battery can charge on both the ports (VBUS/VCC). Change-Id: I2745a5a179662aaeef8d48c8c1763919e8853fd0 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/351752 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* gru: Enable charging of USB-A devices in S3Shawn Nematbakhsh2016-06-142-15/+18
| | | | | | | | | | | | | | | | | Leave USB-A charging enabled in S3, and move gru-specific code into board hooks, out of the power state driver. BUG=chrome-os-partner:54159 BRANCH=None TEST=Manual on gru. Verify USB-A enable GPIOs are asserted in S0 and deasserted in G3. Change-Id: Icadeb771226dd0fda4ae96fdde9b3984d87fdd15 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/351670 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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