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* npcx: deprecate use of PC87570 mode on PM chan 1stabilize-8530.Bstabilize-8530.96.Bstabilize-8530.93.Bstabilize-8530.89.Bstabilize-8530.80.Bstabilize-8530.77.Bstabilize-8530.71.Bstabilize-8530.35.Brelease-R53-8530.BCHLin2016-06-301-5/+9
| | | | | | | | | | | | | | | | | | | In NPCX5m5g/NPCX5m6g, PM channel 1 can support both PC87570-Compatible and enhcnced mode. In next generation of chip, only enhanced mode will be supported. Set the enhanced mode as default in the firmware to support all gereration of chips. BUG=chrome-os-partner:34346 TEST=make buildall -j; verify on Wheatley BRANCH=none Change-Id: Ide9e17a1fe8a0d2bfdc33efe2336a10702660679 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/357752 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* motion: Add ability to stop ring interrupts.Gwendal Grignou2016-06-303-17/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, it is assumed the host will sooner or later retrieve the events from the sensor ring: It is only used by Android and the sensor HAL is enabling the ring buffer at boot. But if nobody processes the ring, and the ring is almost full, the EC will generate interrupt for every new events. This can happen with ARC, where events generated for ChromeOS will be in the ring but nobody will process them until Android is started. Add a command to allow sending ring MKBP events. It will be used when the IIO ring buffer is enabled / disabled. It also can be used for preventing raising interrupt when the device is about to go to sleep. BRANCH=ryu,cyan BUG=b:25425420,b:27849483 TEST=Check with fiforead that no events are queued when IIO ring buffer is disabled. Check with ectool and androsensor that interrupt generation stops. Change-Id: Ibc85eed2e0eae3a9ec07d191e692118bc2fd0dab Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356689
* kevin / gru: Wait to allow ADC 'version' cap to sufficiently chargeShawn Nematbakhsh2016-06-301-1/+1
| | | | | | | | | | | | | | | | | Allow at least 10ms for the 'version' cap to charge in order to have a voltage on the ADC pin that reflects our voltage divider circuit. BUG=chrome-os-partner:54768 BRANCH=None TEST=Manual on kevin. Run 'ver', verify that rev3 board is recognized as version 3. Change-Id: I1f3326f4c99a165d77363834d5671aa357a89007 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/357970 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* kevin: re-define for changed GPIOWonjoon Lee2016-06-303-9/+8
| | | | | | | | | | | | | | | - swap M10/J6 to avoid SHI interrupt priority contention - USB-C power enable signal to active high BUG=none BRANCH=none TEST=get proper working on kevin-rev3 Change-Id: I52b71636779cad8975cef5921e9c9a1b7da8645e Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/351151 Commit-Ready: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* keyboard_scan: Support boot key recognition with stuck KSI2Shawn Nematbakhsh2016-06-304-0/+24
| | | | | | | | | | | | | | | | | For certain board configurations, KSI2 will be stuck asserted for all scan columns if the power button is held. We must be aware of this case in order to correctly handle recovery mode key combinations. BUG=chrome-os-partner:54602 BRANCH=None TEST=Manual on gru. Do three-key salute, verify EC detects recovery mode. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I03d76e1121107484f79520745858388f6cae096c Reviewed-on: https://chromium-review.googlesource.com/357590 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tpm test: use proper locality zero SPI bus addressesnagendra modadugu2016-06-301-5/+7
| | | | | | | | | | | | | | The fix for SPI bus base address missed the tpm test driver, this patch fixes the issue. BRANCH=none BUG=chrome-os-partner:54720 TEST=tpmtest.py connects over ftdi & tests pass Change-Id: I5a59a6e089aee5a7c25466e0d183f3647c67343a Signed-off-by: nagendra modadugu <ngm@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356556
* reef: Add I2C_PORT_ACCELDavid Hendricks2016-06-291-0/+7
| | | | | | | | | | | | | | | | | | | The motion sensor drivers used to rely on #defines indicating I2C or SPI port to tell which to use. However, these days the drivers get that info passed in via the motion_sensor_t struct. Now this #define simply decides whether to compile in SPI or I2C wrapper code. We should eventually make it less confusing, but that's beyond the scope for now. BUG=none BRANCH=none TEST=reef motion sensor init works now Change-Id: Ic38c57a6c070af391d2d4e2ec1a68ac90a377688 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356822 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: hardware based mod exp may need a final reducenagendra modadugu2016-06-291-0/+5
| | | | | | | | | | | | | | | | | | The modexp implementation occasionally produces a result larger than the modulus, in which case a single final reduce is required. The software based implementation already has this check. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tpmtest.py passes Change-Id: I0a830781e2a109963394d0702cbc2ca6457c410c Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/357010 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* anx74xx: allow anx74xx_tcpm_mux_set() to disable muxDavid Hendricks2016-06-291-17/+19
| | | | | | | | | | | | | | | | | | | This handles the case where we wish to disable the mux. Without this the "else" case will return EC_ERROR_UNIMPLEMENTED when we transition to the PD_STATE_SRC_DISCONNECTED state, and the EC console shows "Error setting mux port(0)." BUG=none BRANCH=none TEST=no longer see "Error setting mux port(0)" on Reef EC console Change-Id: I97f35775a5c92636ede1b32293b3a4d01e002dc0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/354680 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: add a golden test for RSA key gen from a fixed seednagendra modadugu2016-06-292-17/+48
| | | | | | | | | | | | | | | | Add a test that verifies RSA keygen from a fixed seed and template from the TCG EK Credential Profile spec. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpmtest pass Change-Id: I2f1cfb8460a0497c93079b89b9ff4e031eaff358 Reviewed-on: https://chromium-review.googlesource.com/356561 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: shi: Use worst-case logic for applying 256B bypassShawn Nematbakhsh2016-06-291-3/+3
| | | | | | | | | | | | | | | | | | | | SHI_OBUF_VALID_OFFSET may wrap on buffer full, leaving us with an incorrect tally of bytes transmitted. Always assume the worst case, that SHI_OBUF_VALID_OFFSET is at maximum, when deciding to apply 256B bypass. BUG=chrome-os-partner:54566 BRANCH=None TEST=Manual on gru. Verify 'flashrom -p ec -r read.bin' does not produce CRC errors. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I7c0ccc1b555838854584a3be8ced50057eaea961 Reviewed-on: https://chromium-review.googlesource.com/356771 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* add support for using flash commands to overwrite rwsigMary Ruthven2016-06-291-0/+5
| | | | | | | | | | | | | | | | | | When verifying RW using rwsig, we need to be able to erase the RW signature to remain in RO. This change excludes the RW signature from the area protected by system_unsafe_to_overwrite, so flash write can be used to overwrite the RW signature while still in the RW system image. BUG=none BRANCH=lucid TEST="ectool flashwrite 0x1ff00 corrupt_sig" runs successfully, and on reboot the EC firmware verification fails. Change-Id: I7e234664ae564eef30a8b021ea0539b6c0ae898e Reviewed-on: https://chromium-review.googlesource.com/356810 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cleanup: gate RTC console/host command behind new config optionsphilipchen2016-06-295-1/+16
| | | | | | | | | | | | | | | | Put RTC code supporting console/host command behind new flags 'CONFIG_CMD_RTC'/'CONFIG_HOSTCMD_RTC' BUG=chromium:613699 TEST=make buildall BRANCH=master Change-Id: Ida52265d124978f48bd6ca522be3badee9f99588 Reviewed-on: https://chromium-review.googlesource.com/356206 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: TEMP: to be researched and removedVadim Bendebury2016-06-292-3/+8
| | | | | | | | | | BRANCH=none BUG=chrome-os-partner:54916 TEST=none Change-Id: Ie7fc68a0ad8f9459558d3af03f942b4accaeebaf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356590
* Revert "Cr50: Set the default idle action to Sleep"Vadim Bendebury2016-06-291-16/+5
| | | | | | | | | | This reverts commit 9a644c429af9f299445962892666685233cb0a1b. BUG=chrome-os-partner:54916 Change-Id: I4e92258412d79d4962049552e911fb4ab2cfc914 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/357321
* elm: Choose low input voltage whenever possibleKoro Chen2016-06-291-0/+3
| | | | | | | | | | | | | | | To achieve higher power efficiency, we want the input voltage to be as low as possible. If the PD source advertise several choices over PD_MAX_POWER_MW, choose the one with the lowest voltage. BRANCH=none BUG=chrome-os-partner:54519 TEST=Plug in Liteon charger and make sure 15V/3A is selected Change-Id: I6157eb94a1cb45cd537acc79c377db2cff09d922 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/356317 Reviewed-by: Rong Chang <rongchang@chromium.org>
* tcpm: fusb302: Avoid unwanted CC PU changesShawn Nematbakhsh2016-06-281-53/+63
| | | | | | | | | | | | | | | | | | | | If set_cc() is called, our toggle interrupt may still be active. Since alert() is called from the pdcmd task and set_cc() is called from the pd tasks, an unwanted interrupt may fire and override our desired CC settings. BUG=chrome-os-partner:54786 BRANCH=None TEST=Manual on gru. Rapidly attach + detach DP dongle, verify we don't get stuck in SNK_DISCONNECTED_DEBOUNCE. Change-Id: Ib60123c45d9a3a78243a3347377fb2190cbdf94b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356513 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec_commands: Add suspend control needed for SkylakeGwendal Grignou2016-06-281-0/+17
| | | | | | | | | | | | | Changes were submitted for ec_commands.h but only in the braswell tree. Merge in ToT for future reference. BRANCH=none BUG=chrome-os-partner:50627 TEST=compile. Change-Id: I74f6ce3c5fd2a628879593a65506d10c44ee574d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356551
* npcx: shi: Avoid 'unexpected state' console spamShawn Nematbakhsh2016-06-281-5/+21
| | | | | | | | | | | | | | | | | | | If SHI finds itself in an unexpected state, we may try to print an error message for each IBF / IBHF interrupt, which is excessively spammy and may even lead to EC watchdog. Avoid console spam by not duplicating IBF / IBHF / IBEOR error prints, if our state doesn't change. BUG=chrome-os-partner:54502 BRANCH=None TEST=Manual on gru. Verify only one print is seen when SHI fails due to missed initialization. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I331c64c24fa3a68d7c17e052240691076d3532cc Reviewed-on: https://chromium-review.googlesource.com/356239 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add RO image hash base to the reported FW versionVadim Bendebury2016-06-281-6/+21
| | | | | | | | | | | | | | | | | | | | The CR50 RO version is identified not just by the git hash, but also by the fuse settings and keys used for signing. The first four bytes of the entire RO image's hash are saved in the image header. Adding these four bytes to the version string reported to the host allows to uniquely identify both RO and RW firmware versions. BRANCH=none BUG=none TEST=verified that the appropriate string is showing up: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO: 97594095 RW: cr50_v1.1.4803-dcac93a-dirty localhost ~ # Change-Id: I30a21fad15d99523b1edfa1baa32d80b44e7d0df Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356735 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* pd: tcpci: Properly get / set mux polarityShawn Nematbakhsh2016-06-282-7/+11
| | | | | | | | | | | | | | | | | | | CONFIG_STANDARD_OUTPUT bit 0 on the TCPC is used to indicate connector orientation flipped status. BUG=chrome-os-partner:53502 BRANCH=None TEST=Manual on amenia / reef. Verify USB3 drive is properly detected as SuperSpeed for either polarity. Change-Id: I707e46064cbf0f89b3098c850b1cee55c9fead58 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355670 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: shi: Ensure SHI is initialized prior to enabling CS interruptShawn Nematbakhsh2016-06-281-8/+14
| | | | | | | | | | | | | | | | | | | shi_init() must be called before shi_enable(). BUG=chrome-os-partner:54810 BRANCH=None TEST=Manual on gru. Power-up EC, verify no SHI error prints are encountered. Boot to OS, run "sysjump rw", verify that host commands continue to be handled correctly. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ff0db87115f5b1f358d7d98e7b7050ee3e3fe0a Reviewed-on: https://chromium-review.googlesource.com/356178 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lucid:enable RW firmware verificationMary Ruthven2016-06-282-0/+30
| | | | | | | | | | | | | | | | Check RSA signature of RW firmware and jump to it if it is valid. BUG=chrome-os-partner:54824 BRANCH=lucid TEST=flash lucid with good and bad firmware. Verify it wont jump to the bad firmware. Change-Id: I97d7df81500e158963bdc835c22445471818b85e Reviewed-on: https://chromium-review.googlesource.com/356560 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* bd99955: Enforce minimum input current of 512 mAShawn Nematbakhsh2016-06-282-1/+5
| | | | | | | | | | | | | | | | | Lower input current limits can cause back-boosting in some cases. BUG=chrome-os-partner:54778 BRANCH=None TEST=Manual on reef. Plug multiple chargers, verify ilim doesn't drop below 512 mA and back-boosting does not occur. Change-Id: Ia019fe52d75a9a37177605ceda473d338fd87fc3 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356161 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* BD99955: Change the minimum charging current valueVijay Hiremath2016-06-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | If the battery is not yet ready to provide the power or battery is not present and the charging current is set to 64mA then the charger voltage regulation is transient. ROHM recommended 512mA of minimum charging current for this issue, hence changed the minimum charging current from 64mA to 512mA. BUG=chrome-os-partner:54821 BRANCH=none TEST=Manually tested on Amenia. a. Until the battery is initialized from cut-off mode, charging voltage doesn't drop below battery voltage max. b. With 15W charger (5V, 3A) without the battery, charger voltage is regulated to battery voltage max. Change-Id: I44172d4e9152b699976137bf070d618097c8cef7 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/356570 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Decouple temp sensor from thermal throttlingMary Ruthven2016-06-2814-1/+26
| | | | | | | | | | | | | | | Not everything with a temperature sensor uses thermal throttling. This change modifies the conditional build to enable building temp sensor source without thermal throttling. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356484 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: i2c: Don't do i2c_unwedge / reset on repeated start requeststabilize-8516.BMulin Chao2016-06-271-2/+5
| | | | | | | | | | | | | | | | | | Checking for bus busy (stop condition sent) should not apply if the caller is requesting a repeated start. BUG=None TEST=Manual on gru. Attach USB PD charger, verify i2c_unwedge is not called. BRANCH=None Change-Id: Idf13bdc530920c8da02c8d0d8064377513a5d144 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356490 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* BD99955: Added support for 'psys' & 'amonbmon' console commandsVijay Hiremath2016-06-2712-18/+216
| | | | | | | | | | | | | | | | | | | | Added console commands for the debugging purpose psys - Can be used to measure the system power amonbmon - Can be used to measure AMON/BMON voltage diff, current BUG=chrome-os-partner:54273 BRANCH=none TEST=Manually tested on Amenia psys - Ran fish task and observed psys value changes. amonbmon - AMON & BMON voltage & current are same as measured across sense resistors. Change-Id: I6653e814d9b00efe7dae9ce1fbd7ddbc2356f8e0 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/353043 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Support DP alt mode of Type-C controllerli feng2016-06-274-10/+38
| | | | | | | | | | | | | | BUG=chrome-os-partner:54413,chrome-os-partner:54649 BRANCH=none TEST=none Change-Id: I32c969a97f84bf4e9953031c69008f8e598b7920 Signed-off-by: li feng <li1.feng@intel.com> Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/355604 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: enable highsec jittery clockMary Ruthven2016-06-272-3/+2
| | | | | | | | | | | | | | | | | The highsec jittery clock was breaking the USB peripheral, because it would use bank values that mapped to frequencies less than 15MHz. This change modifies stepx16 to keep the bankvalues mapped to frequencies above 18MHz to ensure the USB peripheral can work with the high security jittery clock. BUG=chrome-os-partner:53952 BRANCH=none TEST=sudo flashrom -p raiden_debug_spi:target=AP -r test_img.bin Change-Id: If8b45583f2cd9272b6d1e79a06556724c25d6495 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356192 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Set the default idle action to SleepBill Richardson2016-06-251-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Cr50 doesn't have anything else to do and it's been a while since anyone has communicated with it (10 seconds via UART, 1 second via SPI, and the USB bus has stopped sending SOF packets), it enters one of three idle states: wfi = fully powered, just waiting for an interrupt. sleep = low power mode, but RAM is preserved. It resumes quickly. deep sleep = hibernate. RAM is lost, resume is a warm boot You can get/set the idle state with the "idle" console command. BUG=chrome-os-partner:49955,chrome-os-partner:54331 BRANCH=none TEST=make buildall To test it: * I've only tested on the debug board, because I need a serial console (not serial-over-USB) to see if it's asleep or not. * I haven't been able to knowingly force USB Suspend on my workstation, so to fake it I just unplug the USB cables. * Wait 10-12 seconds after typing anything on the serial console, then press a key. If the Cr50 was asleep, the first character will be lost. If it wasn't, you'll see the character echoed immediately. Change-Id: Icc213e50b0c38f8c2b16bcd9960e2e5550b43180 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356123 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Elm: Update battery parameters for SanyoRyan Zhang2016-06-251-5/+5
| | | | | | | | | | | | | BUG=chrome-os-partner:54617 BRANCH=master TEST=`make -j BOARD=elm` Change-Id: Id4bf6180b7776363f470f29d1b7d3d4d8095c659 Reviewed-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/353514 Commit-Ready: Ryan Zhang <Ryan.Zhang@quantatw.com> Tested-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Control power state properly on power button / lid toggleShawn Nematbakhsh2016-06-241-10/+45
| | | | | | | | | | | | | | | | | | | | | | | | - Power up the AP automatically on initial EC power-on. - In S0, wait for 8s power button hold before powering down. - In S3 and lower, power down immediately on power press. - In G3 / S5, power up on lid open. BUG=chrome-os-partner:54582,chrome-os-partner:54511 BRANCH=None TEST=Manual on gru. Verify the following: - AP powers up when battery initially attached. - `reboot` powers up AP after EC reset. - `reboot ap-off` doesn't power up AP. - `apshutdown` + `lidclose` + `lidopen` causes AP power-up. - Holding power for 4s in S0 does not change power state. - Holding power for 8s in S0 causes AP power down. Change-Id: I588056549a972212c28b9aa6a83fe2e0b179baa9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355650 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: write 0 to RBOX_WAKEUP_CLEAR to clear registersMary Ruthven2016-06-241-0/+1
| | | | | | | | | | | | | | | We need to write 0 to RBOX_WAKEUP_CLEAR after writing 1 to clear the rbox wakeup registers. BUG=none BRANCH=none TEST=after init verify 'rw .h 0x40550098' returns 0 Change-Id: Id7eda45f443300e77f293556eece72d52ca28f17 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355283 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Hsiao-heng Lee <kelinlee@google.com>
* kevin / gru: Enable host-controlled USB-C SS muxShawn Nematbakhsh2016-06-243-16/+26
| | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:52639 BRANCH=None TEST=Manual on gru with subsequent commit. Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool usbpdmuxinfo` output: Port 0: DP Port 1: USB Flip DP dongle and verify output changes: Port 0: DP INV Change-Id: I5459cb587badd46c03d1c433f13fdf21a5dc63ed Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355282 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_mux: Add support for host-controlled 'virtual' USB muxShawn Nematbakhsh2016-06-248-4/+147
| | | | | | | | | | | | | | | | | | | | | | | | For designs where the host SOC is responsible for setting the USB-C SS mux, the EC must track the desired mux state and inform the host when the desired state changes. Then, the host must ask the EC for the new desired state and set the mux accordingly. BUG=chrome-os-partner:52639 BRANCH=None TEST=Manual on gru with subsequent commit. Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool usbpdmuxinfo` output: Port 0: DP Port 1: USB Flip DP dongle and verify output changes: Port 0: DP INV Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6a99ce93a76c3197f9195cfaa25c5217d09aeb75 Reviewed-on: https://chromium-review.googlesource.com/355281 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin / gru: Remove console features to save RAM spaceShawn Nematbakhsh2016-06-241-4/+5
| | | | | | | | | | | | | BUG=chrome-os-partner:52876 BRANCH=None TEST=`make buildall -j` Change-Id: I10bebf4c6af4e23f4e07bbb609626424434c721a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355280 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* sb_firmware: update lockfile pathDavid Hendricks2016-06-241-1/+1
| | | | | | | | | | | | | | | This updates the lockfile path for FHS 3.0 since powerd as well as other pieces of software are migrating over. BUG=chromium:616620 CQ-DEPEND=CL:351271 BRANCH=none TEST=compiled Change-Id: I6aa5fa30225e45039316e4a3af0e50cdef0fdf4e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/351345 Reviewed-by: Dan Erat <derat@chromium.org>
* Cr50: Added TPM register write/read to extract FW versionScott2016-06-241-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Created a new TPM register define at the beginning of the vendor defined configuration register space 0xF90 - 0xFFF. Note that this same space is defined for each locality. In order to retrieve the FW version string, the TPM register at offset 0xF90 needs to be written. This will initialize a the pointer index to 0. The same register is then read by the AP and each read will return up to 4 bytes of the FW version string. Once Cr50 detects the string termination character, it stops incrementing the index so that 0s continue to be returned for each subsequent read. In addition there is a max value of reads for the case when the version string is corrupt and doesn't have a '\0' character. BRANCH=none BUG=chrome-os-partner:54723 TEST=Manual Added a routine in /coreboot/src/drivers/spi/tpm.c tpm_init() that does the write/read sequence described above. This test routine produced the folloiwng AP console output: Reading TPM EC Version!! scollyer@ code goes here Read 1: cr50 0x30 Read 2: _v1. 0x2e Read 3: 1.47 0x37 Read 4: 81-1 0x31 Read 5: 3619 0x39 Read 6: 95-d 0x64 Read 7: irty 0x79 Read 7: 0x0 Cr50 FW Version: cr50_v1.1.4781-1361995-dirty Read Count = 29 Initialized TPM device CR50 revision 0 Change-Id: I5d68a037f7a508e3109c35e841dbcb3a893ce22f Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355701 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* tpm: use proper locality zero SPI bus addressesVadim Bendebury2016-06-231-10/+11
| | | | | | | | | | | | | | | | | The "PC Client Protection Profile for TPM 2.0" document defines SPI bus addresses for different localities. That definition is not honored in the cr50 implementation, this patch fixes it: locality zero register file is based off 0xd40000. BRANCH=none BUG=chrome-os-partner:54720 TEST=verified that upstream Linux driver is happy now Change-Id: Ibc01035a5dcc823a0ec82374d758de08a70083b6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355610 Tested-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* ec_commands: Be sure all C code is within #ifnef ACPIGwendal Grignou2016-06-231-2/+2
| | | | | | | | | | | | | | When __ACPI__ is set, only #define are allowed. BRANCH=none BUG=chrome-os-partner:52433 TEST=Coreboot compiles with this code. Change-Id: Iadb3893960f16ff49aa4f4e5871d5d17cbb87642 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355570 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* reef: force PMIC reset on initial bootKevin K Wong2016-06-231-0/+17
| | | | | | | | | | | | | | | | | | | | On EC reset where PMIC_EN will be pulled low, PMIC could get into an unknown state and will not sequence properly on sub-sequent boot. This is a temporary workaround for Reef Proto, a hardware change will be implemented on EVT. BUG=chrome-os-partner:53974,chrome-os-partner:54507 BRANCH=none TEST=Reef powers to S0 and starts coreboot after EC reset Tested with servo cold reset button and console reboot command Change-Id: I32aa004b000895da2c97d1014a8ef48c0a98779d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/354762 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Enable external power interrupt GPIOVijay Hiremath2016-06-233-8/+6
| | | | | | | | | | | | | | | | | BUG=chrome-os-partner:54503 BRANCH=none TEST=Manually tested using console commands on both the ports. a. Issued 'gpioget AC_PRESENT', observed AC_PRESENT is 1 when AC connected & 0 when AC disconnected. b. Issued 'hibernate' & on plugging in the AC, device boots to S0. Change-Id: Iad09914d79cdbd798fb650146321eafed06eb91c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/354721 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: NvMem: Added mutex lock protection for cache memoryScott2016-06-223-52/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added mutex lock for nvmem write/move operations. In the current implementation, there is no single entry point for the platform specific NvMem calls. The mutex lock is coupled with a task number so that the same task can attempt to grab the lock without stalling itself. In addition to the mutex lock, changed where the cache.base_ptr variable is updated. Previously, this was done prior to the partition being copied from flash to the shared memory area. Now, the variable is only updated after the copy so that read operations will always read from the correctly from either flash or from cache memory if a write operation has been started. BRANCH=none BUG=chrome-os-partner:52520 TEST=Manual make runtests TEST_LIST_HOST=nvmem and verify that all tests pass. Tested with tcg_test utility to test reads/writes using the command "build/test-tpm2/install/bin/compliance --ntpm localhost:9883 --select CPCTPM_TC2_3_33_07_01". Change-Id: Ib6f278ad889424f4df85e4a328da1f45c8d00730 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353026 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mkpb: Add MKBP support over ACPIGwendal Grignou2016-06-224-7/+21
| | | | | | | | | | | | | | | | | | | | Add a host event to support MKPB: When sent, the ACPI code will send a notification to the kernel cros-ec-lpcs driver that will issue EC_CMD_GET_NEXT_EVENT. We can allow code (sensor stack for instance) that uses MKBP to work on ACPI based architecture. Obviously, host event over MKPB is not supported. BRANCH=none BUG=b:27849483 TEST=Check we get sensor events on Cyan through the sensor ring. (cyan branch) Change-Id: Iadc9c852b410cf69ef15bcbbb1b086c36687c687 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353634 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rk3399: kevin: Adding get_rtc_alarm functionality.Shelley Chen2016-06-212-6/+67
| | | | | | | | | | | | | | | | | | | | | | Adding ability to get # seconds before rtc alarm goes off. BUG=chrome-os-partner:52218 BRANCH=None TEST=ectool rtcgetalarm w/o setting returns Alarm not set. ectool rtcsetalarm 30; ectool rtcgetalarm to make sure counting down to 0. After alarm goes off, rtcgetalarm should return alarm not set again. rtcsetalarm 30; rtcgetalarm to check alarm is set. rtcsetalarm 0; should disable alarm. Use rtcgetalarm to ensure that alarm is disabled. Change-Id: I176b12fe2dda08eedd23ea33dc64785f09f1d9ae Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353331 Reviewed-by: Shawn N <shawnn@chromium.org>
* build: Skip cr50 board in `make buildall` if private folder not presentShawn Nematbakhsh2016-06-211-0/+4
| | | | | | | | | | | | | | BUG=chromium:621993 BRANCH=None TEST=`make buildall -j` from public checkout succeeds. Also verify cr50 still built from private checkout. Change-Id: I982806e282146aab76154b51c366226d3d1aed14 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/354540 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Elm: update LED controlstabilize-8481.BRyan Zhang2016-06-201-9/+39
| | | | | | | | | | | | | following Change#227416 to meet client's spec. BUG=chrome-os-partner:54263 BRANCH=master TEST=`make -j BOARD=elm`, check factory force IDLE, works good Change-Id: I1f0abdcbd56eeab379a6258869ccc133ff80736d Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/353521 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: vbnvcontext: Fix misaligned accessShawn Nematbakhsh2016-06-201-11/+18
| | | | | | | | | | | | | | | | | | | | We have no guarantee about the alignment of our input buffer so don't use 32-bit access. BUG=chrome-os-partner:54561 BRANCH=None TEST=Manual on gru. Enable CHROMEOS_VBNV_EC, verify exception isn't encountered on host command 0x17. Also verify call to system_set_vbnvcontext followed by system_get_vbnvcontext results in same data being read back. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I4df636b70c71a43a2dd6f584ee965135e90b4351 Reviewed-on: https://chromium-review.googlesource.com/354132 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kevin: add CHARGER_NARROW_VDC to prevent DC-DC stoppingWonjoon Lee2016-06-191-0/+1
| | | | | | | | | | | | | | | | BD99955 DCDC wiil turn off Vsys voltage under VSYSVAL_THL_SET or VREF_BAT<VBAT if Charging Voltage set under actual battery voltage or VSYSVAL_THL_SET. BUG=chrome-os-partner:53777 BRANCH=none TEST=boot-up without battery. using zinger or oem supplier used kevin rev2, rev3 Change-Id: I03c5c52790b2d481be3fa942054516fbefa3ce98 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/348563 Reviewed-by: Shawn N <shawnn@chromium.org>
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