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* kevin: Add FIFO for ARC++ support.stabilize-8737.BGwendal Grignou2016-08-232-13/+25
| | | | | | | | | | | | | | | Add Sensor FIFO, set the sensors in force mode since we haven't enabled their FIFO. BRANCH=kevin BUG=b:27849483 TEST=Check kernel load cros-ec-ring. Check ARC++ get accel info with AIDA64. Change-Id: I1c4d5c1291d2c778fdabd8b8f4e6b6a370f37b04 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373140 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx/i2c.c: Verify that controller value is not negative before using itMartin Roth2016-08-231-2/+19
| | | | | | | | | | | | | | | | | | | | The function i2c_port_to_controller() returns a negative value if the port value was out of range. This wasn't being checked before the controller value was getting used which could lead to using an invalid value as a pointer to a structure. This returns an error where it makes sense, and just ignores the incorrect value otherwise. TEST=Build BUG=None BRANCH=None Change-Id: Ie8967bc4db87d3dd1863a2e36e35ac87e6161132 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371400 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* reef: ensure board can boot again after entring G3 after SW syncAaron Durbin2016-08-231-2/+6
| | | | | | | | | | | | | | | | | | When SW sync is enabled and the board enters G3 after being up there was no way to boot the board again because the system_jumped_to_this_image() check disallowed the pmic startup sequence. One needs to check if the pmic is also already on before bailing on the pmic startup sequence. BUG=chrome-os-partner:56530 BRANCH=None TEST=Booted. Jumped to RW EC. Shutdown system. Can boot again once G3 entered. Change-Id: I71670ceee09536a282479d1eca6a3ce264f0f5d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374080 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cr50: remove internal pull up on DIOM0Mary Ruthven2016-08-234-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | There is leakage on SYS_RST_ODL from the internal pullup cr50 has on DIOM0. This change removes the internal pullup. Without the internal pull up SYS_RST_ODL is not pulled up whenever the EC is off. I changed how sys_rst_asserted is handled so it will ignore the sys_rst interrupt whenever rbox asserts EC_RST to make sure cr50 doesn't reset itself every time it resets the EC. If the EC resets itself and sys_rst_l is no longer pulled up, it is fine if cr50 resets. BUG=chrome-os-partner:53544 BRANCH=none TEST=manual 'rw 0x40550010 1' causes the EC to reset but not cr50 On the development board verify DIOM0 is not pulled up. Test cr50 boots normally on reef and gru Change-Id: Ic1d4d160ddb0d69081cb1f194d50939dac6fc5c2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373838 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* btle: Accepts and maintains connectionsLevi Oliver2016-08-233-5/+321
| | | | | | | | | | | | | | | | | | Can now accept and maintain a single connection indefinitely by sending empty packets at every connection interval to keep the connection alive. TEST=BTLE dongle sending connect requests and connecting to NRF51 running this code. Connection was established and ran for at least 48 hours until manual termination. BUG=None BRANCH=None Change-Id: Iad4bd434ecd1edd6c5c8dfe8b72ca41fd82d0bb4 Signed-off-by: Levi Oliver <levio@google.com> Reviewed-on: https://chromium-review.googlesource.com/370839 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charger/bd99955: only print data if read was successfulMartin Roth2016-08-231-1/+2
| | | | | | | | | | | | | | | In console_command_bd99955(), because the return value wasn't being checked before displaying the data variable, it could be printed without being initialized. TEST=Build BUG=None BRANCH=None Change-Id: I03e0aae6fee33e32f648d952d6f2906e71f67ea2 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371398 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* npcx/flash.c: Init return value for successMartin Roth2016-08-231-1/+1
| | | | | | | | | | | | | | | | | In flash_physical_erase(), if the area being erased was already cleared, the return value would never be set, and would be returned without being defined. Initialize the value so that if the area being erased is clear, we return success. TEST=Build BUG=None BRANCH=None Change-Id: Ib13e0be0ad1d3ad23c065b407c35e7b5c4db8487 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371399 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: gpio: Enable wake GPIO interrupts prior to hibernateMulin Chao2016-08-231-1/+4
| | | | | | | | | | | | | | | | This is necessary after the pending patch to not enable all GPIO interrupts by default. BRANCH=None BUG=chrome-os-partner:56486 TEST=Manual on kevin, run 'hibernate', attach AC and verify wake occurs. Change-Id: I04d2c6edf9fb32b1a6a7e6a5ed4d2c53895e00f0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374179 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: shi: Properly disable interrupts throughout sending of HC responseShawn Nematbakhsh2016-08-231-9/+9
| | | | | | | | | | | | | | | | | Expand interrupt disable to include checking of our SHI state in case preemption occurs immediately afterward. BUG=chrome-os-partner:55795 BRANCH=None TEST=Manual on kevin, verify no errors through 700+ sysjumps. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Icb8a5bdd03dbf87f6a25b4175f73c932d48db726 Reviewed-on: https://chromium-review.googlesource.com/374021 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: Don't enable GPIO interrupts by defaultShawn Nematbakhsh2016-08-232-18/+14
| | | | | | | | | | | | | | | | | | | GPIO interrupts must first be enabled with a call to gpio_enable_interrupt() to prevent ISRs from being run before prerequiste modules are initialized. BUG=chrome-os-partner:56486 BRANCH=None TEST=Manual on kevin, stress test sysjump for ~1 hour (~700 sysjumps) without failure. Change-Id: Ia4006ef1b0c3218dfe5c92fde6713c10b0d22d2a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374020 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* reef: remove DEFERRABLE_MAX_COUNTVincent Palatin2016-08-231-3/+0
| | | | | | | | | | | | | | | | | | | DEFERRABLE_MAX_COUNT is no longer used and has been removed from other boards. Reef was probably in-flight at that time, clean up board.h Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall Change-Id: Iee11b0519d647be3beb0c164a5a82bbb1edb54c4 Reviewed-on: https://chromium-review.googlesource.com/373778 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* kevin: Increase UART TX buffer size to 4kbNicolas Boichat2016-08-231-0/+4
| | | | | | | | | | | | | | | | | | We have enough memory for that, and it makes it possible to poll the logs from AP much more unfrequently. BRANCH=none BUG=chrome-os-partner:56460 TEST=make buildall -j TEST=Boot kevin, cat /sys/kernel/debug/cros_ec/console_log does not miss any data. Change-Id: I7dc880a27d34f97746a8fde00e49d8d08ed85b9d Reviewed-on: https://chromium-review.googlesource.com/373285 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Use parse_bool() for boolean argsBill Richardson2016-08-224-24/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The parse_bool() function exists so we don't have to litter our console commands with stuff like this: if (!strncasecmp(argv[1], "on") || !strncasecmp(argv[1], "enable" || !strncasecmp(argv[1], "true" || [...] This CL uses parse_bool instead of that kind of thing so I don't have to remember which commands use "enable" and which use "on" and so forth. I only changed the commands that Cr50 uses. BUG=none BRANCH=none TEST=make buildall; test on Cr50 hardware I tested all the affected commands to ensure that they still work correctly: usb, ccd, flashwp (which doesn't do anything anyway). Change-Id: I7d875ab22934fb4b500e3d0f62ebe3e04101272d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373658 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: implement firmware upgrade protocol version 3Vadim Bendebury2016-08-223-126/+216
| | | | | | | | | | | | | | | | | | | | | | This patch modifies CR50 code to switch to firmware update protocol version 3. In this version both SPI and USB updates use exactly the same messages (apart from the size field added by USB to help reassembly of the fragmented frames). Bot unused RO and RW sections can be now programmed. BRANCH=none BUG=chrome-os-partner:55789 TEST=on a Kevin running the existing cr50 image programmed the new cr50 image, restarted the device, programmed the cr50 image again (this time using version 3), restarted the device, then programmed both RO and RW images and restarted the device. Each time verified that the proper image is running. Change-Id: I0cf196ec6de1786510433f8252164a33ccdc6dec Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371941 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* reef: use only CONFIG_USB_PD_VBUS_DETECT_CHARGERKevin K Wong2016-08-221-1/+0
| | | | | | | | | | | BUG=chrome-os-partner:56392 BRANCH=none TEST=Both C-Ports are able to detect any kind of chargers Change-Id: I6f6dbb93746d33a5750442c1b3bbe381cfd3a434 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/373659 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* chip/g/sps: Initialize received_data pointer to NULLMartin Roth2016-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | I don't think that the received_data pointer in sps_rx_interrupt can actually be used without initialization in the current code flow, but GCC 5.3 thinks that it can, and throws an error. sps_check_rx() always sets the pointer or returns 0. In either case we should be ok, but initializing it to null here won't hurt anything since it's not masking an actual error. BUG=None BRANCH=None TEST=Build all boards successfully. Change-Id: Idaea7efd1af3067c492a3ade4c89104e975f4c1d Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/370663 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* BD99955: Map PD port number to charge port numberVijay Hiremath2016-08-226-26/+37
| | | | | | | | | | | | | | | | Charger port number may differ from PD port number hence added a macro to select appropriate port numbers during compilation. BUG=chrome-os-partner:54970 BRANCH=none TEST=Reef can negotiate on both the ports. Change-Id: Id3b4b639a5f8698c27341be037bb09370910cac5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/357836 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Add "wp" console command to control EC_WP_LBill Richardson2016-08-222-0/+33
| | | | | | | | | | | | | | BUG=chrome-os-partner:49959 BRANCH=none TEST=manual On the Cr50 console, use the "wp" command to get/set the desired state. On the EC console, use "gpioget wp_l" to watch it change. Change-Id: I5978e6116ad0a07a7a61a8356dc1daf79e2397d0 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373618 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* it83xx: lpc: add support 'CONFIG_KEYBOARD_IRQ_GPIO' and fix lpc_init()Dino Li2016-08-221-0/+68
| | | | | | | | | | | | | | | | | | | | | | 1. To assert keyboard IRQ GPIO pin instead of SERIRQ if keyboard data ready to send. 2. Clear STATUS_PROCESSING bit in lpc_init() to avoid host waiting after a sysjump. 3. Save and restore event masks while doing a sysjump. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. keyboard work normally if host support this keyboard interrupt. 2. Software sync done and jumping to RW and boot to kernel. 3. EC generate SCI normally after a sysjump. Change-Id: Ib0d9785106d4d4d21f8e9a6d1f0548f187fa7976 Reviewed-on: https://chromium-review.googlesource.com/372499 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Disable spstest command.Bill Richardson2016-08-221-5/+0
| | | | | | | | | | | | | | This command was used for early testing of the SPI slave interface. It's no longer needed, so disable it to save space. BUG=none BRANCH=none TEST=make buildall; test on Cr50 hardware Change-Id: If730f909c7361b1179e23b2bf1d07c9d51aa6e8f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373619 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* charger: bd99955: Prevent truncated console command outputShawn Nematbakhsh2016-08-221-1/+3
| | | | | | | | | | | | | | | | | "bd99955_dump" output may be larger than our UART output buffer, so flush our buffer in between prints. BUG=None TEST=Run 'bd99955_dump' on kevin, verify full output is seen. BRANCH=None Change-Id: I5816e0ce0c000bf63bc09502888e5acc9c4728ae Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373660 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kevin: Save and restore display backlight PWM duty across sysjumpShawn Nematbakhsh2016-08-221-0/+25
| | | | | | | | | | | | | | | | | | Display backlight going down for an extended period of time is a major user annoyance, so save the duty prior to sysjump and restore it upon init. BUG=chrome-os-partner:56390 BRANCH=None TEST=On kevin, run "sysjump rw" from recovery screen, verify backlight goes black for a fraction of a second and comes back to previous level. Change-Id: I98f12ace9b933874ba9088a790b9efa0941050ed Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373621 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* g: Remove unused CONFIG_RBOX_DEBUG featureBill Richardson2016-08-223-95/+2
| | | | | | | | | | | | | | | | | | This feature is not enabled, is awkwardly written, and shouldn't be left lying around to use as a bad example. This CL doesn't change any compiled code. A followup CL will add a working RBOX interrupt handler. BUG=none BRANCH=none TEST=make buildall; test on Cr50 hardware Change-Id: I5d0701f55ab9521bf1f29e7ec18994c4401d68fb Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373600 Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* flash_ec: Add check for servo_has_cold_reset.Kevin Cheng2016-08-221-1/+7
| | | | | | | | | | | | | | | | | | When flashing a servo v4, the function will try to initiate a cold_reset but that interface does not exist for a servo v4. Add in a check for cold_reset before trying an ec_reset to prevent printing the useless error message 'No control named "cold_reset"'. BRANCH=None BUG=None TEST=flashed and did not see error message anymore. Change-Id: I6086883f002b4961807ae0663b0ee32aea4c63d8 Reviewed-on: https://chromium-review.googlesource.com/365151 Commit-Ready: Kevin Cheng <kevcheng@chromium.org> Tested-by: Kevin Cheng <kevcheng@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* npcx: Apply deep idle bypass for hibernateMulin Chao2016-08-221-1/+24
| | | | | | | | | | | | | | | | | | | Although probability is small, we still have chance to encounter the same symptom which CPU's behavior is abnormal after wake-up from deep idle. Apply the same bypass in task.c but not enable interrupt to solve it. Modified sources: 1. system.c: Apply deep idle bypass for hibernate. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall; test "hibernate"&"hibernate 10" on wheatley. Change-Id: Ib00b9932ac34414d6a177d60668664ab31284a79 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/373300 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
* g: Remove obsolete spstpm commandBill Richardson2016-08-221-30/+0
| | | | | | | | | | | | | | | | | | At one time we could switch between TPM and HC protocols on the SPI slave bus. We disabled the HC protocol long ago with commit e4690f61524e. This CL removes the spstpm command, since there's no longer any point to having a console command to disable the TPM protocol too (which would leave us with nothing listening to incoming traffic on the SPI bus). BUG=none BRANCH=none TEST=make buildall; test on Cr50 hardware Change-Id: Ic5028dfc1631fab4ddf2584635cb48be50d05d4d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373638 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kevin: Disable hostcommand debuggingNicolas Boichat2016-08-221-0/+3
| | | | | | | | | | | | | | | | | kevin EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD is called every 100ms. Even when hcdebug is set to off, we still get command errors. BRANCH=none BUG=chrome-os-partner:56460 TEST=make buildall -j TEST=Flash kevin EC, see that output is fairly quiet. Change-Id: Iad974c463c8dd91960e872ec977fe0e653696701 Reviewed-on: https://chromium-review.googlesource.com/373284 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: support Rp/Rp debug accessoriesVincent Palatin2016-08-222-30/+105
| | | | | | | | | | | | | | | | | | | | | | Support Rp/Rp debug accessories in the USB PD state machine including detecting the polarity and the available type-C current. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:52592 TEST=manual, plug a Suzy-Q reworked with Rp3A0/Rp1A5 resistors on a Kevin, and see the PD state machine is going to PD_STATE_SNK_ACCESSORY (and leaving it on unplug). Re-verify a few existing accessories (Rd/Rd SuzyQ, legacy RpUSB cable, Rp3A0 power supply). Change-Id: Icef6c90027105d7c633f2785210ab9dae74fc33c Reviewed-on: https://chromium-review.googlesource.com/368700 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* it83xx: add reset cause of reset pinDino Li2016-08-221-1/+1
| | | | | | | | | | | | | | | | | | If reset was caused by reset pin, we need this reset cause for next sequence(recovery key). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=To assert EC WRST pin and we will get the reset cause for both power-on and reset-pin. Change-Id: I0361091680a148df07cbbb8f4e53635dbf48fdee Reviewed-on: https://chromium-review.googlesource.com/371798 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* TCPM: it83xx: support Rp 1.5/3.0A pullup configurationDino Li2016-08-221-7/+17
| | | | | | | | | | | | | | | | | | Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:54452 TEST=1. To check appropriate register setting. 2. Measure the CC voltage by connecting USB-C to DP cable to EVB. Default : 433mV CONFIG_USB_PD_PULLUP_1_5A: 951mV CONFIG_USB_PD_PULLUP_3A : 1.72V Change-Id: Id5a36ded94121db4343c48ecea19a5a533244f43 Reviewed-on: https://chromium-review.googlesource.com/371020 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: fix i2c moduleDino Li2016-08-221-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | 1. If one i2c transaction includes timeout and done events at the same time, the transaction result will be timeout. Fixed: The transaction is succeed instead of timeout. 2. The interrupt of i2c will not be enabled if an i2c write transaction is split into two or more xfer. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Console commands:'i2cscan', 'i2cxfer', and 'battery'. 2. Use two or more i2c_xfer(the first with flag 'I2C_XFER_START' and the last with flag 'I2C_XFER_STOP') to do a i2c write transaction and no error. Change-Id: Ieb2cb229748ac9504cf1636a2826bbb3097aa55c Reviewed-on: https://chromium-review.googlesource.com/360762 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* anx7688: Add custom vbus functionNicolas Boichat2016-08-211-1/+16
| | | | | | | | | | | | | | | | | On ANX7688, POWER_STATUS.VBusPresent is averaged 16 times, so its value may not be set to 1 quickly enough during power role swap. Therefore, we use a proprietary register to read the unfiltered VBus value. BRANCH=oak BUG=chrome-os-partner:55221 TEST=LG monitor works over type-C, power role swap looks good Change-Id: I68572c34440be65882f431bb892ed032da05bd0a Reviewed-on: https://chromium-review.googlesource.com/364351 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kevin: Keep LED test status with ectool led.Jongpil Jung2016-08-211-2/+0
| | | | | | | | | | | | | | | | | | | | With "ectool led power blue=0 green=100 red=100", LED color is changed. But LED will turn off immediately. To keep color with "ectool led", we need remove led turn off when "Battery/Power LED" auto control are not enabled. BUG=chrome-os-partner:56179 BRANCH=none TEST=manual, run ectool command on user space. ectool led power blue=0 red=100 green=100 ectool led power blue=100 red=0 green=100 ectool led power blue=100 red=100 green=0 ectool led power auto Change-Id: Ifa6b426443ca800f34ba7c61cea6e2e49694fb0e Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/368586 Reviewed-by: Shawn N <shawnn@chromium.org>
* tpm: limit the length of the string reported through TPM_FW_VERVadim Bendebury2016-08-211-36/+9
| | | | | | | | | | | | | | | | | | | | The version string reported through TPM_FW_VER register has become way too long, it takes too much time to transmit at startup, especially at i2c speeds. Let's limit it to the essentials: header versions and hashes of the active RO and RW sections. BRANCH=none BUG=chrome-os-partner:49954 TEST=verified version in the firmware log localhost ~ # grep cr50 /sys/firmware/log Firmware version: B2:0 RO_A:0.0.1/84e2dde7 RW_A:0.0.3/cr50_v1.1.5106-f7349c9+ Change-Id: Ic391f90673fe21c0100b776944f6efc080213ff3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/372380 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* reef: add power led behaviorli feng2016-08-211-12/+57
| | | | | | | | | | | | | | | | There is only one set LED in reef, so with charger attached, LED behave as charging LED; without charger, as power LED. BUG=chrome-os-partner:55492 BRANCH=none TEST=on reef proto, verified power led behavior is correct in s0/s3/g3 Change-Id: If6b83c46fc4b8b455531698177f559ca319d241a Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/366102 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: set the BUSY bit while handling ACPI command write.Kevin K Wong2016-08-212-8/+15
| | | | | | | | | | | | | BUG=chrome-os-partner:55583 BRANCH=none TEST=verified OBF status is cleared during idle without event which means kernel driver waited for the BUSY bit and read the data. Change-Id: I79357fea5483fe7a175c60f54235926e105ec832 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/373043 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* sweetberry: add i2c supportNick Sanders2016-08-217-5/+814
| | | | | | | | | | | | | | | | | stm32f446 has two types of i2c blocks, the traditional stm i2c, and "fast mode plus" i2c, which need different drivers. This commit adds both, muxed in i2c-stm32f4, as the ec codebase doesn't really support multiple types of the same interface. BUG=chromium:608039 TEST=i2c works on all 4 channels BRANCH=None Change-Id: I6a9ac632f44142bd809ffee5782a192ae47af1f0 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368358 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_updater: host side support protocol version 3Vadim Bendebury2016-08-213-105/+283
| | | | | | | | | | | | | | | | | | | | | This patch introduces support for the cr50 firmware update protocol version 3. It is described in more details in the comment in the patch, the bottom line is that both RO and RW updates are supported, and SPI and USB modes use the same protocol now. The notions of PDU (protocol data unit) passed between the host and the programming function on the CR50 is introduced, and USB mode framing is described. BRANCH=none BUG=chrome-os-partner:55789 TEST=verified that version 1 and 2 updates still work. Version 3 mode was tested later, when the device side patches were applied. Change-Id: If51854b6a0b140730e85853bc42039233550fe8c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371509 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Change transfer_endpoint to transfer_descriptorVadim Bendebury2016-08-211-24/+24
| | | | | | | | | | | | | | | | | | | | In preparation to cr50 update protocol enhancements allowing to update both RO and RW sections this patch is changing the name of the structure containing communications endpoint information. In the upcoming patches more fields are going to be added to this structure, it is cleaner to change its name and existing use before adding new features. BRANCH=none BUG=chrome-os-partner:55789 TEST=make -C extra/usb_updater Change-Id: I5ca0b6da75067a4f01ea80b6a6ca49a50e1136ab Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371508 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: usb_updater: add command line option to allow updating the RO sectionVadim Bendebury2016-08-211-1/+7
| | | | | | | | | | | | | | | | | | | | | This just adds the new command line option and a help message for it. This option will be used to signal that the RO section update is required along with the RW section update when invoking usb_updater. The flag indicating presence of the option will be saved in the endpoint structure so it is available at different layers of the code. BRANCH=none BUG=chrome-os-partner:55789 TEST=built usb_updater and invoked it with --help option, observed the new option showing up in the output. Change-Id: Ief35a553651d29ca39c42c5af7294d3aba223b02 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/369160 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: usb_updater: clean up update protocol handlingVadim Bendebury2016-08-214-100/+86
| | | | | | | | | | | | | | | | | | | | | | In preparation of introducing new update protocol version this patch cleans up the existing implementation. The receive and transmit PDU headers are separated into their own structures and are now shared between the server and client sides. Some comments have been added to better explain different protocol versions' details. BRANCH=none BUG=chrome-os-partner:55789 TEST=verified that it is still possible to update RW_A and RW_B on a Kevin CR50, works using both USB and SPI. Change-Id: Ied65b2c2a7800bae045f1d2dd64e58dd5e793d27 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368989 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Fix AES CFB encryption for non-divisible-by-16 lengthsAndrey Pronin2016-08-201-18/+14
| | | | | | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:56284 TEST=login as new user, check in log that TPM2_Create is unmarshaled without TPM_RC_INSUFFICIENT errors. Change-Id: Ie0c0aeb2486b21eaffccf6565f68f4d96f2121bf Signed-off-by: Andrey Pronin <apronin@google.com> Reviewed-on: https://chromium-review.googlesource.com/373100 Commit-Ready: Andrey Pronin <apronin@chromium.org> Tested-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Revert "shi: Enable SHI interrupt from CS interrupt"Shawn Nematbakhsh2016-08-211-43/+20
| | | | | | | | | | | | | This reverts commit 77ae58a3a32c40d42ac0d66b0ac772c64fb39bf6. Host command interface still getting wedged. BUG=chrome-os-partner:55710,chrome-os-partner:55795,chrome-os-partner:56254 BRANCH=None TEST=None Change-Id: I2a4d39d222ebfd9aa78cc9f5231c38ebd50e80ce Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373739
* shi: Enable SHI interrupt from CS interruptShawn Nematbakhsh2016-08-201-20/+43
| | | | | | | | | | | | | | | | | | | | | | Enable the SHI interrupt only after we have received and begun processing our host command. Disable the SHI interrupt once our transaction is complete (with either success or error status). This will prevent the SHI interrupt from being asserted at the same time as the CS interrupt, which can lead to the SHI interrupt being serviced first. Also, it avoids needless, non-useful SHI interrupts during error transactions. BUG=chrome-os-partner:55710,chrome-os-partner:55795,chrome-os-partner:56254 BRANCH=None TEST=Manual on gru. Stress test flashrom w/ unpowered Donette attached (for host command spam), verify no errors encountered after 100 minutes. Also verify host command interface functions properly after sysjump. Change-Id: I41e3deb382897cd4286e6ac96f4f3066bf7a94a7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371510 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* kevin: usb_pd: Accept VCONN swap only when 5V is availableShawn Nematbakhsh2016-08-201-2/+1
| | | | | | | | | | | | | | BUG=chrome-os-partner:56247 BRANCH=None TEST=Connect kevin to samus, run "pd 0 swap vconn", verify vconn state shown by "pd 0 state" toggles. Also verify swaps instigated by samus toggle vconn state on kevin. Change-Id: Ieb8b7fe8b5e56a0d6fd29deba91efb2686c41ea4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371378 Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* COMMIT-QUEUE.ini: Change builders to compile-only.Aseda Aboagye2016-08-191-2/+4
| | | | | | | | | | | | | | | | | | Really, we only care if the chromeos-ec package fails to build and not if the test stages fail. The test stages don't actually test aganist our EC changes anways, so it's kind of a waste of time to run them. Besides, that's what FAFT is for. BUG=None BRANCH=None TEST=\_()_/ Change-Id: I6a1db02a05f17b276a16543ced58efa8a04fb997 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/372325 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mkbp_event: Provide host event wake mask to hostShawn Nematbakhsh2016-08-191-0/+15
| | | | | | | | | | | | | | | | | | | Use EC_CMD_HOST_EVENT_GET_WAKE_MASK (already implemented on LPC platforms) to share CONFIG_MKBP_WAKEUP_MASK with the host. BUG=chrome-os-partner:56164 BRANCH=None TEST=Run `ectool eventgetwakemask` on kevin, verify CONFIG_MKBP_WAKEUP_MASK mask is printed. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I252c8d6297e3db97dd3df506b3a386a3ad777174 Reviewed-on: https://chromium-review.googlesource.com/372320 Commit-Ready: Douglas Anderson <dianders@chromium.org> Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* chip/npcx/lpc: Fix SCI and SMI generationFurquan Shaikh2016-08-192-6/+37
| | | | | | | | | | | | | | | | | | | | | | Following steps need to be followed for SCI/SMI generation: 1. If automatic mode is being used, set SCIE/SMIE bit in HIPMIE register during lpc_init. This step needs to be performed only once. 2. If SCI/SMI generation is required, set ST1/ST2 bit in HIPMST register during update_host_event_status. 3. In lpc_generate_sci/smi, if automatic mode is being used, set SCIB/SMIB bit in HIPMIC register. BUG=chrome-os-partner:55489 BRANCH=None TEST=lidclose behavior verified in kernel. Change-Id: Ib6e0ee32bc06a8c51297010ac4843a7de45a99bd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/371059 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* g: report RW header version along with code revisionVadim Bendebury2016-08-192-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | Header version fields are instrumental when determining which of the available images is started by the RO. Let's include the header version when reporting the RW images' version as well as RO. BRANCH=none BUG=none TEST=verified that RW header information is now included in the version command output: > vers Chip: g cr50 B2 Board: 0 RO_A: * 0.0.8/8755904e RO_B: -1.-1.-1/ffffffff RW_A: 0.0.1/cr50_v1.1.5093-751a584+ RW_B: * 0.0.1/cr50_v1.1.5093-d27f65f Build: 0.0.1/cr50_v1.1.5093-d27f65f ... Change-Id: I675c473a277e272f55670324fafdab8a6e6edd78 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/370939 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* sweetberry: add build target for sweetberryNick Sanders2016-08-196-0/+236
| | | | | | | | | | | | | | sweetberry is an stm32f446 based power monitoring board, with 48 channels of INA current sense chips BUG=chromium:608039 TEST=boots BRANCH=none Change-Id: If263bcee3a648ba3605f991999d481b7a0e2a1db Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/370718 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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