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* Cr50: I2CS TPM: Prevent sleep when I2CS is activestabilize-8838.BScott2016-09-253-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to the TPM SPI interface, added code to disable sleep an I2CS interrupt is received. Enabling sleep follwoing a 1 second delay when the TPM fifo register has been read by the host. The I2CS TPM layer doesn't know when a command has finished, but the one second delay is more than enough delay since sleep will be disabled again when the next I2CS interrupt is received. BRANCH=none BUG=chrome-os-partner:40397 TEST=manual Tested without these changes first. Shortened sleep delay to 30 seconds, and disconnected suzyq. Waited 30 seconds then issued the command on the AP console: tpmc read 0x1007 0xa [ 59.796813] tpm tpm0: tpm_transmit: tpm_send: error -16 ERROR: write failure to TPM device: Device or resource busy In addition, using logic analyzer verifed that there was activity on SDA/SCL but no response from Cr50. With this CL in place, ran the test and got the following: tpmc read 0x1007 0xa 2 0 1 0 1 0 0 0 0 4f With the logic analyzer I was able to confirm that there was no activity from the host on the I2CS bus until the command was issued. Change-Id: If07573ae8f72b983bca57979d53c22660b91b95e Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/387910 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Cr50: I2CS: Fixed i2cs word aligned fifo write functionScott2016-09-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed an issue with word aligned write to fifo routine. There were two errors. In the top section, the fifo was being read always from the beginning word or the hw fito, but the updated word was written back to the proper location. The same error was in the section that dealt with the last < 4 bytes. Both have been corrected. The error in the top section would in practice be invisible because flow control prevents TPM fifo reads from happening while one is in progress. The error in the bottom section was responsible for the problem as described in chrome-os-partner:57782. BRANCH=none BUG=chrome-os-partner:57782 TEST=manual Used special AP fw build that supports a 'tpm_raw' command to initiate the Cr50 TPM fifo write/read. 'tpm_raw 0x80 0x01 0x00 0x00 0x00 0x16 0x00 0x00 0x01 0x7a 0x00 0x00 0x00 0x06 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x7f' Without this CL, the 1st two bytes were incorrect ~50% of the time. With the fix in place, verified that the first two bytes returned were always correct. Change-Id: Iff7620561eee463d599abfa6c07455c56bb5a5a6 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388785 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: make sure board resets when cr50 resetsVadim Bendebury2016-09-241-0/+10
| | | | | | | | | | | | | | | | | | | | cr50 should pretty much never reset, but when it does, for whatever reason, the device it is running on must reset as well. This patch makes every cr50 reset (be it command line induced, or caused by an exception) a hard reset, such that it re-initializes the R-box, which in turn causes reset of the entire platform. CQ-DEPEND=CL:361680 BRANCH=none BUG=chrome-os-partner:55948 TEST=verified that running commands like 'reset' or 'md 0xf0000' (which triggers an exception) causes the entire chromebook to reboot. Change-Id: Ifa160450b9b4c5ef25e512caf1ffdced9c97acd6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388007 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Lock console by default, with long timeoutBill Richardson2016-09-241-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This locks the Cr50 console by default, and makes the unlock process take the full 5 minutes unless the battery is removed. BUG=chrome-os-partner:57408 BRANCH=none TEST=make buildall; test on Gru & Reef Build the image with make buildall or make BOARD=cr50 Put it on Gru & Reef, and confirm that the console is locked, by running "lock" or "help". Try to unlock it with "lock off" and observe that you have to poke the power button for five minutes before it unlocks. Remove the battery and confirm that "lock off" now only requires a single power button press to take effect. Build the image with CR50_DEV=1 make BOARD=cr50 and now the behavior is back to the way it was before this CL. Change-Id: I9f2cc67a1dd63f260221a8711a8591070018be3b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/389238 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Unlock console quickly when battery is unpluggedBill Richardson2016-09-241-25/+56
| | | | | | | | | | | | | | | | | | | | | | The assumption is that removing the cover and disconnecting the battery is sufficiently obvious and time-consuming that it's not necessary to sit there poking the power button repeatedly. We still erase the NVMEM completely before unlocking, of course. BUG=chrome-os-partner:55322 BRANCH=none TEST=make buildall; test on Gru Toggle the Cr50 console with "lock on", then "lock off". Confirm that the 5-minute process only requires one poke when the battery cable is disconnected. Also confirm that both ways abort if you don't press the button at all. Change-Id: Iaa0f5eb102b914c95f3a34002438cbe80affcfb5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388879 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Clear NVMEM before unlocking the consoleBill Richardson2016-09-244-11/+50
| | | | | | | | | | | | | | | | | | | | | | | | The Cr50 console provides access to all sorts of dangerous commands. To protect user secrets, we must erase the persistent storage before unlocking the console. Note that this will not powerwash the AP, leaving you with the impression that you've just forgotten your password. You'll have to manually powerwash (Ctrl+Alt+Shift+R) afterwards. That will be addressed in a future CL. BUG=chrome-os-partner:55728 BRANCH=none TEST=make buildall, test on Gru Lock the console if it's not already ("lock enable"), then unlock it with "lock disable". Confirm that the NVMEM region is erased following a successful unlock process. Change-Id: Iebcd69c9f757f5ab5d496218f065197d3f1f746c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382666 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Change "unlock dance" to "unlock process"Bill Richardson2016-09-241-27/+29
| | | | | | | | | | | | | | | Just a variable & comment renaming. No functional changes. BUG=none BRANCH=none TEST=make buildall; test on Gru At the console, try "lock on", "lock off". It works the same. Change-Id: I65381d5550f68855be8d7961abbaa117dc97184b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/389237 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Add mostly-synchronous tpm_reset() function.Bill Richardson2016-09-245-11/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reset the TPM task, we send it an event so that it will reset only when it's not busy doing actual TPM stuff that might fiddle with the stack or shared memory. But that means that we can't always know when the task finally gets around to resetting itself. This CL adds a tpm_reset() function that blocks until the reset actually occurs. Obviously it can't do that if it's being called in interrupt context or from the TPM task itself, but otherwise it does. BUG=chrome-os-partner:52366 BRANCH=none CQ-DEPEND=CL:361680 TEST=make buildall, test on Gru, manual tests In addition to the normal rebooting, logging in/out, and so forth. I added a temporary console command to call tpm_reset() and scattered a bunch of ccprintfs around it. When called due to SYS_RST_L, it didn't block. When invoked with the console command, it did. Change-Id: I51e8b1299dbdcd1a12273cf48a890e93ed32a8c8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388125 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* anx74xx: fix hard reset issue.Shaoliang Wang2016-09-242-81/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1.ANX3429 have CC Rx buffer, when the partner sent one message,ANX3429 received this message into Rx buffer and triggered an interrupt to inform (TCPM), at this moment Reef sends a CC message before reading CC Rx buffer. After Reef sends this CC message successfully, it receives the message the partner sent. So (TCPM) sees an unexpected message was received, that`s why sends out hard reset. Root cause: ANX3429 use a normal R/W register as a interrupt status register. Between EC read interrupt status and clear interrupt status, if ANX3429 change interrupt status, it causes interrupt status is incorrect on EC side. Solution: ANX3429 FW use two normal R/W registers for interrupt status reg, one is for FW interrupt status,other is for EC control register. Note: Since cc messages conflict between TCPM and the Partner,ANX3429 shall discard the TCPM message, (TCPM) sometimes send soft reset depend on the discarded message type. 2. Sometimes TCPM (Reef) does not response GoodCRC for a received mesg. Root Cause: Reef send message conflict with ANX3429 send auto GoodCRC. Solution: This is fixed in the 1.5 ANX 3429 firmware. BUG=chrome-os-partner:53936 BRANCH=none TEST=On Reef tested with ANX3429 FW v1.5, did not see HARD RST on ec log with Zinger. Change-Id: I81da95433e7a0cc71e7ed121b925afccbcd84b06 Signed-off-by: Swang <swang@analogixsemi.com> Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/381014 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: reset only the TPM state on SYS_RST_LRandall Spangler2016-09-248-4/+76
| | | | | | | | | | | | | | | | | | | | | | Rather than doing a full cr50 reset when the system reset SYS_RST_L is asserted, just reset the state of the TPM task and library. Re-clear .bss for those modules, then re-initialize. BRANCH=none BUG=chrome-os-partner:52366 CQ-DEPEND=CL:366792 TEST=make buildall; test on Gru Trigger a SYS_RST_L by using the AP's reboot command, power off/on, log in/out/in. See that the Cr50 does not reboot and the firmware and userspace are still happy about the TPM. Change-Id: I32cd2bb72316f68c74db77a20a8d09112b402d4b Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361680
* npcx: gpio: Remove DEBUG_GPIO to make gpio_interrupt reentrantShawn Nematbakhsh2016-09-232-5/+0
| | | | | | | | | | | | | | | | | | | | GPIO interrupt priority levels can vary (notably, SHI CS interrupt is higher) so gpio_interrupt must be reentrant. BUG=chrome-os-partner:57434 BRANCH=Kevin TEST=Stress test on kevin 'pd 1 reset' with OEM charger attached, verify pdcmd task never gets wedged with TCPC ALERT stuck low. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If853b80ebcef622480389a7cc94e851de0f8bb20 Reviewed-on: https://chromium-review.googlesource.com/388745 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 011da7eb51c10a8e108bae0e489ff3ddc848ee33) Reviewed-on: https://chromium-review.googlesource.com/388749 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpm: anx74xx: Initialize regs for proper CC cye diagramShawn Nematbakhsh2016-09-232-2/+23
| | | | | | | | | | | | | | BUG=chrome-os-partner:56788 BRANCH=None TEST=Verify CC eye diagram looks better. Change-Id: I4880e81b0a4737a303027513e77c9a66845472e2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380352 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Enable Host command that limits external charger voltage/currentShamile Khan2016-09-231-0/+1
| | | | | | | | | | | | | | This command will be used to perform power validation. BUG=none BRANCH=none TEST=ectool extpwrlimit command can be used to set the max voltage/current drawn from external charger. Change-Id: Ic258954c1e3a714be7f648e77234dab594227ce0 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/388843 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Selectively filter WDT reset in reset_flagsMulin Chao2016-09-231-13/+21
| | | | | | | | | | | | | | | | | | | | | | NPCX reboots by triggering the watchdog which in turn causes the watchdog reset flag to be set as one of the system-wide reset_flags. However, other software can confuse the presence of the watchdog reset flag as a panic. This patch selectively sets the watchdog reset flag only if we're not explicitly doing a soft or hard reset or waking from hibernate. Patch created by Mulin Chao <mlchao@nuvoton.com> BUG=chrome-os-partner:56594 BRANCH=none TEST=panic reset no longer observed Change-Id: I016b59ffda4f6334cf41e196960edcbb87f6c049 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* kevin / gru: Use FW register for bd99955 resetShawn Nematbakhsh2016-09-231-7/+2
| | | | | | | | | | | | | | | | | | | | Use the FW reset register rather than the physical reset pin for bd99955 power-on reset to avoid bad side effects during reset. BUG=chrome-os-partner:57671 BRANCH=Kevin TEST=Manual on kevin, do EC cold reset w/ 15V attached to port 0, peripheral attached to port 1. Verify port 1 stays at <= 5V. Change-Id: If90d754bf6256a50901132de0b2ccde69aec2ebe Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388757 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 80291c05a6e96d0042969980ab09b2549cb44a75) Reviewed-on: https://chromium-review.googlesource.com/388748 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: I2CS: Set INT_AP_L as in input when the AP is offScott2016-09-231-0/+25
| | | | | | | | | | | | | | | | | | | | | | | INT_AP_L is used as a sync trigger to the host during i2cs transactions. This signal is nominally set high and pulled up to 1.8V. However, when the AP is off, this line won't be pulled up which would lead to excessive power draw by the Cr50 if this signal remains driven high. Added a change to set this signal as an input while the AP is powered off. When the AP powers back up, it's changed back to an input and driven high which is the default level. BRANCH=none BUG=chrome-os-partner:57733 TEST=manual Change-Id: I12f175a7899eff6b90acb5a82282e526db3c1b9f Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388799 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* power: common: Print RTC when changing states.Aseda Aboagye2016-09-231-0/+3
| | | | | | | | | | | | | | | | | | In order to help correlate EC logs with those from the kernel, it was suggested that the EC could periodically print the RTC time. This commit prints out the RTC time when changing power states. BUG=chrome-os-partner:57731 BRANCH=gru TEST=Build and flash kevin. Boot system up and suspend. Verify that RTC times are logged to the EC console. Change-Id: Ia1ee1ec88c6733f863a703fb3f841ab74b80fcb9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/388802 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Print RTC when resetting chipset.Aseda Aboagye2016-09-231-0/+3
| | | | | | | | | | | | | | | | | | In order to help correlate EC logs with those from the kernel, it was suggested that the EC could periodically print the RTC time. This commit prints out the RTC time when a chipset reset is requested. BUG=chrome-os-partner:57731 BRANCH=gru TEST=Build and flash kevin. Trigger watchdog from kernel and verify that RTC time is printed when the chipset is reset. Change-Id: Idc9a815c3337f720d41d16e0d844b4c1ea6728d8 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/388857 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* system: Add print_system_rtc().Aseda Aboagye2016-09-233-8/+30
| | | | | | | | | | | | | | | | | This commit adds a function that allows the real-time clock to be printed on the EC console. This could be helpful in trying to correlate events between the EC's log and the kernel's. BUG=chrome-os-partner:57731 BRANCH=gru TEST=make -j buildall Change-Id: I5e20692a173bddea3dc5c20cc0f2061cc170ce7d Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/388856 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* i2c: Add i2ctest console commandVijay Hiremath2016-09-2324-4/+469
| | | | | | | | | | | | | | | | | | Added i2ctest console command to test the reliability of the I2C. By reading/writing to the known registers this tests provides the number of successful read and writes. BUG=chrome-os-partner:57487 TEST=Enabled the i2ctest config on Reef and tested the i2c read/writes. BRANCH=none Change-Id: I9e27ff96f2b85422933bc590d112a083990e2dfb Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/290427 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: wake from deep sleep on rising edge of AP UARTMary Ruthven2016-09-231-0/+8
| | | | | | | | | | | | | | | The AP UART is used to detect if the device is in s0. When it is cr50 should not be in deep sleep for any reason. This change makes DIOA5 a wake pin before entering deep sleep. BUG=chrome-os-partner:56100 BRANCH=none TEST=make buildall Change-Id: Icb57824c0ca1421f5f508fce7cf5609010b91e32 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388793 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* kevin / gru: Make AP_OVERTEMP assertion print less scaryShawn Nematbakhsh2016-09-231-4/+4
| | | | | | | | | | | | | | | | | | | AP_OVERTEMP is asserted for various reasons by the host to bring itself down, so make that clear. Also shorten some misc. prints to save RAM. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ia8d15f421bd3f34aeeeb2251fbfd5d7cd3f7c081 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/386681 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit dbea6711a3cedbd9865022d2079b297bd6c20852) Reviewed-on: https://chromium-review.googlesource.com/387626 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* pi2usb9281: Prevent race condition in RMW control registerVictor Prupis2016-09-231-25/+69
| | | | | | | | | | | | | | | | Added unlocked versions of register access, modified RMW functions to use unlocked versions and made them locked themselves. BRANCH=master BUG=chrome-os-partner:49182 TEST=DUT boots successfully Change-Id: Ifd16abc349cc731aeed78b12989595214e65cea2 Signed-off-by: Victor Prupis <vprupis@google.com> Reviewed-on: https://chromium-review.googlesource.com/377151 Commit-Ready: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: use RXILVL to trigger fewer UART RXINTsMary Ruthven2016-09-233-10/+40
| | | | | | | | | | | | | | | | | | | | | | | | This change sets UART_FIFO_RXILVL to 3 for the AP and EC UART. With this change RXINT will only be triggered when 4 characters are received instead of for every character. The change also flushes the RX FIFO whenever console input is received through usb make sure to the user can see their input as they are typing. BUG=none BRANCH=none TEST=run taskinfo after the system finishes booting. Before Change the IRQ count for 181 should be around 20000. After the change it should be around 5000. Use the AP and EC console over USB and verify there is no noticeable change in their usability. Change-Id: I134ea0d2bc254038dad6c341b94f822adb90c000 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/387175 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* anx74xx: remove pd role control from init codeKevin K Wong2016-09-231-3/+0
| | | | | | | | | | | | BUG=chrome-os-partner:54332 BRANCH=none TEST=verify only zinger is detected in sink mode (G3/S5), and both zinger and hoho is detected in dual role mode (S0). Change-Id: Ifce0009908acc4b1849723ce807ca1b4c8e26020 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/387260 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Allow forced/manual hibernation on ACVijay Hiremath2016-09-231-3/+0
| | | | | | | | | | | | | | | | | | Allow hibernation on AC for hibernate console commands and hardware key sequence [ALT + VolumeUp + H]. BUG=chrome-os-partner:57724 BRANCH=none TEST='hibernate' console command & hardware key sequence can successfully hibernate the system on AC. Change-Id: Idfcc37620a712faca4b48a680ec9a7903c26ed88 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/388591 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* flash: Add command to get SPI flash chip infoRandall Spangler2016-09-237-35/+181
| | | | | | | | | | | | | | | | | | | Previously, there was no way to identify which flash chip was used by the EC, for ECs using an external SPI flash. Now, 'ectool flashinfo' will print more information about the SPI flash chip in these cases. BUG=chrome-os-partner:56765 BRANCH=any EC with MEC1322 or NPCX still going through factory TEST=define CONFIG_HOSTCMD_FLASH_SPI_INFO, then 'ectool flashspiinfo' on samus indicates no SPI flash info, and prints additional info on chell and kevin. Without the config defined, all platforms report no spi flash info. CQ-DEPEND=CL:386368 Change-Id: I3c162f7ad12ed4b30ab951c03f24476683382114 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385702 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Fix FAFT failure for firmware_ECUsbPortsDivya Sasidharan2016-09-233-5/+5
| | | | | | | | | | | | | | | | | Modify USB enable GPIO name to comply with FAFT test. It uses this name format USB%d_ENABLE to power on/off all the USB ports. BRANCH=none BUG=none TEST=on Reef FAFT test firmware_ECUsbPorts passes Change-Id: I9b3b5d1668acfca5505dcff6708800f409555040 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/386854 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Add gpio input for platform reset (plt_rst_l)Scott2016-09-233-4/+67
| | | | | | | | | | | | | | | | | | | | | | | For TPM operation with Intel chipset APs, the signal PLT_RST_L needs to trigger a TPM reset. For current Reef boards, this signal is connected to DIOA13. The next version will have it on DIOM3. This CL adds support for platform reset connected on DIOA13 and uses a new board property so that it doesn't affect Kevin/Gru. BRANCH=none BUG=chrome-os-partner:55115 TEST=manual Used H1 dev board configured as Reef. Created high to low transisition on to verify that platform reset was detected. Tested on Kevin to ensure that resets were not occurring. Change-Id: I58f02b7ffa644a9197f4303ae6e640df181040bd Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380336 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kevin: gru: Reset charger before initializing it.Aseda Aboagye2016-09-231-0/+26
| | | | | | | | | | | | | | | | | | | | | | | The reset line to the charger IC isn't hooked up to the cold_reset circuitry. This commit makes the EC reset the charger at init time. BUG=chrome-os-partner:57524 BRANCH=gru TEST=Enable power save mode. Toggle cold reset. Verify that power save mode is still enabled. Flash kevin with this patch. Verify that power save mode is disabled. TEST=Enable power save mode, reboot, verify power save mode is disabled. TEST=Enter G3. Enter hibernate. Insert zinger and verify that EC wakes up. Repeat 20 times. TEST=Verify system powers successfully with no battery, and wakes successfully from battery cut-off. Change-Id: Ib1362aefc71056e7c2b212a4fbdd6f979c57e20f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/384320 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/npcx: Close LPC window before sysjumpFurquan Shaikh2016-09-231-0/+12
| | | | | | | | | | | | | | | | | | Before performing a sysjump, ensure that: 1. LPC interrupts are disabled : Ensures interrupts are not taken until next enable. 2. LPC window is closed by writing 0xfffffff8 to window base addresses: Prevents any memory corruption by host. BUG=chrome-os-partner:57642 BRANCH=None TEST=Verfied that LPC communication works after sysjump to RW. Change-Id: I7b7826b2544f1c94cfa9c96b6ac82bc3517b1820 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388755 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* chip/npcx: Fix interrupt enabling during lpc_initFurquan Shaikh2016-09-231-12/+9
| | | | | | | | | | | | | | | | | | 1. interrupt enabling should be the last thing done when lpc_init completes required intialization 2. memset to 0 of static uninitialized variables is not required. Remove that. BUG=chrome-os-partner:57642 BRANCH=None TEST=Verified that LPC communication is fine after sysjump to RW. Change-Id: Ib8891dccf2b301590ebca41b75680d954d88a4d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388752 Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* usb: power_smart: Allow CONFIG_USB_PORT_POWER_SMART_PORT_COUNT < 2Shawn Nematbakhsh2016-09-221-2/+8
| | | | | | | | | | | | | | | | Don't require GPIO_USB2_ENABLE to be defined if we have only one port. BUG=None TEST=Redefine CONFIG_USB_PORT_POWER_SMART_PORT_COUNT to 1 for reef, remove GPIO_USB2_ENABLE definition, verify build is successful. BRANCH=None Change-Id: I5bfbee48ceabd87bbbd45cb120fda320d5eb1897 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/387926 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: notify chipset hooks when the AP state changesMary Ruthven2016-09-224-79/+34
| | | | | | | | | | | | | | | | | | | | | Cr50 monitors UART1 RX to sense the state of the AP. This signal can be used to tell if it is in S0. If the signal is pulled up then the AP is on. If it is not pulled up then the AP is not in S0. This change notifies HOOK_CHIPSET_SUSPEND when UART1 RX is not pulled up, and then notifies HOOK_CHIPSET_RESUME when the signal is high again. The AP usb can be disabled during suspend, so this change changes the hook that triggers disabling the AP usb to be attached to HOOK_CHIPSET_SUSPEND instead of HOOK_CHIPSET_RESUME. BUG=chrome-os-partner:55747 BRANCH=none TEST=buildall Change-Id: I47fb38a4bbcd72424ec2535d61e87f820cf1bcd7 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383978 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Revert "kevin: bd99955: Enable power save mode."Shawn N2016-09-221-1/+0
| | | | | | | | | | | | This reverts commit 0183a4f784194d2ab23467fb31c8a50e7503f1c0. See crosbug.com/p/57671. Change-Id: Ib0561352b1376da63cf4e3cbc593eece63a139c7 Reviewed-on: https://chromium-review.googlesource.com/388090 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* kevin: Fix EC watchdog on power-down after sysjumpShawn Nematbakhsh2016-09-211-0/+15
| | | | | | | | | | | | | | | | | | | If the AP requests a shutdown before HOOK_INIT completes, we may yank our SPI pins before motion sense-related SPI sensor init has completed. BUG=chrome-os-partner:57518 BRANCH=Kevin TEST=Cold reset EC, verify EC doesn't watchdog. Change-Id: Ie8196fc1f6f52e119860378b001bf6037e7d5239 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/386445 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 0a17e821524d1ef66ac878e5573abf80cb440746) Reviewed-on: https://chromium-review.googlesource.com/387627 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* BD9995X: Rename common code of BD99955 and BD99956 as BD9995XVijay Hiremath2016-09-2118-752/+762
| | | | | | | | | | | | | | | | | | Except the CHIP_ID and charger name code is common between BD99955 and BD99956. Hence renamed the code to BD9995X so that valid output is printed from console commands. BUG=chrome-os-partner:57519 BRANCH=none TEST=Manually tested on Reef. 'charger' console command prints charger name as 'bd99956' Change-Id: I3c995757941bcc5a6a8026dd807d76a7a47c9911 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/387119 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* system: Add console print for reboot-on-ap-shutdownShawn Nematbakhsh2016-09-211-0/+3
| | | | | | | | | | | | | | | | | | | | | If the EC suddenly resets due to a reboot-on-ap-shutdown host command, it's often not obvious why, so add a print. BUG=None TEST=Trigger cold reboot-on-ap-shutdown, verify print is seen on console. BRANCH=Kevin Change-Id: Iada34c9575462e687ffc6267b1ffead394b72bfe Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/386264 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit ab6f29a02bf36cdcca309b304a07006bebec01e9) Reviewed-on: https://chromium-review.googlesource.com/387628 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charger v2: Don't set charger current limit if capability is unknownShawn Nematbakhsh2016-09-215-15/+21
| | | | | | | | | | | | | | | | | | If charge_manager has not decided on a current limit, don't set a minimum current limit, since we may brown-out in the no / low-battery case. BUG=chrome-os-partner:56139 BRANCH=None TEST=Manual on kevin, attach cut-off battery, attach OEM charger, verify system doesn't brown-out due to OC. Change-Id: Id53eb32c4a8ac9c6d9a0d3f1d700f089a50fcb0f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/386793 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: shi: Clear EOR bit at start of legit transactionShawn Nematbakhsh2016-09-211-0/+6
| | | | | | | | | | | | | | | | | | | | Prevent EOR from cascading from one failed transaction to the next by explicitly clearing it when CS is asserted. BUG=chrome-os-partner:57563 BRANCH=Kevin TEST=Package new EC image into recovery installer, verify recovery completes without failure. Change-Id: I44112f81cb712bb1e93fc10d2aff58f527e7a0fe Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/387236 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> (cherry picked from commit 50fc635fc8335df767e209488493d25e6548c641) Reviewed-on: https://chromium-review.googlesource.com/387625 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: lock i2c port before checking if the port is busyKevin K Wong2016-09-211-4/+5
| | | | | | | | | | | | | | | since i2c port can be accessed by other hook events, the port should be locked first. BUG=none BRANCH=none TEST=i2cscan on reef returns no error and detects all devices. Change-Id: I848496e61b5d8cf513d9f9579e86846d652101d3 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/387217 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* ALS: OPT3001: Return appropriate error valueVijay Hiremath2016-09-211-7/+7
| | | | | | | | | | | | | | | | | | | Return appropriate error value for I2C errors and data verification errors. BUG=chrome-os-partner:57512 BRANCH=none TEST=Manually tested on Reef, ALS data changes when surrounding brightness is changed. Change-Id: I17b5bd10da5fa5cc82fdff10337ae893146c70ee Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/386397 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Print tcpc firmware versionDivya Sasidharan2016-09-218-0/+46
| | | | | | | | | | | | | | BUG=chrome-os-partner:56866 BRANCH=master TEST=prints firmware version at boot up;make buildall -j Change-Id: Idb067186924e6706ccfc69a64f2febd61f396074 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/380317 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpm: anx74xx: fix wrong clear CABLE_DET bit in 0x50:43 register.Tang Zhentian12016-09-211-10/+14
| | | | | | | | | | | | | BUG=None TEST=Verify cable detect is correct. BRANCH=None Change-Id: I6eb7c6cd979120835f89bbb68116ddbc03813f3b Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com> Reviewed-on: https://chromium-review.googlesource.com/382868 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* it83xx: EC sleep mode for system hibernateDino Li2016-09-217-17/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The typical power consumption in sleep mode is 65uA. IT83xx uses deep doze mode for low power idle task. The typical power consumption in this state is 280uA (depends on EC tasks, it should be more) and the wake up time is in microsecond. We are using deep doze mode for low power idle task instead of sleep mode is because the wake up time will be 6ms more. While in system hibernate (EC sleep mode), EC won't wake up frequently so we can keep the power consumption at 65uA. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=- hibernate 0 [1|999999] - hibernate [1|5|10|600] - hibernate then press power button. - hibernate then lid open. Change-Id: I94884c010264f01ede4950c6bb1b0a444d7b1e6d Reviewed-on: https://chromium-review.googlesource.com/383332 Commit-Ready: Dino Li <dino0303@gmail.com> Tested-by: Dino Li <dino0303@gmail.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Remove private-cr51 from version stringBill Richardson2016-09-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We no longer depend on this directory, so there's no need to include its sha1sum in the version string. BUG=chrome-os-partner:54101 BRANCH=none TEST=make buildall; try on Cr50 hardware Before > version Chip: g cr50 B2 Board: 0 RO_A: * 0.0.9/0088a3eb RO_B: 0.0.3/8fe06b9e RW_A: * 0.0.6/DEV/cr50_v1.1.5333-cca986c RW_B: 0.0.6/DEV/cr50_v1.1.5334-115b338 Build: 0.0.6/DEV/cr50_v1.1.5333-cca986c private-cr51:v0.0.87-24457f2 tpm2:v0.0.264-5e5aaa3 cryptoc:v0.0.4-5319e83 2016-09-16 21:59:31 wfrichar@wintermute.mt > After > version Chip: g cr50 B2 Board: 0 RO_A: * 0.0.9/0088a3eb RO_B: 0.0.3/8fe06b9e RW_A: 0.0.6/DEV/cr50_v1.1.5333-cca986c RW_B: * 0.0.6/DEV/cr50_v1.1.5334-36b2cee Build: 0.0.6/DEV/cr50_v1.1.5334-36b2cee tpm2:v0.0.264-5e5aaa3 cryptoc:v0.0.4-5319e83 2016-09-19 17:48:17 wfrichar@wintermute.mtv.corp.google.com > Change-Id: I785dff86e6b970219da87c8674f2a324fa074987 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/387238 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: make device state detect level triggeredMary Ruthven2016-09-211-3/+3
| | | | | | | | | | | | | | | | | The interrupts on all of the gpios detecting if the device is on were edge triggered. If the rising edge happened in between when the gpio level was read and when the interrupt was enabled, then the device state could be falsely detected as off for a short period of time. This change changes them to GPIO_INT_HIGH. BUG=none BRANCH=none TEST=buildall Change-Id: I9aa3cff14047cf4f6473c32f2cdc4724afca3414 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385164 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: remove unused detect_off interruptMary Ruthven2016-09-215-68/+24
| | | | | | | | | | | | | | | | The interrupts to detect when the falling edge on the UART signals are currently disabled and never reenabled. Power off is detected by polling and not through interrupts. This change removes all of those falling edge interrupts. BUG=none BRANCH=none TEST=cr50 can detect when the EC, AP, and Servo are off or on Change-Id: I0fd8a0d970f3235b26af6b90dd395ea7c75e0c17 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385192 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* npcx: Fixed bug i2c sometime cannot generates NACK in Read Byte protocolMulin Chao2016-09-211-3/+5
| | | | | | | | | | | | | | | | | | | | | | | We should clear STASTR to release SCL only after NACK/STOP bits are set. If an interrupt which priority is higher than i2c's issues at this moment, i2c hardware might not generate NACK since SCL is already released by clearing stall's pending bit. Modified sources: 1. i2c.c: Fixed bug i2c sometime cannot generate NACK during Read Byte. BRANCH=none BUG=chrome-os-partner:34346,chrome-os-partner:57452 TEST=make buildall; passed "while(1); do; ectool i2cread 8 0 0x50 0x44; done;" on reef. Change-Id: I68ee5bf3d703cbe4fceefcfcc9afab9cb14bc2dc Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/386586 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: Free more RAM spaceShawn Nematbakhsh2016-09-211-0/+2
| | | | | | | | | | | | | | | | | | Remove lesser-used console commands. BRANCH=None TEST=`make buildall -j` BUG=None Change-Id: I0aa48e792d89a2835833790383e1d0469c9487a0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/386451 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 68fadf7e0e0b0eb8c6f1ea506cd604e1eafbb9c8) Reviewed-on: https://chromium-review.googlesource.com/386368 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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