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* BD9995X: Disable input to port when sourcingVijay Hiremath2016-10-2712-101/+82
| | | | | | | | | | | | | | | | | | POR has both VCC & VBUS enabled. If the port is sourcing VBUS it will also act as sync and AC_OK pin gets enabled. Hence disable the input to the port when sourcing. BUG=chrome-os-partner:59020 BRANCH=none TEST=Manually verified on Reef. Connected HoHo and AC_OK is not enabled. Change-Id: Ic51b81f45759d7dddb2c9744d1c24dbafd1e1293 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/404168 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* gru/kevin: turn on flags to save code sizephilipchen2016-10-271-0/+8
| | | | | | | | | | | | | | | | Turn on CONFIG_HOSTCMD_ALIGNED and CONFIG_COMMON_GPIO_SHORTNAMES to squeeze more space for the upcoming sensor code. BUG=chrome-os-partner:59084 BRANCH=gru, kevin TEST=Check the map to confirm the size reduction Change-Id: I7a9ca8fccf6d57a797c391dc76cacb0b929e14df Reviewed-on: https://chromium-review.googlesource.com/403485 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* extra/usb_updater: don't use uninitialize variablesAaron Durbin2016-10-271-1/+1
| | | | | | | | | | | | | | | The 'transferred_sections' variable wasn't initialized in all paths. Fix that. BUG=chrome-os-partner:58794 BRANCH=None TEST=Built. Change-Id: If82ef1274d6a931e0cd193f276f34bfcac1fb1c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/404548 Tested-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
* usb_updater: report running H1 firmwareAaron Durbin2016-10-271-22/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a command line option which allows to retrieve version currently running on the cr50 device. BRANCH=none BUG=chrome-os-partner:58794 TEST=run the following command: $ sudo ./extra/usb_updater/usb_updater -f open_device 18d1:5014 found interface 4 endpoint 5, chunk_len 64 READY ------- start Target running protocol version 5 Offsets: backup RO at 0, backup RW at 0x4000 Keyids: RO 0x3716ee6b, RW 0xb93d6539 Current versions: RO 0.0.9 RW 0.0.8 Change-Id: Ia34f455d3ca826a24992adf123a07865dccb1d57 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400418 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* kevin: Add bugs to TODOs.Aseda Aboagye2016-10-272-2/+5
| | | | | | | | | | | | | | | | Found some TODOs and filed bugs for them. BUG=None BRANCH=gru TEST=make -j buildall Change-Id: I3aa4350383f1fe9954f2dd20811c2256d0940a48 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/404112 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* Adding offsetof macro to stddef.h.Johnnie Chan2016-10-261-0/+9
| | | | | | | | | | | | | | | | | This duplicates the macro definition that exists in compile_time_macros.h. Adding it is okay since they are both guarded by a #ifndef #endif check. This is needed by code being pulled in from google3 which expects the macro to be defined in the standard place. BUG=none BRANCH=none TEST=make BOARD=haven_dev Change-Id: Ibddefcd8bbfe0d121b3ce65950ce979e65778761 Reviewed-on: https://chromium-review.googlesource.com/403573 Commit-Ready: Johnnie Chan <johnniec@google.com> Tested-by: Johnnie Chan <johnniec@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: provide platform API for fw version capabilityVadim Bendebury2016-10-261-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tpm is supposed to report its firmware version when TPM_PT_FIRMWARE_VERSION_1 and TPM_PT_FIRMWARE_VERSION_2 capabilities are requested. This patch retrieves form the build info string SHA1s of the ec and tpm2 repositories and returns them to the caller. BRANCH=none BUG=chrome-os-partner:58177 TEST=with the appropriate tpm2 source tree changes the ec and tpm SHA1s are now reported: localhost ~ # tpm_version TPM 2.0 Version Info: Chip Version: 2.0.0.0 .... Firmware Version: 0a92ec7c01b9c924 (the first half is the zero prepended 7 characters of the ec SHA1, and the second half is the zero prepended 7 characters of the tpm2 SHA1). Change-Id: I01e4fffdafbbdc4668342ea511ca9c4a555e20a9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403115 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* eve: Add new boardDuncan Laurie2016-10-268-0/+1487
| | | | | | | | | | | | | | | | | Add support for eve P0 board with: - chip: npcx - pmic: bd999992GW - charger: bd99956 - tcpc: 2x anx3429 BUG=chrome-os-partner:58666 BRANCH=none TEST=build and boot on eve board Change-Id: I69ff246e9f8197d5d50241e6a8fa4796f4c9bfda Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400638
* Cr50: i2cs: Re-enable sleep after every interruptScott2016-10-262-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, sleep was being reenabled only after tpm fifo reads as that would typcially be near the end of a host driven TPM command. However, in the case the host reads or writes to the STS register, then sleep would not be re-enabled. Moved the re-enable point to at the end of every i2cs interrupt. Since sleep is delayed by 1 second prior to being reenabled then Cr50 will not go to sleep in the middle of TPM command since the host is either writing or reading STS at a much faster rate when a TPM command is being executed. BRANCH=none BUG=chrome-os-partner:40397 TEST=manual Added a debug counter in idle.c and shortened sleep delays from 3 minutes to 5 seconds. Unplugged suzyq and verified that when reconnected, the counter was incrementing to verify that Reef would go to sleep. Also verified that TPM worked successfully and kernel was launched. Change-Id: I03ad33ed3591bbba24b5c56445c06d0e11368019 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/401808 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* task: Don't propagate TASK_EVENT_TIMER between between waitsShawn Nematbakhsh2016-10-265-6/+18
| | | | | | | | | | | | | | | | | | | | In __wait_evt(), if a timer expiration occurs after we read event status, before the timer is canceled, then TASK_EVENT_TIMER will be propagated to the next task wait, likely leading to premature timeout. Prevent this by clearing TASK_EVENT_TIMER after canceling our timer. BUG=chrome-os-partner:58658 BRANCH=gru TEST=Manual on gru, run 'pd # hard' for 12 hours with charger attached, verify no TCPC I2C read errors occur. Change-Id: Iac2f05a768b4ef29f82e7c3eb899f4c7dd5c3744 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400968 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: fix contract negotiation with dynamic PDOsVincent Palatin2016-10-264-9/+19
| | | | | | | | | | | | | | | | | | | | | When the board is using dynamic source PDOs, we need to ensure that we are checking the incoming sink power request against the right set of PDOs else we might reject a valid request (e.g. with high-power source, we need to check against the 3.0A limit if we only have one port connected). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=gru BUG=chrome-os-partner:56110 TEST=Connect Kevin to Caroline, ask Caroline to charge from the other side and see it negotiating successfully a 5V/3A contract. Change-Id: Ie1aa5746776be5946422bf07c08ae0f22faddd8c Reviewed-on: https://chromium-review.googlesource.com/403088 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: enable write protectMary Ruthven2016-10-261-2/+2
| | | | | | | | | | | | | | | | Enable write protect based on the type of image being built. Write protect will be enabled on production images and disabled on dev images. BUG=chrome-os-partner:49959 BUG=chrome-os-partner:55604 BUG=chrome-os-partner:58961 BRANCH=none TEST=verify wp is enabled unless the image is built with CR50_DEV=1 Change-Id: Ibcd7f35fb4b33142c94e59e8c103624fce4e0b10 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403308 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Snappy: Fix multi-func mode for USB PDBruce2016-10-261-2/+7
| | | | | | | | | | | | | | | | | Without this change the Alternate mode adapter with multi-function capablity would only be configured as DP instead of (DP + USB). BUG=None BRANCH=master TEST=make buildall Change-Id: I44d2b0ff56a8851b8104c4305b8f5826dcbe2107 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/401266 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Snappy: Enable low power idle modeBruce2016-10-261-1/+1
| | | | | | | | | | | | | BUG=None BRANCH=none TEST=make buildall Change-Id: I8c71f6916b17d36026d9f96c91391f397bbaef43 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/401245 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: espi: Fix SMI/SCI virtual wire handlingCHLin2016-10-262-2/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When GPIOC6/GPIO76 are not selected as SMI/SCI function(ie. selected as GPIO), the reading of SMIB/SCIB will be a fixed value. This means it cannot reflect the actul SMI/SCI status. As a reault, use SET_BIT/ CLEAR_BIT macro to toggle SMIB/SCIB is not feasible. Firmware should read the SMI/SCI status from VWEVSM(2) register before setting it. This CL defines some macros to achieve it. In the previous CL, SMI/SCI negative polarity is conditionally disabled. However, the negative polarity is not used in current firmware design. Set the SMI/SCI polarity as postive unconditionly by default. Modified drivers: 1. lpc.c: use macro NPCX_VW_SMI/NPCX_VW_SCI to generate Virtual wire. use SMI/SCI postive polarity uncontionally by default. 2. register.h : define macro to handle SMI/SCI virtual wire. BUG=chrome-os-partner:34346 BRANCH=none TEST=make buildall; try hostevent on Wheatley and check virtual wire signal is correct on logical analyzer. Change-Id: Id4a7748addeaa3b35f280ff29f6fcd8a08b9894b Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/400161 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* lpc: Add function for host reset without RCIN GPIODuncan Laurie2016-10-264-2/+46
| | | | | | | | | | | | | | | | | | | | | | | Prior x86 boards have had GPIO for toggling RCIN directly on the PCH, although many likely had HW-assisted methods as well. With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality software control over RCIN Virtual Wire is not available with the npcx EC, so the legacy LPC interface for pulsing KBRST must be used instead as this is the only way to generate RCIN. This method will likely vary on different EC chips, but for skylake it can just be abstracted into the LPC module. BUG=chrome-os-partner:58666 BRANCH=none TEST=successful 'apreset warm' on eve EC console Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400037 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add board callback before RSMRST# state changeDuncan Laurie2016-10-263-0/+29
| | | | | | | | | | | | | | | | | | | | | | This board function allows workarounds to be applied to a board after all power rails are up but before the AP is out of reset. Most workarounds for power sequencing can go in board init hooks, but for devices where the power sequencing is driven by external PMIC the EC may not get interrupts in time to handle workarounds. For x86 platforms and boards which support RSMRST# passthrough this board callback will allow workarounds to be applied despite the PMIC sequencing by ensuring that the function is executed before RSMRST# deassertion. BUG=chrome-os-partner:58666 BRANCH=none TEST=test IMVP8 workaround on multiple eve boards Change-Id: I0569494084000a4b1738ee18aafce5c96900dc4b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/402591 Reviewed-by: Shawn N <shawnn@chromium.org>
* amenia: remove mainboardAndrey Petrov2016-10-259-1771/+0
| | | | | | | | | | | | | | | Amenia is EOL. Remove mainboard. BUG=chrome-os-partner:57490 BRANCH=none TEST=none Change-Id: Idd453299df866c8ea6e4a4903d94bc26ff9150c6 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/392231 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* reef/pyro/elm/amenia/snappy: Remove false battery critical messageVijay Hiremath2016-10-255-18/+8
| | | | | | | | | | | | | | | | | | Till the charger task is initialized port is not set for the BD9995X users and a false battery critical message is printed. Removed the false message printed for BD9995X users to avoid confusion. BUG=chrome-os-partner:58972 BRANCH=none TEST=Manually tested on Reef. False battery critical message is not printed on the EC console. Change-Id: Iec8d0f354c4f6dc17efa9da8db38b125e57addab Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/402668 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: espi: Fix pltrst handler for chipset reset hookDuncan Laurie2016-10-251-14/+28
| | | | | | | | | | | | | | | | Enable the chipset_reset_hook by adding interrupt trigger on pltrst assertion and fix the compilation when built with CONFIG_CHIPSET_RESET_HOOK enabled. BUG=chrome-os-partner:58666 BRANCH=none TEST=build with CONFIG_ESPI and CONFIG_CHIPSET_RESET_HOOK Change-Id: I64eb7a1acc58c07beba0d28f94d95ef33d7220fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400035 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: lpc: Fix DP80CTL setting for eSPIDuncan Laurie2016-10-251-0/+4
| | | | | | | | | | | | | | The datasheet says DP80CTL[1] should be set when using eSPI. BUG=chrome-os-partner:58666 BRANCH=none TEST=boot with espi and see port80 values Change-Id: Ie46feacc50dc78b1f0bf5e4e131198708cd6ec89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400034 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: lpc: Fix SMI generationDuncan Laurie2016-10-251-1/+1
| | | | | | | | | | | | | | | | The check for whether or not to send an SMI needs to check the same status bit that it is using to indicate that it is going to send an SMI. The SMIE bit is enabled in lpc_init() so it is always set. BUG=chrome-os-partner:58666 BRANCH=none TEST=shutdown with lid close event at developer screen Change-Id: I9a0f34025c4fa11175fca7be34224ec680bffbef Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400033 Reviewed-by: Shawn N <shawnn@chromium.org>
* include: Add default state for ESPI and VW_SIGNALSDuncan Laurie2016-10-256-7/+13
| | | | | | | | | | | | | | Add the default undefined state for CONFIG_ESPI and rename CONFIG_VW_SIGNALS to CONFIG_ESPI_VW_SIGNALS. BUG=chrome-os-partner:58666 BRANCH=none TEST=pass presubmit checks Change-Id: I45242d545915c16bb46f751532a01ab937cee5f0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400032 Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: introduce a fixed endorsement seed & certsnagendra modadugu2016-10-251-20/+239
| | | | | | | | | | | | | | | | | | | | | | This change introduces a 'fixed' endorsement seed, and corresponding certificates. This fixed seed is used in the endorsement process when a production mode chip is running dev-signed firmware (or vice-versa). The fixed certificates are untrusted by production services, and are suitable for use in a development environment. BRANCH=none BUG=none TEST=build succeeds Change-Id: Ifad0b361413a10f88c4977b03033a30a750cd536 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/401634 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* chip/g/flash: Return error if flash command isn't recognizedMartin Roth2016-10-251-0/+2
| | | | | | | | | | | | | | | This fixes a build failure using gcc 5.3 where opcode and max_attempts are used before being initialized. BUG=None BRANCH=None TEST=Build all boards successfully. Change-Id: Ia7c4273f8812cca9f127fcd71101ce3a4e4ad4c7 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/370662 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Pyro: Fix multi-func mode for USB PDBruce2016-10-241-2/+7
| | | | | | | | | | | | | | | | | Without this change the Alternate mode adapter with multi-function capablity would only be configured as DP instead of (DP + USB). BUG=None BRANCH=master TEST=make buildall Change-Id: I85c8b52469dec6fc347c5cfe6a3b208bc765069e Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/401074 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Pyro: Enable low power idle modeBruce2016-10-241-1/+1
| | | | | | | | | | | | | BUG=None BRANCH=none TEST=make buildall Change-Id: If3ba1f57989d9c0f1027e8281a4ff6bddaac7dec Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/402108 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Pyro: Fix sensors order for devices with BM160 and LPC mode.Bruce2016-10-232-44/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the kernel reads sensor data via LPC, it expects the order to be: - ACCEL - ACCEL - GYRO (other sensors data are read through EC commands) BMI160 expects ACCEL, GYRO and MAG to be next to each other. Reorganize motion_sensor array to fit these 2 requirements: If BMI160 in the lid: - BASE_ACCEL - LID_ACCEL - LID_GYRO ... If BMI160 in the base: - LID_ACCEL - BASE_ACCEL - BASE_GRYO ... BUG=none BRANCH=none TEST=make buildall Change-Id: If89cf29d28b70e9a46dde8a3301a1942b3a1dd8b Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/401206 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Pyro: remove obsolete code for protoBruce2016-10-233-123/+0
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Change-Id: Idfa57dc6f06e0b3a42eca3f77279c60e615b6ae5 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/401222 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Pyro: Enable CONFIG_CMD_ACCEL_INFOBruce2016-10-231-0/+1
| | | | | | | | | | | | | | | Enable this EC console command for testing BUG=None BRANCH=master TEST=make buildall Change-Id: I95e3926bcc30f91ebb5174a055db98469b5a8b76 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/400983 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Pyro: Enable Host command that enables/disables Display BacklightBruce2016-10-231-0/+1
| | | | | | | | | | | | | | | This command will be used to perform power validation. BUG=none BRANCH=none TEST=make buildall Change-Id: I993438162871ceba3e45635db31e3b1bd5aae643 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/401084 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* stm32: make usb_iface_request externBrian Norris2016-10-211-1/+1
| | | | | | | | | | | | | | This isn't supposed to be static. And with CL:401421, we noticed that clang doesn't like this form. So fix this one too. BRANCH=none BUG=chromium:658436 TEST=build Change-Id: Ibd0c5724d5178c5ce8fc8c1b74382aeddd8f744d Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/402068 Reviewed-by: Shawn N <shawnn@chromium.org>
* Fixup usb_updater for reef/clangBrian Norris2016-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | clang doesn't like the array here: ec-utils-0.0.1-r3361: x86_64-cros-linux-gnu-clang -std=gnu99 -g -Wall -Werror -Wpointer-arith -Wcast-align -Wcast-qual -Wundef -Wsign-compare -Wredundant-decls -Wmissing-declarations -O0 -I/build/reef/usr/include/libusb-1.0 -I../../include -I../../board/cr50 -I ../../chip/g -I../../util usb_updater.c -lusb-1.0 -lcrypto -o usb_updater ec-utils-0.0.1-r3361: In file included from usb_updater.c:32: ec-utils-0.0.1-r3361: In file included from ../../include/usb_descriptor.h:14: ec-utils-0.0.1-r3361: ../../chip/g/usb_hw.h:29:14: error: tentative array definition assumed to have ec-utils-0.0.1-r3361: one element [-Werror] ec-utils-0.0.1-r3361: static int (*usb_iface_request[]) (struct usb_setup_packet *req); ec-utils-0.0.1-r3361: ^ ec-utils-0.0.1-r3361: 1 error generated. But it's willing to forgive if this is extern. It should be extern anyway. BRANCH=none BUG=chromium:658436 TEST=reef pre-cq passes (building ec-utils) Change-Id: I5b5f8eb8dcdc3340487b118b30469c8cee73e182 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/401421 Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: Enable low power idle modeVijay Hiremath2016-10-201-1/+1
| | | | | | | | | | | | | | | BUG=chrome-os-partner:56183 BRANCH=none TEST=Used dut-control command 'dut-control pp3300_ec_mw -r <n>' to measure the pp3300 rail and power in S3 dropped from ~9mW to ~5mW. Change-Id: I64b463351a6f191a94a41a31de9ee51ae6d9b7b4 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/400948 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Snappy: Create initial boardBruce2016-10-209-0/+2383
| | | | | | | | | | | | | | | Create initial snappy EC code, by copy from reef BUG=chrome-os-partner:58233 BRANCH=None TEST=make buildall Change-Id: Ie13491c07165988047d131404a0e759c0d40562a Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/401221 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* host_command_pd: pd_exchange_status: Fix first_exchange logicNicolas Boichat2016-10-201-1/+4
| | | | | | | | | | | | | | | | | | | The code clearly indends to sleep on the second time the loop is taken, but the variable first_exchange is reset to 1 inside the loop. If, for whatever reason, PD alert status cannot be cleared, the code will then loop forever, and lead to a watchdog reset. BRANCH=none BUG=chrome-os-partner:58750 TEST=Flash EC RO using ec_util Run fwupdatetest with charger unplugged for 10 iterations. Change-Id: I9e13f2523111853fdc5c45e75886c11f1c8006eb Reviewed-on: https://chromium-review.googlesource.com/401238 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* spi_flash_reg: Correct lengths for W25Q40/GD25LQ40David Hendricks2016-10-201-3/+3
| | | | | | | | | | | | | | | | | | | | | | The lengths were previously specified as end offsets and were thus off by 1. Fortunately it seems these chips were never used with an EC where we actually utilize this table. Still, it would be nice if we actually tested this on real hardware to check that there aren't any other silly errors. BUG=none BRANCH=none TEST=needs testing Signed off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I0a5315808c756797940436a10cd4f6df7313ab8c Reviewed-on: https://chromium-review.googlesource.com/400642 Commit-Ready: Dan Shi <dshi@google.com> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Support alignment for EC host command structuresRandall Spangler2016-10-197-430/+553
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The host command parameter and response buffers should be explicitly aligned by the LPC/SPI/I2C drivers. But the host command handlers don't know that, and the structs are all __packed, so the compiler generates horribly inefficient ARM Cortex-M code to cope with unaligned accesses. Add __ec_align{1,2,4} to force the param / response structs to be aligned. Use it in a few structs now which were straightforward to test. It should be added to more structs as space is needed, but that would make this change unwieldy to review and test. Add CONFIG_HOSTCMD_ALIGNED to enable the additional alignment. Currently, this is enabled only for LM4 and samus_pd, so that EC code can be tested without affecting other non-samus ToT development (none of which uses LM4). Fix the two handlers that weren't actually aligned (despite one of them having comments to the contrary). Also, add a CHROMIUM_EC define that can be used to determine if a file is being compiled for an EC target. We need that so that we only force structure alignment for EC binaries. On the AP side, buffers may not be aligned, so we should not force alignment. BUG=chromium:647727 BRANCH=none TEST=Flash samus and samus_pd. Boot samus and run a bunch of ectool commands (with and without --dev=1, so it tests both EC and PD). System boots and all commands return expected results. Change-Id: I4537d61a75cf087647e24281288392eb85f22eba Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/387126
* pd_task: print pd state nameKevin K Wong2016-10-193-18/+37
| | | | | | | | | | | | | | | | | | Shifted pd_task debug level by 1 so that debug level 1 will enable printing the pd state name. Added a CONFIG flag to remove ability to change debug_level during runtime and debug print level will be fixed. BUG=none BRANCH=none TEST=make buildall Change-Id: I545813bafa8084355cedc2d8334c3aec5a2b6739 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/339935 Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* reef: usb_pd_policy: Fix multi-func mode for USB PDDivya Sasidharan2016-10-191-3/+8
| | | | | | | | | | | | | | | | | | | Without this change the Alternate mode adapter with multi-function capablity would only be configured as DP instead of (DP + USB). BUG=chrome-os-partner:58670 BRANCH=master TEST=On Reef, with Dell dongle verified on both ports that USB 3.0 device and ethernet is working. Change-Id: I7a15a281306e29f589de2ef59da9c424f3f6710d Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/400080 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* polyberry: add initial board buildNick Sanders2016-10-186-0/+311
| | | | | | | | | | | | | This supports gpio initialization only. BUG=None TEST=Successfully checked console and available GPIO on sweetberry BRANCH=None Change-Id: Id50f66652b05c25a8c79ce2938fa161a944d93b8 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/399643 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Re-enable Google USBC peripheral FW updates.Todd Broch2016-10-185-5/+75
| | | | | | | | | | | | | | | Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=glados,gru,oak BUG=chrome-os-partner:57458 TEST=usbpd_GFU Change-Id: I5a6bfde742a5c698680f99f342b1696084fd002a Reviewed-on: https://chromium-review.googlesource.com/397862 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Benson Leung <bleung@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Added "stdbool.h" and definition of uint_least8_t to "stdint.h".Carl Hamilton2016-10-172-0/+15
| | | | | | | | | | | | | | | | | | | The two types added, bool and uint_least8_t, are needed by the nanopb common header file "pb.h". The file added and the file modified are EC versions of files that are normally provided by the compiler. This change follows the approach already take to provide our own, mimimalist versions of these files. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I892e25b14f7cbe3ecca6f60d6a2955d4d628e3a9 Reviewed-on: https://chromium-review.googlesource.com/398921 Commit-Ready: Carl Hamilton <carlh@chromium.org> Tested-by: Carl Hamilton <carlh@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* npcx: i2c: Remove needless controller state pre-checkShawn Nematbakhsh2016-10-171-9/+1
| | | | | | | | | | | | | | | | | | | | | We're now locking i2c at the controller (not port) level, so it's not necessary to check if a given controller is busy before doing an i2c transaction. BUG=None TEST=Manual on kevin, verify i2c is still functional. BRANCH=gru Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic0cda34f9a58c76083699990a0dc3e761bcdec4f Reviewed-on: https://chromium-review.googlesource.com/393107 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> (cherry picked from commit 7d2e2f565b79a035a270ca083af97c6a14983739) Reviewed-on: https://chromium-review.googlesource.com/396138 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: rk3399: Debounce PGOOD_SYS signalShawn Nematbakhsh2016-10-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | PGOOD_SYS may glitch for a period not to exceed 1ms. When PGOOD_SYS or PGOOD_AP are deasserted, wait for up to 100ms for both signals return before transitioning out of S0. BUG=chrome-os-partner:56822 BRANCH=gru TEST=Manual on kevin, boot device and verify it remains in S0 without spurious transitions to S3. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I95ccae54fc5939c835f00dc9b7cf88b9d0553c11 Reviewed-on: https://chromium-review.googlesource.com/393148 Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit b867d3fc9dea04ac65f5288fb99d3ed65c127644) Reviewed-on: https://chromium-review.googlesource.com/396139 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* lucid: Remove console history to save flash spaceShawn Nematbakhsh2016-10-171-0/+1
| | | | | | | | | | | | BUG=None TEST=`make BOARD=lucid` BRANCH=None Change-Id: If90479817fcb5a5c0027718395aaf318dd7b4fcb Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/399769 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org>
* pd: Initialize pd comms and dual role state from PD taskShawn Nematbakhsh2016-10-142-69/+86
| | | | | | | | | | | | | | | | | | | | Don't call into tcpm_*() functions from HOOKs since these functions may manipulate common sets of TCPC registers. BUG=chrome-os-partner:57691 BRANCH=gru TEST=On kevin, boot to S0, verify 5V is sourced to legacy peripheral. Drop to G3, verify role is back to sink and charging is functional. Back to S0, verify 5V is sourced. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9ade9de068589dce6995cda6b106217aa85aa793 Reviewed-on: https://chromium-review.googlesource.com/394809 (cherry picked from commit 18e9e3870722d57efd232bd7f0a0300003b46ad6) Reviewed-on: https://chromium-review.googlesource.com/396137 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Rename charge_temp_sensor_get_val() to charge_get_battery_temp()Vijay Hiremath2016-10-1416-16/+16
| | | | | | | | | | | | | | | | | charge_temp_sensor_get_val() is used to get the battery temperature value hence renamed it to charge_get_battery_temp(). BUG=none BRANCH=none TEST=make buildall -j Change-Id: I2b52cac57dcde12a6b7405e7d712240e278954e2 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/397962 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* servo_v4: support autodetect of CCDNick Sanders2016-10-142-5/+216
| | | | | | | | | | | | | | | This allows a servo_v4 to export case closed debugging automatically, if it detects that it's been plugged into a ccd device. BUG=chromium:571476 TEST=Connect to reef in both orientations. BRANCH=None Change-Id: I8e2781056b22e834132bc4bb839ef2763fa0b4b8 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/375359 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cts: Fix back-to-back buildDaisuke Nojiri2016-10-144-15/+16
| | | | | | | | | | | | | | | | | | | Currently eCTS suites share the same directory (e.g. build/stm32l476g -eval) to put build artifacts even though some files (e.g. board.c) compile differently suite to suite. So, if cts-i2c-stm32l476g-eval is built, followed by cts-gpio-stm32l476g-eval, build fails or produces incorrect binary. This patch makes eCTS create different directories for each suite. As a bonus, we can now builds eCTS suites in parallel. BUG=chromium:654549 BRANCH=none TEST=make buildall -j (with uncommitted change) Change-Id: I4abedc917787be5f79b97e0e50d0d08e01bd5f9d Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/398281
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