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* reef: Enable high current on type-A ports by defaultstabilize-8992.BVijay Hiremath2016-11-152-1/+2
| | | | | | | | | | | | | BUG=chrome-os-partner:59309 BRANCH=none TEST=Able to draw 1.5A from Type-A ports Change-Id: I9c598f77a542650edf15f407ec4a10d0e7e7465e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/411345 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Electro: modify battery cutoff commandRyan Zhang2016-11-141-16/+7
| | | | | | | | | | | | | | | Follow Banon's setting BUG=chrome-os-partner:59535 BRANCH=master TEST=`make -j buildall`, shipping mode works well. Change-Id: Idf4b253ddb86a82752fca0f872ddb9603dee256c Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/411023 Commit-Ready: Ryan Zhang <ryan.zhang.quanta@gmail.com> Tested-by: 志偉 黃 <David.Huang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* anx74xx: Fix typo in anx74xx_check_cc_type functionDivya Sasidharan2016-11-141-1/+1
| | | | | | | | | | | | | | | BRANCH=none BUG=none TEST=manual, On Reef connected hoho and made sure it is properly detected instead of as an accessory. Change-Id: I1c271a8c5c2800dd88bf0e63a7c7aa2e23551510 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/411382 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Electro: Support 360 Degree rotationRyan Zhang2016-11-141-3/+3
| | | | | | | | | | | | | | | | | Follow Cyan's & Glados's setting. BUG=chrome-os-partner:59536 BRANCH=master TEST=system can boot up normally. Change-Id: I6abfcef06e5b46cb974706b7472c73f00a644544 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/408497 Commit-Ready: Ryan Zhang <ryan.zhang.quanta@gmail.com> Tested-by: 志偉 黃 <David.Huang@quantatw.com> Reviewed-by: Mohammed Habibulla <moch@google.com> Reviewed-by: Vincent Wang <vwang@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: Stop disabling the AP/EC uart when ccd is disabledMary Ruthven2016-11-141-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This change removes the uart disable in rdd_disconnect. It used to be necessary because we used to disable device state detection in rdd_disconnect. Without device state detect we had to disable the AP and EC uart to make sure there were no interrupt storms. Now we keep device state detection running all the time. It handles enabling/disabling the AP and EC uart when it senses the RX signals aren't pulled up. UART is only enabled/disabled when cr50 detects that the AP or EC state changed from off to on or on to off. If the debug cable is detached and then reattched the uart will be disabled on detach, but it won't be reenabled until the AP/EC are rebooted. BUG=chrome-os-partner:58222 BRANCH=none TEST=Detach and reattach suzyq without rebooting the AP or EC and make sure both consoles come back after reattaching the cable. Change-Id: Id104e12dc533e8d7047f32aebd41abd1c959d267 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/410269 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* reef: Enable fast charging profileVijay Hiremath2016-11-141-0/+1
| | | | | | | | | | | | | | | | | | Enable fast charging profile config (CONFIG_CHARGER_PROFILE_OVERRIDE) so that the battery desired current & voltage can be selected for given rated performance values. BUG=chrome-os-partner:59779 BRANCH=none TEST=Manually overrode the temperature and voltage. Observed correct charge profile config is selected for each tests. Change-Id: I080a3ace6d2f77bb6b97911b7705a44ec563258b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/410824 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Snappy: enable tcpc-controlled drp toggleBruce2016-11-131-0/+1
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=make buildall Change-Id: Icdeb4c67234c863128d1d3dd9bdecd149ee866ce Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/409733 Commit-Ready: Devin Lu <Devin.Lu@quantatw.com> Tested-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: Add support to S0iX based on host commands from KernelVijay Hiremath2016-11-136-71/+54
| | | | | | | | | | | | | | | | | | Picked the code from Glados branch. Change-Id: I4bf114235c4d542dd7cf0dad6427c771e54d4611 https://chromium-review.googlesource.com/#/c/331358/ BUG=chrome-os-partner:59742 BRANCH=none TEST=make buildall -j Change-Id: Ib79f1209dfd9e6a9de0438cb1866bba2939e5393 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/410036 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* smart_battery: Add console command to read ManufacturerAccess() dataVijay Hiremath2016-11-123-0/+59
| | | | | | | | | | | | | | | | | Added console command to read ManufacturerAccess() data on a given register block. BUG=chrome-os-partner:59660 BRANCH=none TEST=Enabled config on Reef. Successfully able to read ManufacturerAccess() data Change-Id: Ic86ae1b44ca8016634c48b54b1130d30fdd2d3fa Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/409638 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Pyro: Enable BD9995X power save mode when hibernatedBruce2016-11-121-0/+3
| | | | | | | | | | | | | | | | Turn off the charger BGATE when the system is hibernated to save maximum power. BUG=None BRANCH=None TEST=make buildall Change-Id: Ifd5d50bbdfde1383538e3ce86f002845798940ac Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/409853 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Pyro: enable tcpc-controlled drp toggleBruce2016-11-121-0/+1
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=make buildall Change-Id: I9a37cffc6018a34ba865d718f488206f06d96087 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/409895 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Pyro: clear hpd bit in board level tcpc initBruce2016-11-121-0/+12
| | | | | | | | | | | | | | | | | | PD alternate mode is covered in tcpc interface. So tcpci_tcpm_init() doesn't reset HPD. If keeping HDMI/DP type-C cable connected, doing sysjump sets HPD signal to high while it's already high(this high comes from previous state), then OS doesn't output to HDMI/DP monitor. BUG=None BRANCH=none TEST=make buildall Change-Id: Ic3bc75b1e5579816d8c1b294fe2eb65a20e3eae3 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/409751 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* bd9995x: Battery charging profile settingsVijay Hiremath2016-11-121-34/+69
| | | | | | | | | | | | | | | | | Added battery charging profile settings as given in the datasheet. BUG=chrome-os-partner:58553 BRANCH=none TEST=Manually verified on reef. VBAT is equal to battery voltage. Previous/current Charge status is equal to the conditions given in the datasheet. Change-Id: Ie04619a122fe52d6768c03ff5156b368e3f2d340 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/398080 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* cr50: request 0mA instead of 500mA for CCDMary Ruthven2016-11-111-0/+3
| | | | | | | | | | | | | | | This changes the usb descriptor to set the MaxPower to 0mA instead of 500mA. BUG=chrome-os-partner:59564 BRANCH=none TEST=Verify 'lsusb -vd 18d1:5014 | grep MaxPower' shows the power is 0mA Change-Id: Ieeb8dec6c205f4fe51392f8106b3a0ed7d3ea0a5 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/410288 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
* Cr50: Add TPM-compliant commands for console lockBill Richardson2016-11-114-55/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows custom TPM commands to be declared using the a DECLARE_VENDOR_COMMAND macro instead of the original (and still unchanged) DECLARE_EXTENSION_COMMAND macro. The new commands are nearly identical, but they are encapsulated using the vendor-specific protocols described in the TPMv2 spec. Our original extensions use a non-standard command code, and return a non-standard struct on completion, which can be confusing to standard TPM drivers and tools. Demonstrating the use of the new macros, this adds commands to obtain the state of the Cr50 restricted console lock, or to set the lock. There is intentionally no command to unlock the console. Note that this CL just adds the commands to the Cr50. We still need to provide a nice userspace utility for the AP to use. BUG=chrome-os-partner:58230 BUG=chrome-os-partner:57940 BRANCH=none TEST=make buildall; load, boot, test, and update again on Reef On Reef, I can use the trunks_send tool to send the raw TPM bytes to invoke these commands: Get the lock state: # trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10 80010000000D00000000001000 The last byte 00 indicates that the lock is NOT set, so set it: # trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10 80010000000C000000000011 Success. On the Cr50 console, I see it take effect: [480.080444 The console is locked] Query the state again: # trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10 80010000000D00000000001001 and now the last byte 01 indicates that the console is locked. And of course the existing extension commands still work as before. In addition to uploading firmware, I can use the usb_updater from my build machine to query the running firmware version: $ ./extra/usb_updater/usb_updater -f open_device 18d1:5014 found interface 4 endpoint 5, chunk_len 64 READY ------- start Target running protocol version 5 Offsets: backup RO at 0x40000, backup RW at 0x4000 Keyids: RO 0x3716ee6b, RW 0xb93d6539 Current versions: RO 0.0.10 RW 0.0.9 $ Change-Id: I7fb1d888bf808c2ef0b2b07c782e926063cc2cc4 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/409692 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* reef: enable tcpc low power modeKevin K Wong2016-11-118-19/+47
| | | | | | | | | | | BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890 BRANCH=none TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/399882 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef/ps8751: Add force wake for PS8751.Kevin K Wong2016-11-111-1/+12
| | | | | | | | | | | | | | | If PS8751 goes into low power mode during sysjump, then tcpm_init will fail since PS8751 is not accessible via I2C, so force it to wake up during hook_init. BUG=chrome-os-partner:59693 BRANCH=none TEST=Verified PS8751 port on reef is functional after sysjump. Change-Id: I2aa5a80b2ea9c17a01e4cba04493f83cb0a39955 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/410132 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* sweetberry: add usb power logging interfaceNick Sanders2016-11-118-12/+1056
| | | | | | | | | | | | | This allows logging of power data over sweetberry BUG=chromium:608039 TEST=log power data BRANCH=None Change-Id: I6f642384cbf223959294c7bd99bca0f9206775b8 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385540 Reviewed-by: Todd Broch <tbroch@chromium.org>
* CR50: add a constant time buffer equals implementationnagendra modadugu2016-11-119-18/+49
| | | | | | | | | | | | | | | | | | | | | | Various cryptographic operations leak timing information if comparisons are not executed in constant time. This change adds DCRYPTO_equals(), a constant runtime comparator. Also replace crypto related callsites that used memcmp() as a binary comparator. BUG=none BRANCH=none TEST=tcg tests pass Change-Id: I3d3da3c0524c3a349d60675902d1f2d338ad455f Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/410163 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* hammer: Switch to exponent 3 RSA keysNicolas Boichat2016-11-112-28/+28
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:59083 TEST=make BOARD=hammer -j && bash flash_hammer Change-Id: I686dbcfa3ad75ce83a997b20a06c22d8a005fccc Reviewed-on: https://chromium-review.googlesource.com/410580 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ISH: fix UART reference clockKyoung Kim2016-11-111-0/+4
| | | | | | | | | | | | | | | UART reference clock is 100KHz for ISH4 and 120MHz for ISH3 BUG=none BRANCH=None TEST=`make buildall -j` Change-Id: Ie33e0bd33e0a0c8e56a58fcf4a48677d38c9d61e Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/409594 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* flash_ec: Only check the board in the raiden list if the board not emptyWai-Hong Tam2016-11-101-1/+2
| | | | | | | | | | | | | | | | | | The firmware provision job running in the lab calls the flash_ec script with the --chip parameter, instead of the --board parameter. So only check if the board name is in the raiden list if it is a non-empty board. BRANCH=none BUG=chrome-os-partner:58039 TEST=Manually triggered the flash_ec command: $ flash_ec --chip=npcx_spi --image=${IMAGE} --port=9999 --raiden Change-Id: I25fef906d93803a94c544f7699ce494a84c46bd8 Reviewed-on: https://chromium-review.googlesource.com/410162 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* eCTS: Test task priorityDaisuke Nojiri2016-11-102-0/+39
| | | | | | | | | | | | | | | | | | CTS task wakes up A and C then goes to sleep: CTS -> A, C -> A -> B -> C Since C has a higher priority, C should run first. This should result in C running one more time than A (or B). BUG=chromium:663873 BRANCH=none TEST=cts.py -m task Change-Id: I89c733ba3aab09b293edf8583d6ed73791531e59 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/409535 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eCTS: Add task suiteDaisuke Nojiri2016-11-106-143/+125
| | | | | | | | | | | | | | | | | | | | Task A wakes up B and goes to sleep. Task B wakes up C then goes to sleep. Task C wakes up A then goes to sleep. This is repeated repeat_count times: A -> B -> C -> A -> ... It's expected all tasks to run exactly repeat_count times. Tick task runs to inject some irregularity. BUG=chromium:663873 BRANCH=none TEST=cts.py -m task Change-Id: Ib7227f05f09b7a49f8528aff6e6e8d3e6df93ba7 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/409534 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* test/rsa: Add test for RSA with public exponent 3Nicolas Boichat2016-11-106-1/+157
| | | | | | | | | | | | | | | This tests RSA 2048 with public exponent 3. BRANCH=none BUG=chromium:663631 TEST=make run-rsa3 Change-Id: I979ad4a23de6baba63aba037d2713b74fed4737f Reviewed-on: https://chromium-review.googlesource.com/408130 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common/rsa: Add support for exponent 3 RSA keysNicolas Boichat2016-11-102-2/+50
| | | | | | | | | | | | | | | | | | These keys are much quicker to verify (259ms to 51ms on a -M0 at 48 Mhz), so they can be used when timing is critical and verification needs to be performed on the board. BRANCH=none BUG=chromium:663631 TEST=make buildall -j && make run-rsa TEST=make run-rsa3 (next commit) Change-Id: I0da4b3e21543bb6f7b18e8b6ddc5e153046a61b8 Reviewed-on: https://chromium-review.googlesource.com/408006 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: disable sleepMary Ruthven2016-11-101-1/+5
| | | | | | | | | | | | | | | When bus obfuscation is enabled we have the chance of doing a security reset when resuming from sleep. Since we cannot disable bus obfuscation on current boards, we need to disable sleep. BUG=chrome-os-partner:57994 BRANCH=none TEST=make buildall Change-Id: I6f49278a9b41c1d15c646838044e34f03b979479 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/409576 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* charge_manager: send EC_HOST_EVENT_PD_MCU at the end of refreshJeffy Chen2016-11-101-2/+6
| | | | | | | | | | | | | | | | | | When kernel get EC_HOST_EVENT_PD_MCU event and query power state, we may not done refresh here. Delay EC_HOST_EVENT_PD_MCU event to avoid this race. BUG=chrome-os-partner:59499 BRANCH=gru TEST=Manual on kevin, check power state correct after unplug charger Change-Id: Ib88acf5a39c2780c6e40144ccebfba17cf84f77c Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/408131 Commit-Ready: Douglas Anderson <dianders@chromium.org> Tested-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* eCTS: Add nested interrupt test (High->Low)Daisuke Nojiri2016-11-094-5/+45
| | | | | | | | | | | | | | | | | | | | | | Add a nested interrupt test to eCTS. Higher priority IRQ is fired, followed by lower priority IRQ. Handlers should be executed sequentially. P1 *-----* / \ P2 / *-----* / \ task_cts ----* *---- B C A D BUG=chromium:653195 BRANCH=none TEST=cts.py -m interrupt; make buildall Change-Id: Ia9f1bf4205cefe8bdc11cc0aa3ad2057359b73ef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/409611 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eCTS: Add nested interrupt test (Low->High)Daisuke Nojiri2016-11-097-15/+92
| | | | | | | | | | | | | | | | | | | | | | Add a nested interrupt test to eCTS. Lower priority IRQ is fired, followed by higher priority IRQ. Handler executions should be nested. P1 *-----* / \ P2 *----* *----* / \ task_cts ----* *---- A B C D BUG=chromium:653195 BRANCH=none TEST=cts.py -m gpio, interrupt, timer; make buildall Change-Id: I34dc7b4e819051b9070a11e69d13d6be704f2e5f Reviewed-on: https://chromium-review.googlesource.com/408797 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eCTS: Pause a few seconds before flushing ttyDaisuke Nojiri2016-11-091-14/+15
| | | | | | | | | | | | | | | | After a board is reset for setting up a tty port, the host should wait for a few seconds before flushing the port as the board may still be booting. This should prevent output from the previous boot from creeping into a test run. BUG=none BRANCH=none TEST=cts.py -m gpio, interrupt, timer Change-Id: I1fb567a3a8ddcfff61865b6db3866c56be386c4a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/408759 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* test/rsa: Add test for RSA signature checkingNicolas Boichat2016-11-096-0/+217
| | | | | | | | | | | | | | This tests RSA 2048 with public exponent F4 (65537). BRANCH=none BUG=chromium:663631 TEST=make run-rsa3 Change-Id: I195a349bb9a862606971054adc9ac3b56a817fe7 Reviewed-on: https://chromium-review.googlesource.com/408129 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: hwtimer: Fix 'slow' timer count just before overflowShawn Nematbakhsh2016-11-093-5/+12
| | | | | | | | | | | | | | | | | | | | If our 32-bit usec timer is close to overflow, we may deep sleep several times in succession without making any adjustment to our count, causing deadlines on the other side (eg. HOOK_TICK expiration) to be reached much slower than expected. Avoid this by not entering deep sleep if our timer is about to overflow. This will result in a <= HOOK_TICK_INTERVAL (200ms interval) period of not entering deep sleep, every ~4300 seconds. BUG=chrome-os-partner:59240 BRANCH=gru TEST=Verify 3x kevin units survive 16 hours in S3 without EC watchdog. Change-Id: I2126458be8820f78212e19c2bb79242ff1194f6f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/409673 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Fix hwtimersShawn Nematbakhsh2016-11-092-6/+21
| | | | | | | | | | | | | | | | | | | | | | - Wait for ITEN bit to be set / cleared, since writing this bit just sets a 'request'. - Ensure ITIM_EVENT_NO reg is set with minimum value 1, per the datasheet. - Don't dsleep if our wake event is in the past (eg. wake event will occur any time now) BUG=chrome-os-partner:59240 BRANCH=gru TEST=Manual on kevin, verify that dsleep period never exceeds expected wait period. Also verify that EC watchdog doesn't occur after 5 hours in S3. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iedb2723c3f12b74dea66082b1d8b8ce1b6e7d945 Reviewed-on: https://chromium-review.googlesource.com/409672 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32f0: Allow change of external int prioritiesDaisuke Nojiri2016-11-092-3/+7
| | | | | | | | | | | | | | This change allows each board to customize external interrupt priorities. BUG=none BRANCH=none TEST=make buildall Change-Id: I5941f368ea70a069b34ce1d98508a1fad1ac22da Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/408796 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hammer: Add elan trackpad supportstabilize-8975.BNicolas Boichat2016-11-094-1/+12
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:59083 TEST=make BOARD=hammer -j && bash flash_hammer Change-Id: I8b0e2f3e33f48622097ce698c9548d3e96ac75f1 Reviewed-on: https://chromium-review.googlesource.com/407741 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* driver/touchpad_elan: Basic elan touchpad driverNicolas Boichat2016-11-085-0/+274
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:59083 TEST=make BOARD=hammer -j && bash flash_hammer Change-Id: I0ff4f48ff1399e054f745ac13ffacf81dffedeab Reviewed-on: https://chromium-review.googlesource.com/407740 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* hammer: Initial checkoutNicolas Boichat2016-11-087-0/+262
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:59083 TEST=make BOARD=hammer -j && bash flash_hammer Change-Id: I8cc11408d28677a800af58e738f47d5dcadea3e6 Reviewed-on: https://chromium-review.googlesource.com/407739 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec_commands: Add a new host event for extended eventsFurquan Shaikh2016-11-081-0/+6
| | | | | | | | | | | | | | | Since we are out of host event bits, add a bit to indicate extended host event exists. This is put in as a placeholder for now so that we don't lose out the last available hostevent bit. BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: If35a246f3da511fde9f8c0bba419afb76a1a9827 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/407804 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: Add new recovery mode button combinationFurquan Shaikh2016-11-086-48/+70
| | | | | | | | | | | | | | | | | | This adds new key combination (Left_Shift+Esc+Refresh+Power) that triggers recovery mode by setting a new host event EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT. This host event can be used whenever user wants to request entry into recovery mode by reinitializing all the hardware state (e.g. memory retraining). BUG=chrome-os-partner:56643,chrome-os-partner:59352 BRANCH=None TEST=Verified that device retrains memory in recovery mode with (Left_Shift+Esc+Refresh+Power) on reef. Change-Id: I2e08997acfd9e22270b8ce7a5b589cd5630645f8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/407827 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* driver: sensor: Remove set_interruptGwendal Grignou2016-11-085-50/+0
| | | | | | | | | | | | | | Remove set_interrupt(), was always a noop. Unused, interrupt is done inside the init routine. BUG=none BRANCH=none TEST=buildall Change-Id: I0ff4843212ea8140be41dcd17af130991117e3da Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/407968 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: Add tablet_mode APIGwendal Grignou2016-11-0811-29/+49
| | | | | | | | | | | | | | | | | | | Simple API to set/get the tablet mode. It can be set via lid angle calculation or if a board has a dedicated HAL sensor/GPIO. Merged from glados branch, add MKBP switch support. BUG=chromium:606718 BRANCH=gru TEST=Check with Cave that both mode works. Reviewed-on: https://chromium-review.googlesource.com/402089 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c940f36ceabcf2425284001298f03ebdb4c3079e) Change-Id: I2ee5130f3e0a1307ec3ea543f7a32d66bc32b31d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/404915 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_serial: add python consoleNick Sanders2016-11-081-0/+287
| | | | | | | | | | | | | | | console.py can access a Google USB serial endpoint specified by vid:pid and serial number BUG=chromium:608039 TEST=open console to send and receive text. BRANCH=None Change-Id: I735692b7031d73506be2745a2cd5225bfcefd396 Reviewed-on: https://chromium-review.googlesource.com/405030 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Kevin Cheng <kevcheng@chromium.org>
* bd9995*: maintain VBAT voltage as battery maximumWonjoon Lee2016-11-086-6/+2
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:54248 BRANCH=gru TEST=Manual on kevin, high temperature chamber(60C), battery will require 0 voltage because of high temp, then check 'chgstate' vbat maintained at 8688 mV. Change-Id: I3b5835701c42a0cd861400ba921b3d3797152bbd Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/400088 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Cr50: Let NVMEM take more time and memoryBill Richardson2016-11-052-1/+3
| | | | | | | | | | | | | | | | | | | | | | We were getting occasional stack overflow and watchdog timeouts when clearing NVMEM. Bump up the stack size a bit in the HOOKS task, and pet the watchdog before invoking the tpm2 init functions. BUG=chrome-os-partner:59419 BRANCH=none TEST=make buildall, manual Lock the console, then unlock it. This will reboot the EC & AP, but should never reboot the Cr50. Before this CL, it did about half the time. After, it doesn't. Change-Id: I33adfeb7360bf7d146a55ef16c923a1a0416393d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/407847 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* reef: Update battery structure info as in the specVijay Hiremath2016-11-051-46/+43
| | | | | | | | | | | | | | BUG=chrome-os-partner:59285 chrome-os-partner:55861 BRANCH=none TEST=make buildall -j Change-Id: I2a22f5ef0072793701f4899cd6e669b8cccca78b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/406682 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* elm / kevin / oak: Don't wake from S3 on lid closeShawn Nematbakhsh2016-11-053-6/+3
| | | | | | | | | | | | | | | BUG=chrome-os-partner:59256 BRANCH=gru TEST=None Change-Id: I8e41dc131343e7639850364db27a3ff926164fba Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/407078 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* anx74xx: Modifed tcpm_get_cc function to fix check for 3.0 A typeScott2016-11-042-37/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When attaching a dump (not PD protocol) TypeC charger, the incorrect charger type was being selected and therefore it was not enabling 3A charging. I tracked this issue down to the anx74xx_tcpm_get_cc() function returning a incorrect value. The expected value was TYPEC_CC_VOLT_SNK_3_0, but instead it was returning TYPEC_CC_VOLT_SNK_DEF. The reason the incorrect cc type was being returned is because the if, else if, construct didn't work properly for the 3A case where the upper 2 bits are set. Modified this routine to use a case statement and consolidated the checks for both cc1 and cc2 into one helper function. BRANCH=none BUG=chrome-os-partner:58738 TEST=manual Connected zinger and guppy chargers and verified correct cc type was being returned. In addition tested hoho/dingdong adapters as well as suzyq. Tested both cable orientations to verify that cc1 and cc2 returned the correct values. With guppy connected, now see this output on ec console: C0 HARD RST TX C0 st5 C0 st36 C0 st37 C0 HARD RST TX C0 st5 [1921.980074 AC on] [1922.008140 charge_request(8688mV, 9280mA)] C0 st6 [1922.910539 Ramp p0 st5 3000mA 3000mA] Change-Id: I8b31c7ce366f383dfcc2f6e850b76a83340a02a1 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/406642 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* host_command_pd: reduce to 5msec delay in between PD interrupt handlingKevin K Wong2016-11-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | Since PD task are highest priority, the 50msec delay between was intended allow other tasks to execute if PD has continuous interrupt. With two separate TCPC handled by host_command_pd task, interrupt from one TCPC will block the interrupt handling of another TCPC by this 50msec and cause error in the PD negotiation. Reduced to 5msec to ensure TCPC interrupt is handled as soon as possible while allow other tasks to execute if needed. BUG=chrome-os-partner:59061 BRANCH=none TEST=Verify zinger can negotiate to 20V, hoho can get display. Also tested with faking PD interrupt always asserted to check for watchdog reset. Change-Id: I9b71277a3d65923f1f5bbfd744b3399e34fd0e6c Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/407542 Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* Cr50: I2CS TPM: Ensure HW read fifo is empty for register readsScott2016-11-043-21/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is a safegaurd to ensure that TPM register data is always placed in the correct location in the HW read I2CS fifo. It is only checked for 1 or 4 byte regsiter reads. Because of the way in which a TPM command is sent and the response is read, there are multiple reads of the STS register prior to reading the TPM fifo register. Therefore ensuring the fifo has zero depth when 1 or 4 byte regsiter reads, improves the robustness of the design. Added a counter to track the number of times the fifo is adjusted and a new console command 'i2cs disp|rst' to display the count and reset it to 0 if desired. Removed section in code for TPM fifo register reads intended to handle the case where there was a mismatch between how many bytes were copied into the fifo and the number read by the host. Since the burstcount field in the status register always contains a valid amount of data that can be read by the host, there should not be cases where the host reads less data than was copied from the TPM fifo register. In the unexpected cases where the host may not drain all of the I2CS read fifo data during a TPM register read, the I2CS fifo depth will be corrected the next time that it reads either the access or STS register which happens prior to the start of any TPM transaction. BRANCH=none BUG=chrome-os-partner:57338,chrome-os-partner:59191 TEST=manual Booted Reef and verfied that TPM functionality is working. Change-Id: I065a55e64bbcc0cb3357a2bd83447a05400b8899 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382689 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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