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* it83xx: adc: interrupt is usedDino Li2017-01-106-23/+116
| | | | | | | | | | | | | | | | | | | | We don't need to loop and waiting ADC's data valid flag after the change was made. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. We build a EC binary for PD EVB (declared two ADC channels for VBUS measurement of PD task and priority is highest) 2. Use console command "adc" continually to read ADC channels and check if any error. Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b Reviewed-on: https://chromium-review.googlesource.com/421307 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: flash: Do not delay flash access requests.Shamile Khan2017-01-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | When depthcharge invokes a Host command that needs EC to access flash, the response is delayed by approx 150 ms because EC is busy with another flash operation to determine size of RW image for computing hash. We can eliminate this delay and also speed up the flash operation by using the same mechanism that is used for mec1322 based designs which also use external SPI flash. The changes are: a) We access 4 bytes from SPI flash at a time instead of a single byte b) We split flash accesses into smaller parts which means that mutex lock is acquired for a short duration. BUG=chrome-os-partner:59875 BRANCH=none TEST=make buildall -j After sysjump to RW, in EC Log the "hash start" is printed approx 120 ms earlier. Change-Id: Icb633379c992e795ba40eaf54fe9ec31747d4be6 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/426016 Reviewed-by: Shawn N <shawnn@chromium.org>
* snappy: modify battery temps setting by follow snappy spec.Bruce2017-01-102-139/+13
| | | | | | | | | | | | | | | | Let unit can't charge when battery temperature is over than 45 degree by follow snappy spec. BUG=none BRANCH=reef TEST=check temp is over than 45 degree, the unit can't charge. Change-Id: Ic6d5f94790bb528b96980681dd223724b5a98359 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/426281 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* npcx: shi: Optimize OBUF copy / fillShawn Nematbakhsh2017-01-101-22/+53
| | | | | | | | | | | | | | | | | | | | | | | We have hard timing requirements once we begin to output our host command response, and most of the time is spent copying our response to OBUF. Optimize our copy loops to remove needless increments and to avoid needless struct dereference. BUG=chrome-os-partner:61304 BRANCH=gru TEST=Manual on kevin, verify the following performance metrics: Time spent in shi_fill_out_status(): Was 40us, now 28us Time spent in shi_write_half_obuf(): Was 60us, now 31us Time spent in shi_write_first_pkg_outbuf: Was 90us, now 37us (bad case) Was 26us, now 16us (better case / less data copied) Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I04075c92744eeefe8f2be009e6598718c45143c4 Reviewed-on: https://chromium-review.googlesource.com/425330 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pyro/snappy: Enter/exit from S0ix based on host commands from kernelBruce2017-01-106-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow reef setting. This patch changes the entry/exit model for S0ix from a PCH SLP_S0 signal based model to a hybrid host event/direct interrupt model. The kernel will send host events on kernel freeze/thaw exit; EC will initiate the S0ix entry based on host command and exit via another host command from kernel. The assertion of SLP_S0 comes later than HC(suspend) and deasserion of SLP_S0 comes earlier than HC(resume). ________ ________ SLP_S0 |______________________| _____ ________ HC |___________________________| BUG=none BRANCH=reef TEST=make buildall Change-Id: I1073b5cb2cbb8492cec0967f2a6004c5ce368ecb Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/426558 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* pyro/snappy: Add CONFIG option to maintain VBAT voltageBruce2017-01-102-0/+2
| | | | | | | | | | | | | | | | | | | | Follow reef setting. On the bd9995*, back boosting may occur when actual battery voltage drops below VBAT register setting. Maintain the VBAT register at the battery-requested charge voltage even when not charging to ensure the bd9995* doesn't become a back boosted animal. BUG=none BRANCH=reef TEST=make buildall Change-Id: Ie7aaffc38fef65721886d00be3d6827e9e124efa Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/426499 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: prepare for releasing rw version 0.0.14Vadim Bendebury2017-01-102-2/+2
| | | | | | | | | | | | | Which is coming soon. BRANCH=none BUG=none TEST=built a new image, verified that its rw version is 0.0.13 Change-Id: Iddd00f901a74e3b4f6d5796a8092aa39676fc3b3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/425854 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* driver: bmi160: Set odr to 0 at init.Gwendal Grignou2017-01-101-0/+6
| | | | | | | | | | | | | | | | | | | | | | | When we switch to a state where the sensor is not powered, we don't call set_data_rate(0), because we may trigger an i2c/spi access to a sensor already powered off. It has the side effect to leave data->odr to the last set sensor frequency. When we init the BMI160, it starts in suspend mode. We will set it to normal mode only if data->odr is 0. Therefore, we must set odr to 0 in the init routine. BUG=chrome-os-partner:61502 BRANCH=reef,kevin TEST=On reef, without this change. When going to S5 (shutdown -h 0) and power back up, sensor is stuck (on EC, accelread 1 reads old value). With this fix, sensor is active and working. This fix a regression due to CL:411964. Check others driver do not check odr for setting suspend/normal mode. Change-Id: Ibc7519d49e55a0b43b4c12ed545bd75ab0260766 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/426766 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* npcx: shi: fix bug of clearing EVSTAT_EOR bitCHLin2017-01-091-1/+1
| | | | | | | | | | | | | | | | | It is not proper to use SET_BIT macro to clear a "write 1 to clear" bit in a register. It will also clear other bits if they are also set. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall; boot up on gru, run ectool stress test for a while without problem. Change-Id: I0c5a850e85e41820515b1a8f15bb43d77397737f Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/425589 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* pyro: modify led pin setting at hibernate state.Bruce2017-01-091-2/+3
| | | | | | | | | | | | | | | | | | HW change led power rail, so the battery led and logo led will light in hibernate state. I modify battery led pin (gpio84, gpioC4) and logo led pin (pwm3) setting in hibernate, let them will not light in hibernate. BUG=none BRANCH=reef TEST=make buildall Change-Id: I6c75694cf92fe05b5afc0d2a399e15c5bff6b7f8 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/425563 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* servo_v4: Added initial USB PD support for both CHG/DUT portsScott2017-01-097-11/+594
| | | | | | | | | | | | | | | | | | | | | | | - CHG port can connect as SNK at different voltage levels - DUT port presents as SNK only - DUT port uses fixed polarity since it has a fixed cable - Not supporting ALT or ALT_DP modes in terms of svdm messages at this point. - No support yet for USB mux. BUG=chromium:571476 BRANCH=None TEST=Manual CHG port: Tested with Zinger and Plankton and 5/12/20V VBUS levels. DUT port: Tested against Reef and verified that port reached SNK_READY. Change-Id: Ib645872790912f9e0a0d4adddc10345a59145d3e Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424413 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* minute-ia: fix floating point inline assemblyKyoung Kim2017-01-091-6/+8
| | | | | | | | | | | | | | | | | | | | change inline assembly for fsqrt and fabs BUG=none BRANCH=None TEST=`make buildall -j` 1. Compare sqareroot(2) from calculator and from sqrtf(2.0f) by multiplying 1.0 x 10E8 for both values to convert int32_t and check the difference. 2. read timestampt before and after 'sqrtf()' and calculate execution time. Change-Id: I62694d8b084a3a74040dc298354b4fd685e77729 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/404927 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* eve: Enable Sensor FIFOGwendal Grignou2017-01-092-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable to FIFO to allow ARC++ sensor support and sensor tests. BUG=chrome-os-partner:59144 BRANCH=eve TEST=On an eve machine, check the ring sensor is receiving data: cd /sys/bus/iio/devices/iio:device0 # cros-ec-ring for i in scan_elements/*_en ; do echo 1 > $i ;done echo 1024 > buffer/length echo 1 > buffer/enable cd /sys/bus/iio/devices/iio:device1 # cros-ec-accel echo 1000 > sampling_frequency # 1s echo 25000 > frequency # 25Hz Check we are receiving data with: od -x /dev/iio\:device0& ... 0031560 0001 0400 ff5e c072 7719 873e 002a 0000 0031600 0001 03e1 ff61 c0be 983e 8995 002a 0000 0031620 0001 03ea ff50 c095 b963 8bec 002a 0000 0031640 0001 03fb ff5c c0c8 da88 8e43 002a 0000 0031660 0001 03ed ff63 c0b0 fbad 909a 002a 0000 ... Change-Id: I0401df4233f4fa1514dfa6d368ba463dcc705895 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424846
* nvmem_vars: use dynamic memory allocationVadim Bendebury2017-01-092-19/+33
| | | | | | | | | | | | | | | To avoid SRAM footprint, let's use dynamic memory allocation in nvram_vars. No one is using this module yet, but the cr50 use case is coming up. BRANCH=none BUG=chrome-os-partner:61107 TEST=make buildall -j passes Change-Id: I21534430217ad387a3787fcc127da596a1b48e03 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/426088 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* test: nvmem_vars: drop redundant erase_flash() invocationsVadim Bendebury2017-01-091-7/+0
| | | | | | | | | | | | | | | There is no need to invoke erase_flash() before load_flash(), as load_flash() invokes that function itself. BRANCH=none BUG=none TEST=make buildall -j still passes Change-Id: Ic4aba9f680402418ec6268d6ed5800065a09110b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/426087 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* power: Extract Intel x86 power sequencing common codeVijay Hiremath2017-01-077-178/+202
| | | | | | | | | | | | | | | | | Extracted Intel x86 power sequencing common code from skylake.c and apollolake.c to implement common code for power sequencing. BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Reef can boot to OS. S3, S5, hibernate are working. Change-Id: I73478fcabb24d6d98cd474bae3586ce5b02986fe Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/406486 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* motion_sense: Add "spoof" modeAseda Aboagye2017-01-077-16/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a "spoof" mode feature to the motionsense stack. It allows the user to arbitrarily set the outputs of the sensor in order to "spoof" the readings of the sensor. This can be useful in emulating tablet mode or device rotations. A command is available from the EC console named `accelspoof` and there is a corresponding motionsense command in ectool called `spoof`. The usage is as follows: - EC console > accelspoof [id] [on/off] [X Y Z] - ectool # ectool motionsense spoof -- [id] [0/1] [X Y Z] If on or off(or 0/1) is not specified, the current spoof mode status of the sensor is returned. If on is specified, but no components are provided, the sensor will lock the current values and provide those as the spoofed values. If the components are provided, those will be used as the spoofed values. BUG=chromium:675263 BRANCH=cyan,glados,gru,oak TEST=Flash a DUT with accels. From AP console, run `ectool motionsense lid_angle` in a loop, use 'accelspoof' EC console command to set spoofed values. Verify that the angle is fixed regardless of the actual angle of the DUT. TEST=Flash a DUT with accels. From AP console, use `ectool motionsense spoof` to spoof values and verify that `ectool motionsense` reflects the spoofed values. Test with both provided component values and no component values. Change-Id: Ie30688d22f38054e7243b1af493a3092b2cdfb72 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/421280 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* charge_state_v2: Correct Smart battery charging/discharging statusVijay Hiremath2017-01-061-1/+25
| | | | | | | | | | | | | | | | | | | | | | | AverageTimeToFull() and AverageTimeToEmpty() are the predicted time based on the AverageCurrent(), these do not reflect the instant time of charging or discharging. Hence we observe huge number of time (1092h because register has 65535) to full time when battery starts accepting current upon reaching 100%. To overcome this issue, explicitly checking if the AverageTimeToFull() and AverageTimeToEmpty() register values are updated with the valid data. BUG=chrome-os-partner:60802 BRANCH=none TEST=Manually tested on Reef. Charge the battery to 100%, once the battery starts accepting current again observed time to full is not huge number. Change-Id: I6d6c21b72ab824dbe47e44e1e77f1c5319ac2720 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/425324 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* apollolake: Add support to enable eSPI signalsVijay Hiremath2017-01-061-6/+32
| | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Change-Id: I6d90d647a6e19c627aa68ddd8a203d6be8b2e32d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/425820 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake: Reuse the sleep event code from the common codeVijay Hiremath2017-01-062-51/+7
| | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Change-Id: I881b92215f24ea047ec4fc3109b174ff1615de29 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/425486 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* iec: Improve efficiency of host command dispatcherSam Hurst2017-01-0611-139/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use binary search in host command lookup dispatcher BUG=chromium:570895 TEST=manual testing on kevin - Kevin boots - ectool hello make buildall -j Verify *.smap hcmds section is sorted: BOARD with host commands and private host commands 0004d0ec R __hcmds 0004d0ec R __host_cmd_0x00000x0000 0004d0f8 R __host_cmd_0x00000x0001 0004d104 R __host_cmd_0x00000x0002 0004d110 R __host_cmd_0x00000x0003 0004d11c R __host_cmd_0x00000x0004 0004d128 R __host_cmd_0x00000x0005 0004d134 R __host_cmd_0x00000x0007 0004d140 R __host_cmd_0x00000x0008 0004d14c R __host_cmd_0x00000x000a 0004d158 R __host_cmd_0x00000x000d 0004d164 R __host_cmd_0x00000x0010 0004d170 R __host_cmd_0x00000x0011 0004d17c R __host_cmd_0x00000x0012 0004d188 R __host_cmd_0x00000x0013 0004d194 R __host_cmd_0x00000x0015 0004d1a0 R __host_cmd_0x00000x0016 0004d1ac R __host_cmd_0x00000x0017 0004d1b8 R __host_cmd_0x00000x0087 0004d1c4 R __host_cmd_0x00000x008c 0004d1d0 R __host_cmd_0x00000x008f 0004d1dc R __host_cmd_0x00000x0092 0004d1e8 R __host_cmd_0x00000x0093 0004d1f4 R __host_cmd_0x00000x0097 0004d200 R __host_cmd_0x00000x0098 0004d20c R __host_cmd_0x00000x00b6 0004d218 R __host_cmd_0x00000x00d2 0004d224 R __host_cmd_0x00000x00d3 0004d230 R __host_cmd_0x3E000x0000 0004d23c R __host_cmd_0x3E000x0002 0004d248 R __evt_src_EC_MKBP_EVENT_HOST_EVENT 0004d248 R __hcmds_end BOARD with host commands only 100bc888 R __hcmds 100bc888 R __host_cmd_0x00000x0000 100bc894 R __host_cmd_0x00000x0001 100bc8a0 R __host_cmd_0x00000x0002 100bc8ac R __host_cmd_0x00000x0003 100bc8b8 R __host_cmd_0x00000x0004 100bc8c4 R __host_cmd_0x00000x0005 100bc8d0 R __host_cmd_0x00000x0006 100bc8dc R __host_cmd_0x00000x0007 100bc8e8 R __host_cmd_0x00000x0008 100bc8f4 R __host_cmd_0x00000x0009 100bc900 R __host_cmd_0x00000x000a 100bc90c R __host_cmd_0x00000x000b 100bc918 R __host_cmd_0x00000x000d 100bc924 R __host_cmd_0x00000x0010 100bc930 R __host_cmd_0x00000x0011 100bc93c R __host_cmd_0x00000x0012 100bc948 R __host_cmd_0x00000x0013 100bc954 R __host_cmd_0x00000x0015 100bc960 R __host_cmd_0x00000x0016 100bc96c R __host_cmd_0x00000x0017 100bc978 R __host_cmd_0x00000x0025 100bc984 R __host_cmd_0x00000x0026 100bc990 R __host_cmd_0x00000x0029 100bc99c R __host_cmd_0x00000x002a 100bc9a8 R __host_cmd_0x00000x002b 100bc9b4 R __host_cmd_0x00000x002c 100bc9c0 R __host_cmd_0x00000x0044 100bc9cc R __host_cmd_0x00000x0045 100bc9d8 R __host_cmd_0x00000x0046 100bc9e4 R __host_cmd_0x00000x0047 100bc9f0 R __host_cmd_0x00000x0061 100bc9fc R __host_cmd_0x00000x0062 100bca08 R __host_cmd_0x00000x0064 100bca14 R __host_cmd_0x00000x0065 100bca20 R __host_cmd_0x00000x0067 100bca2c R __host_cmd_0x00000x0087 100bca38 R __host_cmd_0x00000x008c 100bca44 R __host_cmd_0x00000x008d 100bca50 R __host_cmd_0x00000x008f 100bca5c R __host_cmd_0x00000x0092 100bca68 R __host_cmd_0x00000x0093 100bca74 R __host_cmd_0x00000x0096 100bca80 R __host_cmd_0x00000x0097 100bca8c R __host_cmd_0x00000x0098 100bca98 R __host_cmd_0x00000x0099 100bcaa4 R __host_cmd_0x00000x009e 100bcab0 R __host_cmd_0x00000x00a0 100bcabc R __host_cmd_0x00000x00a1 100bcac8 R __host_cmd_0x00000x00a8 100bcad4 R __host_cmd_0x00000x00a9 100bcae0 R __host_cmd_0x00000x00b6 100bcaec R __host_cmd_0x00000x00b7 100bcaf8 R __host_cmd_0x00000x00d2 100bcb04 R __host_cmd_0x00000x00d3 100bcb10 R __host_cmd_0x00000x00db 100bcb1c R __host_cmd_0x00000x0101 100bcb28 R __host_cmd_0x00000x0102 100bcb34 R __host_cmd_0x00000x0103 100bcb40 R __host_cmd_0x00000x0104 100bcb4c R __host_cmd_0x00000x0110 100bcb58 R __host_cmd_0x00000x0111 100bcb64 R __host_cmd_0x00000x0112 100bcb70 R __host_cmd_0x00000x0113 100bcb7c R __host_cmd_0x00000x0114 100bcb88 R __host_cmd_0x00000x0115 100bcb94 R __host_cmd_0x00000x0116 100bcba0 R __host_cmd_0x00000x0117 100bcbac R __host_cmd_0x00000x0118 100bcbb8 R __host_cmd_0x00000x011a 100bcbc4 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX 100bcbc4 R __hcmds_end BRANCH=none Change-Id: I5d13d2a7fe7fa9a0fbeed43177cc612f572a58bb Reviewed-on: https://chromium-review.googlesource.com/419702 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pyro/snappy: enable/disable KB and TP function in S3stabilize-9157.BBruce2017-01-062-12/+34
| | | | | | | | | | | | | | | | | In S3 state, then disable KB/TP function when state switch to tablet mode from normal mode.Enable KB/TP function when state switch to nromal mode from tablet mode. BUG=none BRANCH=reef TEST=make buildall Change-Id: If759504b6d471ddc18f322aeda07ccbd6ccd636e Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/425416 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* nds32: lds: reduce gap of flashDino Li2017-01-055-32/+38
| | | | | | | | | | | | | | | | | | | | | - Before the change was made, the "__ro_end" was at 00013520h. We change to 00012760h. - Rename "CONFIG_IT83XX_ILM_BLOCK_SIZE" to "IT83XX_ILM_BLOCK_SIZE" this is because we don't support reconfiguration at board-level. - Put some task functions into "__ram_code" section to fill the gap and improving performance of code-fetch. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console commands: flasherase, flashwrite, and flashread. Change-Id: I2f2906a2a0b6971aadd00120c282801161447808 Reviewed-on: https://chromium-review.googlesource.com/424248 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Makefile.rules: Allow specifying HOST_LDFLAGS for cross-compilationMoritz Fischer2017-01-051-1/+1
| | | | | | | | | | | | | | | | Add HOST_LDFLAGS to cmd_c_to_host to allow for cross-compilation of utils such as 'ectool'. BRANCH=master BUG=none TEST=Cross compile using arm-oe-linux-gnueabi with corresponding linkerflags and run resulting binary on armv7 device Change-Id: Iebdfa92239eb5f245d4ad3623cbdceafd82d1675 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: https://chromium-review.googlesource.com/424855 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
* cr50: vendor command to enable nvmem commitsVadim Bendebury2017-01-052-0/+12
| | | | | | | | | | | | | | | | | | | | | TPM NVMEM commits are reenabled as soon as the system boots into Chrome OS. However, sometimes the device does not boot into Chrome OS, in which case it is necessary to be able to reinstate NVMEM commits explicitly. The new vendor command will provide this functionality. BRANCH=none BUG=chrome-os-partner:59873 TEST=added code to depthcharge to issue the new vendor command if the system falls into recovery mode, verify that commits are re-instated once the command is issued. Change-Id: I3c06b27175751dc2c095911441935eee62ed9c50 Reviewed-on: https://chromium-review.googlesource.com/424064 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: Avoiding nvram commits at startupVadim Bendebury2017-01-054-5/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch eliminates NVMEM commits at system startup, namely between the moment the TPM is reset and the moment the AP is trying to read a PCR (which is an indication of the AP having booted into OS). To avoid losing NVMEM changes in case TPM is reset before PCR Read command is issued, pending changes (if any) are saved before TPM reset is processed. For the same reason TPM reset invocation is being added to the hard reboot path; this will kick in when there is a restart after cr50 firmware update. BRANCH=none BUG=chrome-os-partner:59873 TEST=with instrumented coreboot/depthcharge observed the following execution times for various TPM command issued at startup command 0x144, 15203 us command 0x14e, 11814 us command 0x182, 12461 us command 0x182, 12456 us command 0x138, 11503 us command 0x138, 11512 us command 0x14e, 14648 us command 0x14e, 12597 us command 0x121, 11353 us which totals 113 ms and shaves more than 200 ms off the boot time. Change-Id: Ic52309291fdb9c3ede96e0ad015ad9fc076bddc5 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424063 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: enable use malloc/freeVadim Bendebury2017-01-051-0/+3
| | | | | | | | | | | | | | In preparation to adding new features, switch cr50 to using shared memory allocator allowing concurrently allocated buffers. BRANCH=none BUG=chrome-os-partner:59873 TEST=verified that cr50 works fine and could be updated on a reef. Change-Id: I87656cbd1f6d4928f25396dbcc59cc3f43984d85 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424850 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: introduce malloc/free implementationVadim Bendebury2017-01-058-7/+764
| | | | | | | | | | | | | | | | | | | | | | | | | | | The new code allows to replace the existing one buffer at a time shared memory facility with a malloc/free implementation. A new configuration option is being provided (CONFIG_MALLOC). The names of functions allocating and freeing memory are not being changed to allow to switch between the two implementations seamlessly. A double linked list of buffers is used to keep track of free and allocated memory. During initialization the entire free memory block is considered a single free buffer. No allocations/frees are allowed from within interrupts. The control structures are protected by a semaphore, so allocate and free invocation could be blocking. A test is added which randomly allocates and frees memory, continuing until all branches in the allocate and free functions are taken. BUG=chrome-os-partner: TEST=make buildall -j succeeds, which includes testing the new malloc/free implementation. Change-Id: I5e71c0190c6c247ec73bb459f66a6d7a06e3d248 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/420466 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Allow a subset of boards to be built with the "buildall" target.Carl Hamilton2017-01-051-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to reduce build times during development, this change allows an engineer to build a subset of all boards, writing the results for each board into the ".failedboards" directory. The expectation is that, while working on code that affects multiple boards, the engineer will invoke "make build_boards BOARDS=<board-list>" periodically to confirm that all affected boards still build. Before pushing any code for review, however, the engineer is still expected to run "make buildall" to ensure all boards still build and tests pass. * Define a new make variable, BOARDS, whose default value is $(boards). This variable can be overridden on the make command line or via the environment. Its value must be non-empty. * Use the BOARDS make variable to control which boards will be built by the new "build_boards" and "try_build_boards" targets. * Refactor the "buildall" target so that it depends on "build_boards". This indirectly allows the boards built to be controlled via the BOARDS make variable. * Here are some make command lines that were used to test the behavior of the change: make -j buildall # Builds all boards, runs tests. make -j build_boards # Builds all boards, doesn't run tests. make -j build_boards BOARDS="cr50 reef" # Builds cr50 and reef boards make -j build_boards BOARDS= # Fails due to empty BOARDS. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I833277842e5e20d86eaa90df6457264a2f86a3fa Reviewed-on: https://chromium-review.googlesource.com/420110 Commit-Ready: Carl Hamilton <carlh@chromium.org> Tested-by: Carl Hamilton <carlh@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
* poppy: Add new boardNicolas Boichat2017-01-058-0/+1589
| | | | | | | | | | | | | | | | | | | Add support for poppy board with: - chip: npcx - pmic: bd999992GW - charger: isl9238 - tcpc: 1x anx3429, 1x ps8751 - bc12: pi3usb9218c BRANCH=none BUG=chrome-os-partner:61098 TEST=make BOARD=poppy -j Change-Id: I3439399b85ba49b4c733536d614118faeeeb0f93 Reviewed-on: https://chromium-review.googlesource.com/422263 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* charger: isl923x: Add support for ISL9238Nicolas Boichat2017-01-055-300/+330
| | | | | | | | | | | | | | | ISL9237 and ISL9238 are almost identical, with few register changes, let's make the driver generic, to support both chargers. BRANCH=none BUG=chrome-os-partner:61166 TEST=make buildall -j Change-Id: I029894dd62ab7e45897d877289707ee8c1ff1d09 Reviewed-on: https://chromium-review.googlesource.com/422197 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* driver: als: Add error code UNCHANGEDGwendal Grignou2017-01-052-4/+7
| | | | | | | | | | | | | | This error code is used to indicates the data has not changed. Motion sense task will therefore not add any entry in the sensor FIFO. BUG=chrome-os-partner:59423 TEST=make -j buildall BRANCH=reef Change-Id: I58b9be5675d8949bd682d8c89dadea1dfff9bf2e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424856 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* core: Fix bug will cause tasks sleep forever by mutex_unlock in task.c.Mulin Chao2017-01-052-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there's a task switching occurred between loading waiter and unlocking the lock, the task with higher priority won't wake up since the local variable, waiter, doesn't contain its ID bit before task switching. In this situation, the higher priority task only can be awakened when the other tasks execute mutex_unlock() again. But consider the following conditions: (For example, the driver of charger bd9995x.) 1. There are more than one mutex for the usage path of i2c port. 2. There are more than one task access this usage path of i2c port and one of these tasks, task A, met the situation above. 3. The other tasks have no chance to execute mutex_unlock() of i2c since the task A still occupied the mutex of charger. All the tasks used the same i2c port or the other hardware will sleep forever. This CL makes loading waiter and unlocking the lock as atomic to solve this issue. BRANCH=none BUG=chrome-os-partner:60617 TEST=make BOARD=snappy; make BOARD=oak; Executed charger factory test on 4 units of snappy for 3 days and no symptom occurred. Change-Id: Id976fc47955b33ca83bb2182b197d9f2781c341b Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/423285 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* motion: Disable tablet mode if one accel is brokenGwendal Grignou2017-01-043-2/+16
| | | | | | | | | | | | | | | | We need 2 accelerometer for tablet mode. If one of them is not working, disable tablet mode. We will stay in clamshell mode, lid angle will be always unreliable. BUG=chrome-os-partner:61141 TEST=On kevin with a single sensor. Check we are in clamshell mode when rebooting the EC. BRANCH=kevin Change-Id: I7bf6cdc9d85370fce20e5183622b4bc18f4f5f99 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424184 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* pstore: Fix issue with block calculation for pstore blocksMoritz Fischer2017-01-031-2/+2
| | | | | | | | | | | | | | | | Fix issue where the block is calculated wrong since the offset that gets added is wrongly EEPROM_BLOCK_COUNT_PSTORE which is the number of total blocks rather than the starting block given by EEPROM_BLOCK_START_PSTORE. TEST=Build test, ran on board with stubbed out functions. BUG=none BRANCH=none Change-Id: Ide4839845353c2b9f95a37eb689c8d800169bb22 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: https://chromium-review.googlesource.com/424182 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: lpc: Do not use FW_OBF bit to clear OBF bitCHLin2017-01-032-24/+109
| | | | | | | | | | | | | | | | | | | | | Setting HICTRL.FW_OBF clears the HIKMST.OBF and STATUS.OBF flags but it does not deassert IRQ1 when already asserted. To make sure IRQ1 will also be deasserted need to emulate a host read. Modified drivers: 1. lpc.c: emulate a host read to clear OBF and deasserted IRQ1. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall; Run FAFT items related to Power on/off, reboot, and keyboard on Wheatley. Change-Id: Ibf0ff3b8a4eeece853916e4e19d67fcc7ae2e989 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/419909 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* pyro/snappy: Do not discharge on AC when battery is still waking upBruce2017-01-022-50/+82
| | | | | | | | | | | | | | | | | | | Follow reef setting. discharges on AC till the charger is detected and settled but when booting from the cut-off mode this will kill the power hence do not discharge on AC when battery is still waking up and settled. BUG=none BRANCH=reef TEST=make buildall Change-Id: I09d8f5a363d20bb3d0df80694de52ae3a37a0ed9 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/422621 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* reef: Cleanup battery codeVijay Hiremath2017-01-021-120/+98
| | | | | | | | | | | | | | | Removed redundant code and clubbed variables. BUG=chrome-os-partner:61173 BRANCH=none TEST=Battery info works. Change-Id: I8d53df0d98aa5607db7cdc62223dc804b452dc59 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/424321 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* smart_battery: Cleanup smart battery & SB users codeVijay Hiremath2017-01-028-116/+81
| | | | | | | | | | | | | BUG=chrome-os-partner:61173 BRANCH=none TEST=Manually tested on Reef. Battery info works. Change-Id: I6e867eee38885186f8e63a934f52e826f0cf72fd Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/422998 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* electro: Add BQ40z555 Sony battery parameters as in the specVijay Hiremath2017-01-021-10/+34
| | | | | | | | | | | | | | BUG=chrome-os-partner:59904 BRANCH=none TEST=Tested on Reef by manipulating the elctro configs as reef and observed correct charging profile is selected. Change-Id: Ib155ea5aa3ab48b4853ba401a783d42d25fbea99 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/422430 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* charger_profile: Add common code for charger profile overrideVijay Hiremath2017-01-028-179/+391
| | | | | | | | | | | | | | | | | | | Added common code for charger profile override for fast charging. Fast charging configs can be defined in the respective board battery file and use the common code for imposing the custom data. BUG=chrome-os-partner:59393 BRANCH=none TEST=Enabled the config on Reef. Manually overrode the temperature and voltage. Observed correct charge profile config is selected for each tests. Change-Id: I075d271258470b98d38e4d5395d749469d3fd469 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/407928 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* stm32: Remove unused struct definitionsMartin Roth2017-01-022-10/+0
| | | | | | | | | | | | | | | The code that referenced these structure definitions was removed months ago. GCC 6.2 warns about the structures being definte but not used. BRANCH=none BUG=none TEST=Build tested only Change-Id: I68de7cc351667b3fb51aa9004dfc86d936f4a9cc Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424432 Reviewed-by: Shawn N <shawnn@chromium.org>
* eve: Enable CONFIG_PWM_KBLIGHT and fix volume buttonsDuncan Laurie2017-01-022-2/+3
| | | | | | | | | | | | | | | | - Enable keyboard backlight configuration option so the keyboard backlight interface is present. - Enable interrupt on both directions for volume buttons, otherwise we see the press but not the release. BUG=chrome-os-partner:58666 BRANCH=none TEST=manual testing on P1 board Change-Id: If0b6a913bb63f31051ab5a30ffe9f0682550e058 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/424493 Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* driver: temp_sensor: Add support for TI TMP112 sensorMoritz Fischer2016-12-303-0/+112
| | | | | | | | | | | | | | | Add support for the Texas Instruments TMP112 I2C temperature sensor. The sensor provides a single temperature value. BUG=none BRANCH=none TEST=Ran 'temp' console command over and over. Verified values with digital thermometer. Change-Id: Ida4c082309d245c3f7c6282ecea74ce5af746e43 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: https://chromium-review.googlesource.com/418488 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eve: Do not attempt to set 1.5A USB configDuncan Laurie2016-12-301-1/+2
| | | | | | | | | | | | | | | | The EC attempts to limit USB ports to 1.5A if a device is plugged into both ports, but this ends up with no power to the ports instead. Until this can be debugged with the right equipment just pretend we can do 3A to both ports so factory tests can pass. BUG=chrome-os-partner:61431 BRANCH=none TEST=plug device into both ports on P1 board and see that they work Change-Id: Icd4430d0026dc323e56b7ce88b9d8e79e6e825c5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/424453
* pyro/snappy: Discharge on AC till charger is detectedBruce2016-12-294-2/+32
| | | | | | | | | | | | | | | | | | | Follow reef setting. To avoid inrush current from the external charger, enable discharge on AC till the new charger is detected and charge detect delay has passed. BUG=none BRANCH=reef TEST=make buildall Change-Id: Ie4e249a3f8cc3140b99a944e5f252cdbaef4cab3 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/423277 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Revert "servo_v4: Remove PSTATE to create more space in RO"Nick Sanders2016-12-292-13/+2
| | | | | | | | | | This reverts commit 7ed9a96cd7247e66d60464bb7737c139d71e7395. Change-Id: Ifb3c31d04c8ff10c6186370c98ab127295b0f117 Reviewed-on: https://chromium-review.googlesource.com/422478 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* test: sort test names in build.mkVadim Bendebury2016-12-291-12/+39
| | | | | | | | | | | | | | This is a purely cosmetic patch making it easier to maintain the list of test in the ec tree. BRANCH=none BUG=none TEST=make buildall -j succeeds Change-Id: I2f0407c99776ad9d66445ea177a707bdfaa9b815 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424175 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* fix memory size calculations in host/test modeVadim Bendebury2016-12-281-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The common/system.c:system_usable_ram_end() function is used to determine how much room there is available for shared memory. This assumes that the jdata container is located at the top of SRAM right below the panic data buffer. This correct for embedded mode, but when building for host, panic structure is allocated in a different memory block, not necessarily adjacent to the __shared_mem_buf array. This leads to incorrect calculations of the available shared memory amount. Let's make sure the two memory blocks are adjacent, this way the available memory calculations are accurate. BRANCH=none BUG=none TEST=verified that make runtests -j succeeds, including the new test for malloc/free from shared memory (coming up in the next patch). Change-Id: I1fdba0512ac5a85b113a8284216c8b00f1564a94 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424176 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "servo_v4: Added initial USB PD support for both CHG/DUT ports"Scott Collyer2016-12-287-595/+12
| | | | | | | | | | | This reverts commit 167f7e51d8e7693a277077d6c24294d2997e1c55. This CL followed https://chromium-review.googlesource.com/#/c/422450/ which needs to be reverted because PSTATE is required for keeping serial numbers. Change-Id: Icb26043e1ce3145a9d9d5ad159dc709e6b8bf98d Reviewed-on: https://chromium-review.googlesource.com/422480 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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