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* pdchipinfo: Add option to force renewalDaisuke Nojiri2017-02-147-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | This change adds an option to pdchipinfo command to force ec to get the version from the chip instead of the cache (if it's available). This option will be used after firmware update, which makes the cache value stale. BUG=chrome-os-partner:62383 BRANCH=none TEST=Run ectool as follows: localhost ~ # /tmp/ectool pdchipinfo 0 on vendor_id: 0xaaaa product_id: 0x3429 device_id: 0xad fw_version: 0x15 localhost ~ # /tmp/ectool pdchipinfo 1 on EC result 2 (ERROR) Change-Id: Icefe96d7fc1208b991a4caa13aaf4f04052edba7 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/441271 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pdchipinfo: Increase compatibility of fw_versionDaisuke Nojiri2017-02-145-17/+33
| | | | | | | | | | | | | The firmware version formats may vary chip to chip. fw_version field is changed to a union of a 8 byte string and an 64-bit integer. BUG=chrome-os-partner:62383 BRANCH=none TEST=ectool pdchipinfo 0/1 on Electro Change-Id: Id51e66c44338a09ed897ee61f54cd6a394400e63 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/441270
* kevin / gru: Add BC1.2 charge rampShawn Nematbakhsh2017-02-144-1/+61
| | | | | | | | | | | | | BUG=chrome-os-partner:54099 BRANCH=reef, gru TEST=Verify charge_ramp success with a variety of BC1.2 chargers. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0e8bbd063e0933893a4a7f48a15a391c0ad9898a Reviewed-on: https://chromium-review.googlesource.com/435562 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* gru: Remove console commands to free yet more code RAMShawn Nematbakhsh2017-02-141-0/+6
| | | | | | | | | | | | | BUG=chrome-os-partner:54099 BRANCH=gru TEST=With subsequent patches, verify charge_ramp success with a variety of BC1.2 chargers. Change-Id: I461c736710b4d877988ae54c1059b30808ca5e16 Reviewed-on: https://chromium-review.googlesource.com/442166 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* eve: Move DPTF tablet mode support to common codeGwendal Grignou2017-02-143-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable ACPI to retrieve the tablet mode switch status. BUG=chrome-os-partner:62223 BRANCH=eve TEST=With evtest, check we receive tablet switch event. ... /dev/input/event4: Tablet Mode Switch ... Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 1 (SW_TABLET_MODE) Properties: Testing ... (interrupt to exit) Event: time 1486670351.311647, type 5 (EV_SW), code 1 (SW_TABLET_MODE), value 1 Event: time 1486670351.311647, -------------- SYN_REPORT ------------ Event: time 1486670352.574079, type 5 (EV_SW), code 1 (SW_TABLET_MODE), value 0 Event: time 1486670352.574079, -------------- SYN_REPORT ------------ ... Change-Id: I5db6aa2c113bbd2b8e8d8fe0c55551e1edac0c79 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/440405 Commit-Ready: Duncan Laurie <dlaurie@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hammer: Do not use a dedicated pstate bank.Nicolas Boichat2017-02-141-0/+3
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:61671 TEST=Boot hammer, flashinfo/flashwp work as intended. Change-Id: Ib316e036af613519f4b5f58b3a05bab5a880ce84 Reviewed-on: https://chromium-review.googlesource.com/441547 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: Disallow console unlocking for prod images.Aseda Aboagye2017-02-141-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | With this change, only DEV images will have the capability to unlock the Cr50 console. BUG=chrome-os-partner:62727 BRANCH=None TEST=Build a prod image, flash Cr50, try to unlock the console. Verify that access is denied and console remains locked. TEST=Attempt to read EC and AP flash over ccd. Verify that it fails. TEST=Remove AC and battery. Plug in AC. Verify that console is still locked. TEST=Plug in AC, unplug battery, verify that write protect is disabled. Verify that console is still locked and cannot be unlocked. TEST=Build a dev image, verify that console can be locked and unlocked. Change-Id: Ic47aa34f42ee295e74ba3a40b709ac42c34a30b7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/439764 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* lis2dh: code cleanupGwendal Grignou2017-02-135-75/+72
| | | | | | | | | | | | | | | | | | | | | Make FIFO a stack variable to save static memory, Remove auto_inc argument, always set Remove constant for rate 0. Force board to declare sensor private data. Avoid name collision in stm_mems_common Include stm_mems_common.h in accel_lis2dh.h, caller only need to include accel_lis2dh.h. BUG=none BRANCH=none TEST=Compile with discovery_stmems board. Change-Id: Id52b54dd4ec3cf217247c5511ad5a506067ad293 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/441144 Tested-by: mario tesi <mario.tesi@st.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: mario tesi <mario.tesi@st.com>
* kevin / gru: Reduce SRAM footprintShawn Nematbakhsh2017-02-135-56/+27
| | | | | | | | | | | | | | | Remove console commands and add CONFIG options to reduce RAM usage. BUG=chrome-os-partner:54099 BRANCH=gru TEST=Verify charge_ramp CONFIG + task builds for gru. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I2d7bc77d1fc032c6cb75eb1ec8d13dacb676658d Reviewed-on: https://chromium-review.googlesource.com/437662 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* eve: Revert trackpad interrupt changesDuncan Laurie2017-02-132-2/+1
| | | | | | | | | | | | | The trackpad interrupt is input only to the EC and should not ever be driven from here. BUG=chrome-os-partner:58666 BRANCH=none TEST=build and boot on eve p1 Change-Id: I3ffa2ddb4990550b57c9191b5d721ab0ba206aca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/439829
* flash: Pass more precise parameter to flash_[physical_]protect_at_bootNicolas Boichat2017-02-128-88/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding the rollback protection block, pass EC_FLASH_PROTECT_RO/ALL_AT_BOOT to flash_[physical_]protect_at_boot, instead of an enumeration no protection/RO/ALL. This will later allow us to protect/unprotect the rollback region only, by adding a EC_FLASH_PROTECT_ROLLBACK_AT_BOOT flag. BRANCH=none BUG=chrome-os-partner:61671 TEST=Build hammer with CONFIG_CMD_FLASH command, so that write protection can be checked with flasherase/flashwrite. TEST=On hammer (stm32f072): flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp rw; reboot => RO+RW protected flashwp norw; reboot => only RO protected TEST=On reef (npcx): deassert WP, flashwp false; flashinfo => RO+RW not protected flashwp true => only RO protected reboot => only RO protected flashwp rw => RO+RW protected reboot => only RO protected Change-Id: Iec96a7377baabc9100fc59de0a31505095a3499f Reviewed-on: https://chromium-review.googlesource.com/430518 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: Added Poppy and Rowan strap options to config tableScott2017-02-121-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Poppy uses SPI, Plt_Rst, and USB to AP. Its strapping option is 1M PU on both DIOA9|DIOA1 which gives it a strap_config value of 0xA. Rowan uses I2C and it's strapping option is 5k PD on DI0A12 and 5k PU on DI0A6 which gives it a strap_config value of 0x30. BRANCH=none BUG=chrome-os-partner:59833 TEST=manual Used H1 dev board with external PU/PD resistors to replicate both the Poppy and Rowan configurations. With Poppy config console shows: [0.004468 Valid strap: 0xa properties: 0x45] With Rowan config console shows: [0.004460 Valid strap: 0x30 properties: 0x2] Change-Id: I569960114c6f1844a55912fbf7f3d97008f9f71f Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/428000 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Do not silently ignore invalid attempts to use raiden programmerVadim Bendebury2017-02-111-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When --raiden is passed as a command line parameter, do not proceed programming as if it were not present, alert the user and refuse to proceed instead. Need to jump though a couple of extra hoops to avoid printing the error message twice. BRANCH=none BUG=none TEST=tried running with boards supporting and not supporting programming over CCD. $ ./util/flash_ec --board=oak --raiden --image rowan.ec.bin INFO: Using ec image : rowan.ec.bin ERROR: raiden mode not supported on oak $ ./util/flash_ec --board=kevin --raiden --image rowan.ec.bin INFO: Using ec image : rowan.ec.bin INFO: Flashing chip npcx_spi. INFO: Using raiden debug cable. ... Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ia40f348e6dde57fc2f4c49719bc2a0947036dcc1 Reviewed-on: https://chromium-review.googlesource.com/440051 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* PD: Remove CONFIG_USB_PD_TCPC_FW_VERSIONDaisuke Nojiri2017-02-1111-82/+0
| | | | | | | | | | | | | | | This removes CONFIG_USB_PD_TCPC_FW_VERSION. board_print_tcpc_fw_version is removed since it's no longer called. PD chip info is printed in usb_pd_protocol.c. BUG=none BRANCH=none TEST=buildall. Boot Electro, verify chip info is printed. Change-Id: I2ff860c2a1b17ceea124644ba8feb356b9cca2eb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/434911 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ANX74xx: add TCPC low power mode for different DRP stateKevin K Wong2017-02-113-17/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added code to put the ANX74xx in low power mode for different DRP state. 1. When nothing attached or system is in S3 or S5 disable the auto toggling and put ANX74xx system in Analog control mode. 2. Using the CABLE_DET interrupt pin (attach event) enable normal power mode. BUG=chrome-os-partner:59841, chrome-os-partner:61640 BRANCH=None TEST=Manually tested on Reef using below dut-control command dut-control pp3300_pd_a_mw -r <n> 1. S0, S3, S5 - Nothing connected, ANX in low power mode. 2. In S0 SNK (display/USB dongle, eMark cable) connected & put system to S3, ANX remains in normal mode. 3. In S0 SNK connected & put system to S5, ANX in low power** mode. 4. In S0 nothing connected, put system to S3 or S5, attach SNK, ANX in low power** mode. 5. Attach SNK at S3/S5 & boot to S0, ANX in normal mode. 6. SRC (AC adapter) with/without eMark cable are detected in S0, S3, S5, and continue to charge the system after S-state transition. low power**: ANX74xx hardware limitation that Ra/Open (Ex: E-Mark cable only) detection will trigger CABLE_DET continuously, therefore ANX74xx will go to normal power mode momentarily and then low power mode in a loop. Change-Id: I30f7fd7a85e31987fb77e2cab2fe140d59dd3629 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/415580 Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* console: Add non-verbose print config optionShawn Nematbakhsh2017-02-1117-21/+70
| | | | | | | | | | | | | | | | | Shorten certain long prints and reduce the precision of timestamp prints when CONFIG_CONSOLE_VERBOSE is undef'd. BUG=chromium:688743 BRANCH=gru TEST=On kevin, cold reset the EC, boot to OS, and verify cros_ec.log contains all data since sysjump and is < 2K bytes (~1500 bytes). Change-Id: Ia9390867788d0ab3087f827b0296107b4e9d4bca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438932 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Ensure PD is interrupted on EC resetShawn Nematbakhsh2017-02-111-0/+30
| | | | | | | | | | | | | | | | | | | | | If PD is negotiated and the EC is reset, a source partner port will continue providing its negotiated voltage (eg. 20V in the case of zinger). Ensure the partner port is in a known state by providing Rp for a brief period after resetting to RO. BUG=chrome-os-partner:62281 BRANCH=Reef TEST=On kevin, attach zinger, wait for 20V negotiation, and press F3 + power to cause EC reset. Verify VBUS drops to approximately 0V before going back to 5V / 20V. Verify the same with kevin OEM charger as well. Also verify kevin boots with no battery. Change-Id: I1b769a76188d8a9a515388996fbc4cb3d46840a5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/433367 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* jerry: Increase HC task stack size.Aseda Aboagye2017-02-101-1/+1
| | | | | | | | | | | | | | | | With ToT images, we were hitting a stack overflow in the host command task. BUG=none BRANCH=none TEST=disable EC SW sync, flash jerry, verify it boots to login screen. Change-Id: I978b768c1619b4f0dfe862e96c31a91cebce8b87 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/440396 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shelley Chen <shchen@chromium.org>
* Reef: Set RW boot power threshold to 18wDaisuke Nojiri2017-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Electro is able to boot on 15w to Depthcharge but requires 18w or above to boot to the logon screen. This patch allows 15w charger to boot Electro to Depthcharge (as before) but prevents it from booting after that unless the EC in RW negotiates with the charger and gets 18w or more. Without the patch: 1. Boot without battery 2. EC sysjumps to RW 3.a. With 18w charger, Depthcharge proceeds to boot b. With 15w charger, Depthcharge proceeds then browns out 4. Boot without battery 5. Reboot by FSP for RTC well drop 6. Charger goes to disabled state 7. EC fails to negotiate with charger, hard resets charger 8. Brownout 9. Repeat from #4 With the patch: 1. Boot without battery 2. EC sysjumps to RW 3.a. With 18w charger, Depthcharge proceeds to boot b. With 15w charger, Depthcharge times out and shuts down the system So, the outcome is same. With the patch, the user at least is (or will be) given a chance to know battery is the problem. I suppose we have to add a screen showing battery is drained or dead. I currently see no such code in vboot_select_and_load_kernel. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chrome-os-partner:61801 BRANCH=none TEST=Hack the code to enforce syslock. Disconnect battery. Use 18w charger to boot the system. Use 15w charger not to boot. Change-Id: I00d79a96221f1d3b8c6d529de9b8e4588d6112aa Reviewed-on: https://chromium-review.googlesource.com/440390 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Reef-ish: Remove extra newline after board versionDaisuke Nojiri2017-02-103-3/+3
| | | | | | | | | | | | | | This removes the extra newline character after the board version from EC's debug output. BUG=none BRANCH=none TEST=Boot Electro. Change-Id: If6e365a7f175c7e8f2c8db5adbf1780f6715d615 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/441265 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* reef: Add SMP-C22N1626 battery configs as in specVijay Hiremath2017-02-102-3/+12
| | | | | | | | | | | | | | BUG=chrome-os-partner:60899 BRANCH=none TEST=Manipulated SonyCorp Battery as SMP-C22N1626 battery and observed correct charging profile is selected. Change-Id: I6da312e1f9c7c71241beca80a8fc202edfd5de91 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/438805 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* charger_profile: support multiple battery voltage range thresholdsVijay Hiremath2017-02-104-61/+88
| | | | | | | | | | | | | | | | | | | | Current fast charge assumes only one battery voltage threshold range for charger profile override. However we have multiple battery voltage threshold ranges for few batteries hence added a code which can consider multiple battery threshold ranges and choose respective charge profile. BUG=chrome-os-partner:62653 BRANCH=none TEST=Manually tested on Electro. Manipulate smp_cos4870 & sonycorp battery voltage & temperature ranges and observed correct charge profile is selected. Change-Id: Icddc047e608cc8f63cd0c19be716e0f7908ca715 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/438804 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* motion_lid: Fix merge of cl/430344Gwendal Grignou2017-02-101-3/+0
| | | | | | | | | | | | | | Fix merging that would send 2 hook_notify when tablet mode changes. BUG=none BRANCH=none TEST=buidall Change-Id: Ibf19cbbdf3ce28abe3314c0ce2c41a210c86d153 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/440404 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* snappy: BMI160 is powered down on board v3 and older in S3Gwendal Grignou2017-02-101-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Take in account that sensors are down in S3, reinit them back when moving from S3 to S0. Do this only for board version 3 and older. board v4 will have sensors powered in S3. BUG=chrome-os-partner:61502 BRANCH=reef TEST=Check EC power sensors up coming from S3 to S0: [1.627437 power state 6 = S3->S0, in 0x00cf] [1.627994 Port 80: 0x1001][1.628600 chipset -> S0] [1.637391 TCPC p1 Low Power Mode] [1.645020 Lid Accel: Done Init type:0x0 range:2] [1.647733 Lid Accel ODR: 10000 - roundup 1 from config 1 [AP 0]] [1.649015 TCPC p1 Low Power Mode] [1.662231 TCPC p1 Low Power Mode] [1.670560 Base Accel: MS Done Init type:0x0 range:2] C0 st15 [1.679813 PB task 6 = released] [1.680783 PB PCH pwrbtn=HIGH] [1.681108 PB task 0 = idle, wait -1] [1.683463 Base Accel ODR: 10000 - roundup 1 from config 1 [AP 0]] [1.686275 Base Gyro: MS Done Init type:0x1 range:1000] [1.697973 Base Gyro ODR: 0 - roundup 0 from config 0 [AP 0]] [1.776627 Base Mag: MS Done Init type:0x2 range:2048] [1.786490 Base Mag ODR: 0 - roundup 0 from config 0 [AP 0]] ... Change-Id: Icb9961a0f3ce1b478c47057716211e6e14c13674 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/428125 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 37e6fb246495ac972e0bc4ff6fcc16b9bf2eee7b) Reviewed-on: https://chromium-review.googlesource.com/440511 Commit-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org> Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: don't disable TPM_RST_L interruptMary Ruthven2017-02-101-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | x86 devices use TPM_RST_L to detect the AP state, so we set device_states[DETECT_AP].detect to GPIO_TPM_RST_L on those boards. board_update_device_state uses this signal to poll the AP state once a second to detect if the device is off. If for some reason TPM_RST_L is deasserted, but the tpm reset handler has not yet set the state to 'on', we will catch it when we poll the AP state with board_update_device_state. It will call device_state_on with TPM_RST_L. In that case device_state_on used to silently disable the TPM_RST_L interrupt and not change the AP state. This change modifies device_state_on to notify the tpm reset handler and prevent it from disabling the tpm reset interrupt. BUG=chrome-os-partner:62748 BRANCH=none TEST=disable the deferred_tpm_rst_isr call in configure_board_specific_gpios. Close the lid and wait 5 minutes. Open the lid. Verify cr50 prints "device_state_on: tpm_rst_isr hasn't set the AP state to 'on'" and the system boots normally. Change-Id: I6e5b722fab6e7b0acb91dda0e5207e4411e97363 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/439816 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* pyro: Disable Trackpad in S5 to save powerHarry Pan2017-02-101-0/+6
| | | | | | | | | | | | | | | Follow CL:433083, integrate this to children. BUG=chrome-os-partner:59712,chrome-os-partner:62642 BRANCH=reef TEST=gpioget EN_P3300_TRACKPAD_ODL is 1 in S5 & below, 0 otherwise. Change-Id: I79250b8f8765fbcee065f673b1c02afff123abdf Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/438780 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add host command to get PD chip informationDaisuke Nojiri2017-02-0911-28/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a host command to get PD chip info. For PS8751, tcpci_get_chip_info will fail if the chip is in low power mode. It can be woken up by reading a random register first then wait for 10ms. This code doesn't have the wake-up read to avoid 10ms delay. Instead, we call this function immediately after the chip is initialized because it'll gurantee the chip is awake. Once it's called, the chip info will be stored in cache, which can be accessed by tcpc_get_chip_info without worrying about chip states. localhost ~ # ectool pdchipinfo 0 vendor_id: 0xaaaa product_id: 0x3429 device_id: 0xad fw_version: 0x15 localhost ~ # ectool pdchipinfo 1 vendor_id: 0x1da0 product_id: 0x8751 device_id: 0x1 fw_version: 0x37 BUG=chrome-os-partner:62383 BRANCH=none TEST=ectool pdchipinfo 0/1. make buildall Change-Id: I3f1667d00ce1826936d90882ada1df6ed6b0ea37 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/433166
* cr50: Use BATT_PRES_L as source of write protect.Aseda Aboagye2017-02-095-10/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the Cr50 write protect behaviour to simply follow the state of the battery present pin. The state can still be overridden both ways by using the `wp` console command. A user can either force write protect enabled or force write protect disabled. Additionally, the behaviour can be reset to follow the state of the battery pin by issuing `wp follow_batt_pres`. However, the ability to force the write protect state requires an unlocked console. BUG=chrome-os-partner:62726 BRANCH=None TEST=Plug in battery, verify that WP is enabled. Plug in AC and unplug battery, verify that WP is disabled. TEST=Unplug battery, unplug AC, plug in AC, verify that WP is disabled. TEST=Unplug battery, verify that WP is disabled. Use `wp' command to enable WP, verify that it is enabled. TEST=Plug in battery, disable WP using `wp` command, put cr50 into deep sleep, wake it up, verify that WP is still disabled. TEST=Plug in AC, plug in battery, disable WP using `wp` command, unplug and plug battery connector, verify that WP is still disabled. Change-Id: I83d9820067800801ddbde311eab0853c3c2216d3 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/439485 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chip/npcx/espi: Handle global reset events asserting eSPI_Reset#Furquan Shaikh2017-02-093-0/+22
| | | | | | | | | | | | | | | | | | | | | | In case there is a sudden power loss to PCH, then there are no eSPI VW messages sent from the PCH to EC indicating power state transition into S5. Instead, the eSPI compatibility spec defines such events as global reset events. For global reset events, eSPI_Reset# signal is asserted without SLP_SUS# being asserted. This acts as an indication to the EC that there was a global reset event. Add a callback chipset_handle_espi_reset_assert that takes any necessary action whenever eSPI_Reset# pin is asserted. On skylake, it would check if power button was being pressed and release the button. BUG=chrome-os-partner:62014 BRANCH=None TEST=Verified that apshutdown works as expected. Change-Id: I409afa0d00faca55ae3aa577743cedac58d4d877 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438935 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* rowan: enable CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMITYidi Lin2017-02-091-0/+1
| | | | | | | | | | | | | BRANCH=master BUG=chrome-os-partner:62673 TEST=EC_FIRMWARE=rowan emerge-rowan chromeos-ec Change-Id: I16b5584380abac7f32aecd9bcf87ec5dc0123107 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/427565 Commit-Ready: Patrick Berny <pberny@chromium.org> Tested-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* rowan: Add ISL29035Yidi Lin2017-02-093-1/+20
| | | | | | | | | | | | | | | Add ambient light sensor support for rowan. BRANCH=master BUG=chrome-os-partner:62673 TEST=EC_FIRMWARE=rowan emerge-rowan chromeos-ec Change-Id: Idfc34bd7977c96ac245a6d06cab064e65b8bf72a Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/427564 Commit-Ready: Patrick Berny <pberny@chromium.org> Tested-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* rowan: config SPI pinsYidi Lin2017-02-091-6/+3
| | | | | | | | | | | | | | | Configure B12/B13/B14/B15 as SPI pins. BRANCH=master BUG=chrome-os-partner:62673 TEST=EC_FIRMWARE=rowan emerge-rowan chromeos-ec Change-Id: Ia7aad9ba0e15a8e6b623a8ae37f76db3f8f7c7a5 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/427563 Commit-Ready: Patrick Berny <pberny@chromium.org> Tested-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* rowan: GPIO configurationYidi Lin2017-02-095-126/+30
| | | | | | | | | | | | | | | | | | | | | | Configure GPIO pins according to Rowan's design. Leave following pins unconfigured for now. - CCD_MODE_ODL - EC_HAVEN_RST_ODL - OTG_EN_EC - VOLUME_UP_IN_SOC_R - VOLUME_DOWN_IN_SOC_R BRANCH=master BUG=chrome-os-partner:62673 TEST=EC_FIRMWARE=rowan emerge-rowan chromeos-ec Change-Id: Icd5113a7ba1903d1e8eb7930c606dde2418fdc61 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/427562 Commit-Ready: Patrick Berny <pberny@chromium.org> Tested-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* rowan: remove keyscan task to remove the keyboard supportYidi Lin2017-02-091-1/+0
| | | | | | | | | | | | | | | | | Rowan does not have the keyboard. Remove keyscan task to remove the keyboard support. BRANCH=master BUG=chrome-os-partner:62673 TEST=EC_FIRMWARE=rowan emerge-rowan chromeos-ec Change-Id: I802dd4073cabaa71c2655cc654efe3669f6ed083 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/427561 Commit-Ready: Patrick Berny <pberny@chromium.org> Tested-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* rowan: Add initial support for rowanYidi Lin2017-02-098-0/+1609
| | | | | | | | | | | | | | | | Copied from elm with string updated. BRANCH=master BUG=chrome-os-partner:62673 TEST=EC_FIRMWARE=rowan emerge-rowan chromeos-ec Change-Id: I424e9ea1cb1520766222eff3156da5f6edbcc2fd Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/427560 Commit-Ready: Patrick Berny <pberny@chromium.org> Tested-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* cr50: call tpm_rst_isr if we missed the edge during initMary Ruthven2017-02-091-1/+11
| | | | | | | | | | | | | | | | After configuring tpm_rst_l to be connected to the correct pin, check the level of GPIO_TPM_RST_L to make sure we did not miss the rising edge. If we did then call the tpm reset handler BUG=chrome-os-partner:62748 BRANCH=none TEST=verify electro boots, close the lid, wait 5 minutes, open the lid and verify it still boots Change-Id: I1a229fa53664767f0e5cad5f80285f5f030f2197 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/439879 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Snappy: Recondition USB3.0 RXDaisuke Nojiri2017-02-093-3/+21
| | | | | | | | | | | | | | | | | | The loss between PS8751 and Type-C connector is large and requires a larger EQ and low squelch threshold for compensation. - USB Type-c connector facing receiver equalization setting: Compensate for channel loss up to 10.9dB - High Speed Signal Detector threshold adjustment: -25% BUG=chrome-os-partner:61101 BRANCH=none TEST=Boot & charge Change-Id: Ie74e2d0b8ad7206f5e60fb013613c382980c0eac Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/433846 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: reenable ap uart on servo disconnectMary Ruthven2017-02-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ap uart tx signal is disconnected if servo is attached, but it is never reconnected when servo is detached. The 'ccd uart enable' command only reconnects the EC uart tx signal, so if servo is detached the only way to reenable ap uart tx is to detach and reattach suzyq. This can cause cr50 to lose some ccd state. This change reconnects the ap uart when servo is detached. BUG=none BRANCH=none TEST=manual disconnect servo attach suzyq verify the ap console is read write attach servo verify the ap console is read only detach servo verify the ap console is read write Change-Id: I11cdd932b14d968ec77b18adf93dd0d3808fb2e9 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/439704 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* hammer: Add GPIO_F to KB_OUT_PORT_LISTNicolas Boichat2017-02-092-1/+2
| | | | | | | | | | | | | | | | | | Without this, keyboard columns 10 and 11 do not work, as registers for port F are never set. Let's also remove port D, since we do not use it as part of the keyboard scanning. BRANCH=none BUG=chrome-os-partner:62751 TEST=flash hammer, all keys work. Change-Id: I0c07dc2420d7cd570ad8450c76f91a2bad9a50a5 Reviewed-on: https://chromium-review.googlesource.com/439908 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver: accel: Add acc driver basics and FIFO for LIS2DH/LIS2DH12Mario Tesi2017-02-097-0/+895
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for acc sensor ST lis2dh/lis2dh12 Support interrupt management for FIFO watermark Starting to share common code with other devices like lsm6dsm/lsm6dsl (acc/gyro) or new lis2mdl (mag) TODO: Add all embedded functions support (click, tap and so on) BUG=none BRANCH=master TEST=Tested on discovery BOARD with sensor connected on EC i2c master bus. Added motion sense task on discovery board task list, added gpio info in board configuration file and tested with motion sense console commands. Data for acc seems ok: can successfully change ODR and full scale range. Also FIFO and interrupt tested Device tested is lis2dh (lis2dh12 simply differs for low pin count but share the same registers) Change-Id: I16abeac3f139a604094b38d8d8b857a62c93a242 Signed-off-by: Mario Tesi <mario.tesi@st.com> Reviewed-on: https://chromium-review.googlesource.com/412700 Commit-Ready: mario tesi <mario.tesi@st.com> Tested-by: mario tesi <mario.tesi@st.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* snappy: Disable Trackpad in S5 to save powerHarry Pan2017-02-081-0/+6
| | | | | | | | | | | | | Follow CL:433083, integrate this to children. BUG=chrome-os-partner:59712,chrome-os-partner:62641 BRANCH=reef TEST=gpioget EN_P3300_TRACKPAD_ODL is 1 in S5 & below, 0 otherwise. Change-Id: I86716e95d7a32c44df9fe46419dccd842eb7dd48 Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/438779 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* common/spi_nor: Differential erase supportNadim Taha2017-02-092-45/+109
| | | | | | | | | | | | | | | | | | | | If CONFIG_SPI_NOR_SMART_ERASE is defined will read the sector/block to be erased first and only initiate the erase operation if not already in an erased state. The read operation (performed in CONFIG_SPI_NOR_MAX_READ_SIZE chunks) is aborted early if a non "0xff" byte is encountered. Reduced erase time of a mostly erased EEPROM from 44s to 20s (16MB Winbond part) / 1m22s to 40s (32MB Macronix part) @24MHz. BUG=None BRANCH=None TEST=Built all targets. Successfully flashed various EEPROM images. Change-Id: I369b1fcf72140663b8dbce5a469ebad27f7571ec Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/437988 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* commom: enable commits prior to checking for valid nvmem partitionsScott2017-02-081-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If both nvmem partitions are corrupted, then nvmem_reinitialize() will be called and commits must be enabled prior to this so that nvmem_release_cache() succeeds. BRANCH=none BUG=chrome-os-partner:62531 TEST=On Reef after a successful boot, corrupt nvmem partitions using the following console commands: flasherase 0x7d000 0x3000 flasherase 0x3d000 0x3000 Then reboot via H1 console and verified via the console that the nvmem partitions were reconfigured. nvmem_find_partition:302 partiton 0 verification FAILED nvmem_find_partition:302 partiton 1 verification FAILED [0.025928 nvmem_find_partition: No Valid Partition found, will reinitialize!] [0.127752 Active Nvmem partition set to 1] Then verfied that TPM was functional and the system booted booted into the kernel. Without this CL this set of actions would always result in going in to recovery mode due to TPM failure. Change-Id: If1691b179e19cb37f0fc6ba893219dd8c02f2cf5 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/439368 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: print reset count in sysinfoMary Ruthven2017-02-071-0/+4
| | | | | | | | | | | | | | | | | The reset count is very useful for debugging whether the tpm is locked or if the version rolled back. This change makes reading the value easier by adding it to the sysinfo command BUG=none BRANCH=none TEST=reboot cr50 8 times verifying the reset count value is correct each time and that sysinfo also shows a rollback is detected after the 7th boot. Change-Id: I94ac11a444ee73aa04bbdcc066c8e1c7a0a3ae8e Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438788 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* tcpm: it83xx: Add support for TYPEC_CC_OPENShawn Nematbakhsh2017-02-071-6/+27
| | | | | | | | | | | | | BUG=chrome-os-partner:62281 BRANCH=None TEST=Verify compilation on it83xx w/ IT83XX_PD_EVB = 1. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id82387e7d4782ed1a5e07f7968475988ff6da9d5 Reviewed-on: https://chromium-review.googlesource.com/434077 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: Check if inactive RW region needs to be invalidatedScott2017-02-071-2/+10
| | | | | | | | | | | | | | | | | | | | | | | There is no need to invalidate the inactive RW image if it's already been done. Check the magic area of the header and if already 0s, then set *response_size and return VENDOR_RC_SUCCESS. BUG=chrome-os-partner:62588 BRANCH=none TEST=manual Update H1 FW on Eve. Using 'ver' command verify that it has valid A/B RW images. Log into chromeos and see console messages indicating that inactive image is being invalidated and via 'ver' command. Reboot via H1 console and see that this time the message vc_invalidate_inactive_rw: Inactive region already corrupted is displayed. Change-Id: I0894d456fdc63f64fc7272ad55d75ba94dbe94c4 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438787 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* Revert "snappy: led: blink power led in once every 4 secs."Ravi Chandra Sadineni2017-02-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 21e2878a72000788d3c7e7c8e96e0cf9bb0edc08. Reason for revert: OEMS have flexibility over the LED requirements. Original change's description: > snappy: led: blink power led in once every 4 secs. > > Currently the led blinks once sec every 2 secs. But > as per the hardware reuqirements it should be one sec every 4 > secs. > > BRANCH=none > BUG=chrome-os-partner:62655 > TEST=Enter s0ix, s3 manually and make sure it blinks once > every 4 secs. > Signed-off-by: Ravi Chandra Sadineni <ravisadineni@google.com> > > Change-Id: I3ade6c5789c172c66dfb022cd12439752d96addc > Reviewed-on: https://chromium-review.googlesource.com/437601 > Commit-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org> > Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> > Reviewed-by: Aaron Durbin <adurbin@chromium.org> > TBR=bleung@chromium.org,adurbin@chromium.org,adurbin@google.com,moch@google.com,moch@chromium.org,ravisadineni@chromium.org,philipchen@chromium.org,bleung@google.com NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=chrome-os-partner:62655 Change-Id: I81307382774b643af9c2ae2b1682e0e5498b1472 Reviewed-on: https://chromium-review.googlesource.com/439364 Commit-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org> Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* eve: LED changesDuncan Laurie2017-02-071-5/+12
| | | | | | | | | | | | | | | - Use amber for charge when in suspend/off states and leave red to indicate something is wrong. - Blink non-charging LED in S0ix/S3 states. BUG=chrome-os-partner:60797 BRANCH=none TEST=verify led operation in s3/s5 while charging Change-Id: I16660942bf93f7cf6c951c19548c1c6838aabb72 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/438707 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* hammer: Enable PWM output for keyboard backlightNicolas Boichat2017-02-072-1/+19
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:59083 TEST=make BOARD=hammer -j Change-Id: Ibbf82c6c0f8115cbf611c74fc0585e97850d2019 Reviewed-on: https://chromium-review.googlesource.com/430575 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* hammer: Update pin layoutNicolas Boichat2017-02-071-27/+34
| | | | | | | | | | | | | | Previous layout was temporary, on an evaluation board. BRANCH=none BUG=chrome-os-partner:59083 TEST=make BOARD=hammer Change-Id: I14478b9613e4e481bbdc71e595d218d585fbd8e5 Reviewed-on: https://chromium-review.googlesource.com/430574 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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