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* common/button: Blink LED for 3 seconds when setting recovery HW_REINITstabilize-9517.BFurquan Shaikh2017-05-021-0/+29
| | | | | | | | | | | | | | | If user holds down volume up, volume down and power button for 30 seconds, set HW_REINIT event and blink LED for 3 seconds to indicate to user that the request was accepted. BUG=b:37682514 BRANCH=None TEST=make -j buildall Change-Id: I6b70d56f50d0a1cfae3fa7f337a34ac487943775 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/487281 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* common/led_common: Add API for controlling LED stateFurquan Shaikh2017-05-024-1/+28
| | | | | | | | | | | | | | | 1. Provide led_control API that can be used by different drivers to control the state of LED (0=off, 1=on, 2=reset) 2. Add a new LED ID for recovery HW_REINIT indication. BUG=b:37682514 BRANCH=None TEST=make -j buildall Change-Id: I27334bde2b879046746456a610208f3fc2dd68b4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/487840 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* common/button: Add support for HW_REINIT button comboFurquan Shaikh2017-05-021-0/+37
| | | | | | | | | | | | | | | | | | | | | | | If volume up + volume down + power buttons are held down for 30 seconds, then indicate to AP that HW_REINIT is requested by the user. Since recovery mode is triggered by holding down the three buttons for 10 seconds, button_check_hw_reinit_required checks for 20 more seconds only. BUG=b:37682514 BRANCH=None TEST=Verified that: 1. If volume up, volume down and power are held for 30 seconds, AP sees the hw reinit request. 2. If either of the buttons is released before 30 seconds, AP does not see the hw reinit request. Change-Id: I3a53966dcdcb84d73f160578411b6c0f62225b95 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/487002 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* usb_updater: do not filter out dev cr50 versionsVadim Bendebury2017-05-021-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The usb_updater code comparing versions to decide which one is newer filters out values in excess of 1000 to not consider dev build versions to be newer than the released versions. In fact this logic is flawed: with node locked RO it is possible to build dev (self signed) version, which can run on the device, and this version should take over the released version, if it is currently present on the device. If the RO is not node locked, the dev RW version will not verify, so it is safe to download it to the chip, it would be ignored. BRANCH=cr50 BUG=none TEST=with this patch applied it is possible to update self signed versions running on H1 (the updater considers them newer than 0.0.18 and sends the chip the vendor command to enable the downloaded image after download completes). Change-Id: Ibb5761e4bb24fcc7dee5cc10b2f26af7a8e9aa2e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/492087 Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: use 2048 bit key for autosigned imagesVadim Bendebury2017-05-021-37/+25
| | | | | | | | | | | | | | | | | | | | | | | The node locked ROs expect the RW image to be self signed with a 2048 bit key. The only case where loader-testkey-A.pem file is used is is building vanilla images which can't even run any more (they used to be good for old dev RO). Let's replace the 3072 bit key with a 2048 bit key generated by running 'openssl genrsa -3 2048 > util/signer/loader-testkey-A.pem' BRANCH=none BUG=none TEST=verified that RW signed with this key can be run by a node locked RO. Change-Id: I74d189d03acb663fde7db48815e54748163c6399 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/489434 Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* power/intel_x86: add tablet switch event wake masksArchana Patni2017-05-021-8/+10
| | | | | | | | | | | | | | | | | | | | | The wake mask programming for S0ix is done in EC. This patch adds handling for the tablet switch events in the S0ix flows. BRANCH=none BUG=b:37223093 TEST=attach or detach base and check if event is generated Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Jenny TC <jenny.tc@intel.com> Change-Id: Ibd53e85d5a3a1b776e519b70860404684c9ab0fb Reviewed-on: https://chromium-review.googlesource.com/486462 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* it83xx: clock: misc fixesDino Li2017-05-021-46/+4
| | | | | | | | | | | | | | | | | | | | | 1. Disable USB debug interface: If we don't use GPIOH.5/6 pins for debugging, we should disable it to prevent any chances of entering debug mode. 2. command_idle_stats() behind CONFIG_CMD_IDLE_STATS: We can exclude this console command if we don't use it. 3. Remove 'dsleep' console command: DEEP_SLEEP_ALLOWED macro is enough for us. BRANCH=none BUG=none TEST=bit7 at 0xF02030(MCCR register) is cleared after initialization. Change-Id: If34e9738351459891be8c9a6619384adbfe26335 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/487843 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/usb_update: Add support for UPDATE_EXTRA_CMD_UNLOCK_ROLLBACKNicolas Boichat2017-05-022-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AP will use that command to tell base EC that it believe the current FW is functionning correctly, and that the rollback region can be unlocked for an update on the next reboot. BRANCH=none BUG=b:35586219 BUG=b:35587171 TEST=- Flash hammer ToT image with rollback version 0 > flashwp true; reboot > flashinfo => all flash is protected - Update CONFIG_ROLLBACK_VERSION to 1 $ make BOARD=hammer -j - Flash new RW $ sudo extra/usb_updater/usb_updater2 -w $ sudo extra/usb_updater/usb_updater2 -r $ sleep 0.5 $ sudo extra/usb_updater/usb_updater2 -s $ sudo extra/usb_updater/usb_updater2 build/hammer/ec.bin > rollbackinfo rollback minimum version: 0 RW rollback version: 1 - Tell RW to unprotect rollback $ sudo extra/usb_updater/usb_updater2 -u $ sudo extra/usb_updater/usb_updater2 -r > rollbackinfo rollback minimum version: 1 RW rollback version: 1 Change-Id: Ib52253e9b8bba872688d6f601d9bfad8862be25f Reviewed-on: https://chromium-review.googlesource.com/489889 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/usb_update: Support CMD_UNLOCK_RW even with CONFIG_RWSIG is unsetNicolas Boichat2017-05-021-1/+1
| | | | | | | | | | | | | | | | | | Starting with be294d4ef "hammer: Only define required options for RO and RW" we do not define CONFIG_RWSIG for the RW section. However, we want CMD_UNLOCK_RW to be usable when EC is in RW section, to unlock itself in prevision for an update on the next reboot. BRANCH=none BUG=b:35587171 TEST=Update hammer using usb_updater2 Change-Id: I7ae001363697bc3e17d4a59b21413d35101228cb Reviewed-on: https://chromium-review.googlesource.com/489888 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb_update: 1-byte response to extra commandsNicolas Boichat2017-05-021-1/+1
| | | | | | | | | | | | | | | The existing commands do not really need longer response code. Future commands can always reply with more data as needed. BRANCH=none BUG=b:35587171 TEST=Update hammer using usb_updater2 Change-Id: I37cb8ac444d58216a7d98c9090043b06d95c74e1 Reviewed-on: https://chromium-review.googlesource.com/489887 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb_port_power: Allow variable number of portsDaisuke Nojiri2017-05-016-59/+58
| | | | | | | | | | | | | | | | | Currently, usb_port_power_dumb allows fixed number of ports (2) and usb_port_power_smart allows less than 4 ports. This change removes the limitation and makes them accept variable number of ports. BUG=chromium:715178 BRANCH=none TEST=Verified usbchargemode returns consistent charge_mode across sysjumps on Electro. Change-Id: I7675c65ba03d3e6f7f53b2fe48cbe510231d945a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/481077 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rollback: Print RW rollback version as wellNicolas Boichat2017-05-011-0/+4
| | | | | | | | | | | | | | | This is useful for debugging, to understand if the RW rollback version is ahead of current rollback version. BRANCH=none BUG=b:35586219 TEST=Flash hammer, rollbackinfo in EC console Change-Id: I2634199845f1b35447e0938a35b862f79cb24ffa Reviewed-on: https://chromium-review.googlesource.com/489886 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tcpm: it83xx: added chip infoDino Li2017-05-012-1/+17
| | | | | | | | | | | | | | | We can get the correct chip info after the change was made. BRANCH=none BUG=none TEST=console message: [0.013915 TCPC p1 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec] [0.018054 TCPC p0 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec] Change-Id: I4eb94967acb351559e745ed1c4e34a4c58f41e14 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/487767 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* virtual_battery: Fix energy readingsDouglas Anderson2017-05-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The virtual battery "energy" readings were totally broken. Rather than reporting things in units of "10 mW" they were reporting things in units of "10 uW". That's because they were doing this math: result = mV * mA / 10 Said another way: result = (V / 1000) * (A / 1000) / 10 result = (V * A) / (100000) / 10 result = W / 1000000 / 10 result = uW / 10 Aside from the fact that clients were expecting things in "10 mW" instead of "10 uW", we got even more random results. That's because we return to the client in a 16-bit variable, so we were kinda randomly truncating things. Doh. BRANCH=ToT BUG=chromium:717304 TEST=power_supply_info Unfortunately when you try to report sane values for "10 uA" in a 16-bit result, it doesn't work too well ( Change-Id: I8075dffd7ab6b372be5b8fdf293acc96c5878036 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/492546 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 01ceab68cd6b542f8c6355425e6ac6da698e0ebf) Reviewed-on: https://chromium-review.googlesource.com/492568 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* iteflash: exit DBGR mode after flashingDino Li2017-05-011-11/+21
| | | | | | | | | | | | | | | | | | | This change is separated from CL:344481. We need a cold reset after flashing, but we kill 'servod' before execute iteflash for each flashing process. With this change, we can restart 'servod' again without errors. And we are able to use dut-control to do a EC cold reset. BRANCH=none BUG=none TEST=flashing completed, and wait for servo's cold reset. Change-Id: Ifc242467211253fabcd733a971e999baa68a1026 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/488002 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Remove board_print_tcpc_fw_version declarationDaisuke Nojiri2017-05-014-4/+0
| | | | | | | | | | | | | board_print_tcpc_fw_version is no longer called or defined. BUG=none BRANCH=none TEST=make buildall Change-Id: I11b625156c999eb811cc0298a1f2cad1a838088a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/491988 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* BD9995X: Enable/Disable charger depending on charging currentJames Chao2017-04-302-24/+39
| | | | | | | | | | | | | | | | | | | | | | If charging current is set to 0mA during charging, reference of charge current feedback amp (VREF_CHG) is set to 0V. Hence the DCDC stops switching (because of the EA offset). To eliminate this issue, disable/enable charger depending on the charging current is zero or non-zero respectively. BUG=b:37413065 BRANCH=reef TEST=test 'ectool chargecontrol normal/idle/discharge' are working Change-Id: Id31876afe365a476fb906e059ab519b7a0c9a7c6 Signed-off-by: james_chao <james_chao@asus.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/486101 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 6da9ed8786e90ee91b39934180fe84e01ac30260) Reviewed-on: https://chromium-review.googlesource.com/489812 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* common: add feature bit for touchpad supportWei-Ning Huang2017-04-273-0/+6
| | | | | | | | | | | | | | | | Add a new 'feature' bit to allow the host to auto-detect a TP MCU. Signed-off-by: Wei-Ning Huang <wnhuang@google.com> BRANCH=none BUG=b:37584134 TEST=on eve with TP connected, look at the feature bit. Change-Id: I81b30b96b31fc8dcb6769dd146fb33cdd487fddf Reviewed-on: https://chromium-review.googlesource.com/485422 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* rwsig: do not jump if reset source is hard pin resetWei-Ning Huang2017-04-272-3/+21
| | | | | | | | | | | | | | | | | | | According to the new MCU secure update model, EC should wait for host if reset source is reset-pin. BRANCH=none BUG=b:37584134 TEST=on rose, toggle reset pin from host. EC should stay in RO, showing [0.426089 Hard pin-reset detected, disable RW jump] in console. Change-Id: Ie1908cb0744773e2e3ca8b3d8c627b8a9ef4567f Reviewed-on: https://chromium-review.googlesource.com/485199 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* rwsig: add host command for getting rwsig statusWei-Ning Huang2017-04-273-0/+40
| | | | | | | | | | | | | | | | | | | Add a new host command EC_CMD_RWSIG_CHECK_STATUS for getting rwsig status and rw firmware hash. This command is used to check the RW signature of newly updated RW image. A new subcommand is also added to ectool. BRANCH=none BUG=b:37584134 TEST=on rose board `ectool rwsigstatus` works Change-Id: I33d8709f5248d3a4b8bedb36ded84a93dc8c971f Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/485079 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy: Enable low power idle modeNicolas Boichat2017-04-261-0/+1
| | | | | | | | | | | | | | | | | | Poppy should be able to use the low power idle mode for the npcx EC to get lower power in S3, and in S5 before we enter hibernate. BUG=b:36372576 BRANCH=none TEST=build and boot on poppy (with HW VBUS rework and HACK CLs), enter S3 or S5 and observe, using idlestats, that dsleep gets enabled after the 15 second console idle timeout. Change-Id: Ide656711ef87313aec396e34284982b77040dc23 Reviewed-on: https://chromium-review.googlesource.com/487921 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* i2c: separate slave and master codeWei-Ning Huang2017-04-263-21/+30
| | | | | | | | | | | | | | | | | | | | Split i2c.c code in two (i2c_slave.c and i2c_master.c). i2c_slave.c is used when EC has no i2c device connected (i2c master code not needed) but EC is connected to AP via i2c. BRANCH=none BUG=b:37584134 TEST=1. Compile rose board with CONFIG_I2C and CONFIG_CMD_HOSTCMD. Then make sure EC_CMD_GET_PROTOCOL_INFO works. 2. On Kevin and Elm, cherry-pick to firmware branch respectively, build and flash ec, i2c function works. Change-Id: I1f95ad277713c5e30913e0a010ca03dfd9ec248c Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/484999 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rose: stm32f4: fix DMA macro to get ISR bitsRong Chang2017-04-261-1/+1
| | | | | | | | | | | | | | | | Rose reads heatmap via halfduplex SPI sensors. This change fixed the macro to get correct DMA ISR register. BUG=chromium:688979 TEST=manually run spixfer in EC console and check return value BRANCH=none Change-Id: I303bdb483032c02d01fd322095f17dba37555447 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444631 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rose: add stm32f4 SPI master supportRong Chang2017-04-263-1/+43
| | | | | | | | | | | | | | | | This change adds stm32f4 stream DMA support and a config option to use first SPI port as master. BUG=chromium:688979 TEST=build and load on stm32f4 dev board BRANCH=none Change-Id: I2b504be70e0fbb17f16ce070119ae4715c88333a Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438911 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rose: remove dependency between stm32f4 I2C master and slave driversRong Chang2017-04-261-0/+2
| | | | | | | | | | | | | | | Frequency change hooks are needed in I2C master mode only. BUG=chromium:688979 TEST=remove CONFIG_I2C_MASTER and build rose target BRANCH=none Change-Id: I7244af73f97799d396d8680c8f131e8746a56e18 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438910 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* rose: enable stm32f4 EXTI IRQsRong Chang2017-04-261-0/+25
| | | | | | | | | | | | | | | This change copied gpio_init() from stm32f373 driver. BUG=chromium:688979 TEST=load on dev board and check button interrupt BRANCH=none Change-Id: I9dc12ffc02899211b6d07a640682899654c2bbed Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438909 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rwsig/update_fw: Prevent race in rollback protectionNicolas Boichat2017-04-263-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is a window where the rollback information in RW could potentially be updated during RW signature verification. We make sure this cannot happen by: - Preventing update over USB while RWSIG is running - When system is locked, only update rollback information if RW region is locked: this guarantees that RW cannot be modified from boot until RW is validated, and then until rollback information is updated. Also, remove rollback_lock() in rwsig_check_signature: rwsig_jump_now() protects all flash, which also protects rollback. This reduces the number of required reboots on rollback update. BRANCH=none BUG=b:35586219 BUG=b:35587171 TEST=Add long delay in rwsig_check_signature, make sure EC cannot be updated while verification is in progress. Change-Id: I7a51fad8a64b7e258b3a7e15d75b3dab64ce1c94 Reviewed-on: https://chromium-review.googlesource.com/479176 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rwsig: protect all flash before jumping to RWNicolas Boichat2017-04-261-2/+21
| | | | | | | | | | | | | | | | | | | | | On "normal" EC, we do protect RW as part of software sync, which would call flash_command_protect (which indirectly calls flash_protect_at_boot). Here, we don't want to (and can't) rely on the host to tell us to protect the RW, so we need to protect it ourselves before jumping to RW. This does feel a little redundant with rollback_lock though, since ALL will protect both RW and ROLLBACK: a later CL will fix that up. BRANCH=none BUG=b:35587171 TEST=flashwp true; reboot; RO protects all flash before booting to RW Change-Id: I820cabb01d1ca4aa47b81fc013a1670134a6be09 Reviewed-on: https://chromium-review.googlesource.com/476453 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/usb_update: add support for extra commandsNicolas Boichat2017-04-262-2/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for 4 extra commands that are required to update hammer: - UPDATE_EXTRA_CMD_IMMEDIATE_RESET - UPDATE_EXTRA_CMD_JUMP_TO_RW: Tells the RWSIG task to jump to RW as soon as possible (assuming the image verifies) - UPDATE_EXTRA_CMD_STAY_IN_RO: Tells the RWSIG task to not jump to RW, and stay in RO, to leave enough time for AP to update RW. - UPDATE_EXTRA_CMD_UNLOCK_RW: Tells EC to unlock the RW section so that it can be updated (on next reboot). BRANCH=none BUG=b:35587171 TEST=Test RO+RW update cd extra/usb_updater; make # Jump to RW sudo ./usb_updater2 -j sleep 0.5 # Update RO, then reboot sudo ./usb_updater2 ../../build/hammer/ec.bin sleep 0.5 # Update RW (first tell RO to not jump to RW) sudo ./usb_updater2 -s sudo ./usb_updater2 ../../build/hammer/ec.bin TEST=Test RW update only, with RO protected On EC console: flashwp true; reboot cd extra/usb_updater; make # Tell RW to unprotect RW and jump back to RO sudo ./usb_updater2 -w sudo ./usb_updater2 -r sleep 0.5 # Update RW, then reboot sudo ./usb_updater2 -s sudo ./usb_updater2 ../../build/hammer/ec.bin Change-Id: I5e8df7bdb4f06f2ac7b47de53dcde69c5002f578 Reviewed-on: https://chromium-review.googlesource.com/458470 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: peci: Fixed bug caused by wrong source clock of peci.Mulin Chao2017-04-261-2/+2
| | | | | | | | | | | | | | | | | | On npcx5, the peci speed should be 750K bps but we got 1.5M bps since selecting wrong source clock of peci. From the peci specification, the speed range is from 2K bps to 2M bps. That's why we still passed the peci test on npcx5's evb. This CL corrects the source clock of it from apb2 to fmclk and make sure the speed is 750K bps by the scope. BRANCH=none BUG=none TEST=Passed peci test on npcx5's evb and make sure the speed of peci is 750K bps. Change-Id: Ic5c55f7be9be195182e4c4f4ad64b7426afd42db Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/486680 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: clock: uart: Add support for npcx7 series ec.Mulin Chao2017-04-254-103/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In old clock driver, the relationships between each clock sources are ambiguous. For example, we treat OSC_CLK and FM_CLK as the same but sometimes they're not on npcx5. (Only one OSC_CLK definition cannot present the npcx ec's clock tree very well.) This CL added FM_CLK, CORE_CLK, and APBx_CLK definitions and used macro functions to confine the limitation of each clock sources in clock_chip.h to make it more clearly. We also modified the uart driver and fixed its source clock to 15MHz so far in this CL. Since npcx7 already supports uart wake-up mechanism, we removed the functions of switching pins from UART to GPIO by CHIP_FAMILY definitions for saving code space. It also includes: 1. Remove useless CHIP_VERSION definition. 2. Move frequency multiplier values M/N for OSC_CLK to clock_chip.h 3. Add clock_get_fm_freq() for the modules rely on it. Ex, peci. 4. Add clock turbo utilities for npcx7 series. 5. Support uart wake-up mechanism for npcx7 series. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. Passed clock turbo, sysjump and wake-up from UART signals stress tests on npcx796f evb. Change-Id: Id01a8a5d0263f0d2438e6346dfa33bcdef2be56e Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/486821 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Include stdint.h from ec_commands.h.Carl Hamilton2017-04-251-3/+5
| | | | | | | | | | | | | | | | | | | The ec_commands.h header uses types defined in stdint.h. To make the ec_commands.h header more portable, ensure that includes what it uses. Running "make -j buildall" worked for all boards except "gru" and "hammer", which were broken before this change. BRANCH=none BUG=none TEST=make -j buildall Change-Id: I1ffe41a69b7296736616b9250c45f2749a66f22c Reviewed-on: https://chromium-review.googlesource.com/483283 Commit-Ready: Carl Hamilton <carlh@chromium.org> Tested-by: Carl Hamilton <carlh@chromium.org> Reviewed-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Add #defines for UINT62_MAX and INT64_MAX.Jeff Andersen2017-04-251-0/+7
| | | | | | | | | | | | | | | | | Some files being included in firmware expect <stdint.h> to provide these definitions. BUG=none BRANCH=none TEST=make buildall Change-Id: I7313f05d9925a8fdfc4d1d0e8eea6ebcf999802e Reviewed-on: https://chromium-review.googlesource.com/484119 Commit-Ready: Jeff Andersen <jeffandersen@google.com> Tested-by: Carl Hamilton <carlh@chromium.org> Tested-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Carl Hamilton <carlh@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* hammer: Only define required options for RO and RWNicolas Boichat2017-04-254-14/+35
| | | | | | | | | | | | | | | | | | RO does not need touchpad/keyboard driver or I2C passthru, RW does not need RW verification, let's shrink both images by only including required config options. BRANCH=none BUG=b:35582031 TEST=Build and flash hammer: still functional. build/hammer/RO/ec.RO.flat shrank by 10144 bytes: (45868 to 35724) build/hammer/RW/ec.RW.flat shrank by 2764 bytes: (45332 to 42568) Change-Id: Iff0feb4e8446cc9f2e32103cd383fddae3234fec Reviewed-on: https://chromium-review.googlesource.com/479492 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Makefile: Allow different task list for RO and RWNicolas Boichat2017-04-254-41/+84
| | | | | | | | | | | | | | | | | | | | | | | This adds new macros for tasks (_RO and _RW), which allows to enable a task only for RO or RW section. We also create a new task_filter.h include file, that helps pre-filter those tasks, and can be used either from Makefile, or included from task_id.h. BRANCH=none BUG=b:35582031 TEST=make buildall -j; make savesizes Apply this CL make buildall -j; make newsizes => No size change Change-Id: I472bc6d4ab250a0a0e1fa6aeb4b748ba6968bedf Reviewed-on: https://chromium-review.googlesource.com/479491 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Nick Sanders <nsanders@google.com>
* npcx: i2c: Fix i2c freq setting when APB clock is 15 MHzCHLin2017-04-251-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | To configure 1 MHz speed when the APB clock is 15 MHz, the firmware currently sets the SCLHT register to 4. However, we found out that writing 4 to this register (and to SCLLT register) is illegal and results in unexpected results. So there is a need to write 5 in that case. However, this means that the actual i2c frequency will be 750 KHz. To get a higher i2c clock frequency, there is a need to run with a higher APB clock (and a higher core clock). For example, with APB set to 20 MHz, the i2c clock frequency is 833 KHz. In this CL, the i2c freq setting for APB clock=20 MHz is also added which may be used for NPCX7 in the future. BRANCH=none BUG=chromium:714314 TEST=No build error for make buildall(except gru). Use scope to capture SCL signal on npcx5 EVB and make sure its freqency is about 750 KHz. Change-Id: I9025344e6df4b584b203c8c59bb9875250d9fe4f Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/484202 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* tcpm: it83xx: fill out structure membersDino Li2017-04-251-0/+7
| | | | | | | | | | | | | These are options for features can be implemented if they are required. BRANCH=none BUG=none TEST=build 'it83xx_evb' board with pd modules. Change-Id: I1afb7d9c2d764728a375563a6739544032394c54 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/483319 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: i2c: increase clock low timeout to maximumDino Li2017-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | This timeout is described in SMBus specification (25ms). Some I2C devices may required longer clock stretch (The I2C specification does not specify any timeout conditions for clock stretching). So we increase this timeout to maximum. NOTE: Because this codebase already handle timeout of an I2C transfer, so maybe we can disable this mechanism. But we don't have any register to execute this, so we maximize the timeout. BRANCH=none BUG=none TEST=console commands: i2cscan, battery, charger, and accelinfo. Change-Id: I5025f640c027105152247212fc688388f645c5ba Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/485203 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: Added CONFIG_SWITCH support.Dino Li2017-04-251-0/+1
| | | | | | | | | | | | | This change updates switch status to EC MEMMAP. BRANCH=none BUG=none TEST=Use 'mmapinfo' console command to verify lid status. Change-Id: I80b9e407a8793f2de84011473cd51c5453d77859 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/483259 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Add support for npcx7 series ec.Mulin Chao2017-04-257-300/+1021
| | | | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add gpio_chip-npcx5/7.h files and move all macro functions related to chip family to them. (Move wui macro func from gpio_wui.h to them.) 2. Replace alternative and low-voltage mapping table with macro function NPCX_ALT_TABLE and NPCX_LVOL_TABLE. 3. Add UART wakeup mechanism in __gpio_wk1h_interrupt() ISR. 4. Add gpio register definitions of npcx7 family in registers.h. 5. Add GPIO_LOCKED flag for lock functionality. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Passed validation for all GPIO functionalities on npcx5m6g and npcx796f evb. Change-Id: I60c30ce223629a0d8cb767a54a0a9b02a69de9c5 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481561 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Introduce npcx7 series ec chip definitions and configurations.Mulin Chao2017-04-255-36/+154
| | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish which npcx's ec is used on the board. 2. Add config_chip-npcx5/7.h files and move features depend on chip family into them. 3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on npcx7 ec. We'll use them later in gpio/system/flash drivers. 4. Add ram size checking for all npcx ec series. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481560 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tigertail: fix USB timingNick Sanders2017-04-241-1/+7
| | | | | | | | | | | | | | | | Add some disconnect time between mux selections. This ensures that USB VBUS will fall and a USB disconenct will happen. BRANCH=None BUG=b:35849284 TEST=ran on tigertail Change-Id: I6cdbf8ce908f20213c7f8d1f4437ffe2b624be02 Reviewed-on: https://chromium-review.googlesource.com/459219 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* rowan: enable Lid Accel but not Gyro readings in S0Daniel Kurtz2017-04-211-6/+6
| | | | | | | | | | | | | | | | | | | Allow EC to take Lid Accelerometer readings in S0 to support rotation, but disable taking Gyro readings unless requested by AP. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BRANCH=none BUG=b:36668539 TEST=in ec console: accelinfo on => confirm Lid Accel values are non-zero => confirm Gyro values are zero Change-Id: Ie0bf466a5877cf8d20fb3d5cd223696fbdc9c271 Reviewed-on: https://chromium-review.googlesource.com/484140 Commit-Ready: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* rowan: update rotation matrixMilton Chiang2017-04-211-2/+2
| | | | | | | | | | | | | | | | BRANCH=none BUG=b:35647688 TEST=test on rowan proto and make sure the display can rotate correctly according to the orientation. Change-Id: I8066227dd2a0628c899ea93680d0f9764b013ddf Signed-off-by: Milton Chiang <milton.chiang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/461057 Commit-Ready: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Yidi Lin <yidi.lin@mediatek.com> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Patrick Berny <pberny@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
* common/update_fw: Board/chip-specific first_response_pduNicolas Boichat2017-04-212-34/+85
| | | | | | | | | | | | | | | | | | | | | | | | | cr50 and hammer/common code are such different chips that reusing the same first_response_pdu does not make much sense. Instead, we can use 2 different headers, the updater knows which response to expect based on USB product ID. In the common code answer, we can reply with the EC version string, as well as rollback information and key version ID, which will be required for reliable updating. BRANCH=none BUG=b:35587171 BUG=b:36375666 TEST=usb_updater2 can update hammer, and read its version, rollback version and key version. Change-Id: I20b04070606767c71df3e6286d53e238e13375c0 Reviewed-on: https://chromium-review.googlesource.com/476452 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "system: Shutdown AP before entering hibernate mode"Duncan Laurie2017-04-2110-32/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 20c439be209a9cc0bb949ad21f289c453126395f. Reason for revert: This breaks hibernate on skylake boards and needs to be tested on more than just kevin before submitting. BUG=chromium:702451 BRANCH=none TEST=power down and successfully hibernate on Eve Original change's description: > system: Shutdown AP before entering hibernate mode > > BUG=chromium:702451 > BRANCH=none > TEST=manually test on gru: confirm > 'Alt+VolUp+h' puts gru in hibernate mode and > AC plug-in wakes it up. > > Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 > Reviewed-on: https://chromium-review.googlesource.com/470787 > Commit-Ready: Philip Chen <philipchen@chromium.org> > Tested-by: Philip Chen <philipchen@chromium.org> > Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> > TBR=rspangler@chromium.org,aaboagye@chromium.org,philipchen@chromium.org # Not skipping CQ checks because original CL landed > 1 day ago. BUG=chromium:702451 Change-Id: Ie847a5e3efb28256b00ddc6534d8ae6bbbba7121 Reviewed-on: https://chromium-review.googlesource.com/482989 Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* USB: Remove usb_charge_ports_enabledDaisuke Nojiri2017-04-202-27/+0
| | | | | | | | | | | | | usb_charge_ports_enabled is not used. BUG=none BRANCH=none TEST=make buildall Change-Id: I9465b65e9fab2603a4258adc4ae5f16d6bfc93c4 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/481076 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Change second tachometer source from TB2 to TA2.Mulin Chao2017-04-1812-22/+57
| | | | | | | | | | | | | | | | | | | | | | | | In npcx's fan driver, ec selected mode 5 and capturer A as tachometer's input. Choosing TB2 as the second tachometer source is not correct since we didn't initialize the registers for TB2. This patch modified the second tachometer's input from TB2 to TA2 and passed the verification by following changes. 1. Add the second fan settings in pwm_channels, fans, and mft_channels arraies. 2. Modified ALTERNATE marco for pwm-type fans. 3. Set CONFIG_FAN from 1 to 2. 4. Set NPCX_TACH_SEL2 to 1 to test tachometer input 2. (ie.GPIO73/A6) BRANCH=none BUG=none TEST=test dual fans with fanset command on npcx_evb and use faninfo for verifying. Measure the actual rpm by scope. Change-Id: Ia1af2732d9a64e24285d12371223eb0e77e53357 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/472310 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: remove console command "rwreg"Dino Li2017-04-181-86/+0
| | | | | | | | | | | | | We don't use this command so remove it to save flash space. BUG=none BRANCH=none TEST=build all. Change-Id: I7279c56add6ad2b07f0a9b3cdc0ed849f8176e61 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/479976 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: fan: Simplified TACH_TO_RPM formula and fixed bugs.Mulin Chao2017-04-181-48/+92
| | | | | | | | | | | | | | | | | | | | | | This CL simplified TACH_TO_RPM formula and abstracted two definitions (PULSES_ROUND and RPM_DEVIATION) for the pwm-type fan used on boards. The developers can modify them in board-level driver if fan doesn't meet the default spec. In this CL, it also fixed: 1. Declare rpm_pre as array if FAN_CH_COUNT > 1. 2. Add checking for the value of next duty of pwm. 3. Use TAPND pending bit to make sure TCRA is valid. BRANCH=none BUG=none TEST=test fan used in kahlee and Sunon fan with fanset command on npcx_evb and use faninfo for verifying. Measure the actual rpm by scope. Change-Id: Ieb07482eb359912286414ccb9738341d98ea99e4 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/472289 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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