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* reef_it8320: initial reef_it8320 boardDino Li2017-05-1811-906/+367
| | | | | | | | | | | | | | This change is based on reef's board code and modified for it8320. BUG=none BRANCH=none TEST=Run the entire faft_ec suite and passed. Change-Id: I8977d7431eb0a97ceb4ee1dfd11a2c4433687db0 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/487792 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* poppy: ACCELGYRO3_INT_L is always on gpio 36Nicolas Boichat2017-05-181-5/+0
| | | | | | | | | | | | | | | | dabc580d7e42 "poppy: Add ARC++ sensor support." accidentally moved pin from gpio 36 to 30. When updating gpio.inc for rev1, I accidentally thought the pinout had been changed. Let's fix this. BRANCH=none BUG=none TEST=Boot on poppy and soraka Change-Id: I6f44acdcfa7bc8f21144b26887eda503a350a6b0 Reviewed-on: https://chromium-review.googlesource.com/497232 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* host_command: Throttle printing of "+" for repeated commandsNicolas Boichat2017-05-181-1/+10
| | | | | | | | | | | | | | | | | | | | When AP boots and FW screen is shown (e.g. in developer mode), AP FW is querying MKBP status in a loop, leading to a lot of "+" being printed in the EC console. To avoid this issue, let's print "(++)" after a command is received 5 times in a row. BRANCH=none BUG=b:37925684 TEST=Set GBB flags to 0x4a38, reasonable number of "+" is printed on EC console on boot, which firmware screen is being shown. Change-Id: I8368c558b97e7a2513b979322bd4bba442626b27 Reviewed-on: https://chromium-review.googlesource.com/505948 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* touchpad_elan: Read resolution and validate against build-time valuesNicolas Boichat2017-05-181-2/+27
| | | | | | | | | | | | | | | | | At init time, read resolution/dpi from trackpad, and check that logical/physical dimensions match the expected values, provided at build-time. BRANCH=none BUG=b:38277869 TEST=Flash staff, no error message at boot time. Flash hammer image onto staff, a warning is shown at boot time. Change-Id: I5ef7d25b6e6525c2bd6fc023f58f3a242134d962 Reviewed-on: https://chromium-review.googlesource.com/505857 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_touchpad: Add config options to set dimensionsNicolas Boichat2017-05-183-73/+52
| | | | | | | | | | | | | | | | | | | | | | In principle, trackpad dimensions (logical and physical), can be probed from the trackpad at runtime, but this would slow down setup time, as we need to wait for the trackpad to be initialized to read those. Also, we do not have a framework to generate HID report at runtime, and a new base with new trackpad would probably require a new overlay anyway. Also, set appropriate (temporary) values for both hammer and staff. BRANCH=none BUG=b:38277869 TEST=Connect hammer/staff to host, correct logical dimensions are shown in evtest, and resolution is always 32. Change-Id: I39b84274d71ca2f4e285f3324c0841331aae9bc1 Reviewed-on: https://chromium-review.googlesource.com/505856 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fizz: Set up charge suppliers at bootDaisuke Nojiri2017-05-178-199/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | Fizz has two power sources: barrel jack and type-c port. It selects a power source at boot and does not dynamicall switch to the other ports after that. Fizz initializes all power suppliers of all ports to zero then initialize the source supplier (barrel jack or type-c port). When both sources are provided, it prefers a barrel jack. This detection is done by reading the voltage on PPVAR_PWR_IN. If barrel jack is detected as a sink, type-c port works as a source only. If type-c port is detected as a sink, type-c port works as a sink only. Fizz does not have a battery. So, battery module is removed. BUG=b:37573548,b:37316498 BRANCH=none TEST=Boot on both type-c & barrel jack. Change-Id: If4f5ff0c6019d06ac9dacb5dd365f5aa96bffef3 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/499547
* board: reef_it8320: copy board/reefDino Li2017-05-178-0/+2997
| | | | | | | | | | | | | copy board/reef and modified for 'pre-upload.py'. BRANCH=none BUG=none TEST=build all. Change-Id: I76618610f443c7d4bb1b7b507c71f3d74d639667 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/501607 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* keyboard_8042: Add scancode entries for new matrixDuncan Laurie2017-05-171-4/+4
| | | | | | | | | | | | | | | | | | Add the new scan codes for the updated keyboard matrix: R0,C3 = Search (in addition to existing location at R1,C0) R0,C5 = New key using code 0[e0 58] and 1[e0 07] There are no changes to existing scan codes. BUG=b:36735408 BRANCH=none TEST=make -j buildall Change-Id: Ieba22eacd21a5c2dde3c7c43eb62b767fc0db42e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/506716 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* charge_state_v2: Remove assert for no AC and no batteryDuncan Laurie2017-05-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The assert in the charge state machine when there is no battery and no AC is causing a lot of headaches during development, and I don't believe it adds any value to panic the EC like this as it prevents the system from coming up and any debug from happening. This is especially bad with H1 locking out any useful debug by preventing flashing the EC. On Eve EVT we have some 'bad' batteries that are not correctly asserting presence pin, and when powering with adapter this this check happens before AC_PRESENT asserts because the USB PD negotiation is still happening so the EC gets stuck in a reboot loop. Similarly we had issues with the Krill board in the Whale BFT station that was triggering the same assert. In both cases there is an underlying hardware issue which is being investigated separately, but it is impossible to debug these systems because the EC will not come up. With this assert removed the EC and AP can boot and the LED blinks red to indicate there is battery a problem and the OS also reports a problem that the battery cannot be found, and we are able to do further debug without having to open the case. Additionally the error message is printed every ~second and it is very obvious from the EC console that there is a problem. Similar issues were reported at various points on Glados, Chell, Kevin, Elm, and Reef. BUG=b:35563537 BRANCH=none TEST=successfully boot and debug a failing Eve system Change-Id: I002b26d54428d29192a7097f1aae18f3223c5707 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/477733 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: remove code that was used to work around sys_rst issuesMary Ruthven2017-05-162-41/+1
| | | | | | | | | | | | | | | | | | | | | | | Cr50 holds the EC in reset when it wants to flash the EC or AP. This will trigger a pulse on the tpm reset signal. In early Cr50 versions when the tpm was reset we would reboot cr50, so we added some code to prevent cr50 from resetting itself when the update was going on. sys_rst_asserted would check if there was an update going on and ignore the signal if update in progress was true. At the end of the update the deferred function was used to reset Cr50 after the update was complete. None of this is needed anymore. We can just release the EC from reset at the end of the update. This change removes usb_spi_update_in_progress and the deferred update_finished. BUG=b:35571516 BRANCH=none TEST=flash the bob ec and ap using ccd. Change-Id: I79416dba178c06bbc7289ad96968ee4e61947c4c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/506571 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ec: add initial coral related filesYH Lin2017-05-169-0/+2992
| | | | | | | | | | | | | | For now use the files from reef. To be changed later on. BRANCH=none BUG=b:38271615 TEST=emerge-coral chromeos-ec Change-Id: Iff0a7b21b575d6394c27ff9959010496801fd056 Reviewed-on: https://chromium-review.googlesource.com/506117 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: drop obsolete/addressed TODOsVadim Bendebury2017-05-167-33/+0
| | | | | | | | | | | | | | There many TODOs sprinkled in the code, some of them have been addressed or do not apply any mode. This patch removes them. BRANCH=cr50 BUG=none TEST=built and ran cr50 on reef Change-Id: Ica6edb204e5cc0cc9dc7f0d43fd39e7ddaf56809 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/506496 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hammer: Add staff boardNicolas Boichat2017-05-164-1/+15
| | | | | | | | | | | | | | | | | | | | | | hammer corresponds to poppy, and staff corresponds to soraka. Current differences (hammer/staff): - USB id (5022/502b) - PWM frequency (10kHz/100Hz): - On staff, driving PWM at 10kHz leads to an actual duty cycle around 30-40%, with a PWM output at 1% (long rise/fall time). 100Hz looks better, we get ~1.45% duty with 1% PWM output. BRANCH=none BUG=b:38277869 TEST=Flash staff, boots fine. TEST=pwm 0 1 shows quite dim backlight on staff. Change-Id: I66ba2adf89fbee8578ee473afb28e3e242b4d111 Reviewed-on: https://chromium-review.googlesource.com/505855 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* CR50: remove duplicate SHA #definesnagendra modadugu2017-05-161-6/+2
| | | | | | | | | | | | | | | | Include the appropriate SHA header files and remove duplicate #defines. BRANCH=none BUG=none TEST=compilation succeeds Change-Id: I15b77c3f40a07af8ea397f41d671386f303287eb Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/505200 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* tigertail: tigertool command line apiNick Sanders2017-05-169-0/+1020
| | | | | | | | | | | | | | | This tool allows an easy commandline interface to set the USB-C mux position, as well as init and reboot. BRANCH=None BUG=b:35849284 TEST=flash, control tigertail successfully Change-Id: I8d60c215fee04de158c22edca5377c3c6cd48cf0 Reviewed-on: https://chromium-review.googlesource.com/493617 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* flash_ec: Respect the raiden flag if no board givenWai-Hong Tam2017-05-161-1/+1
| | | | | | | | | | | | | | | | In a lab servo, flash_ec is executed without the board flag. In this case, don't check the board flag for raiden and simply respect the raiden flag. BRANCH=none BUG=b:38319398 TEST=Ran the flash_ec script in a lab servo. Change-Id: Ib3757a4b7b550fd77facffdf2009cc3317591888 Reviewed-on: https://chromium-review.googlesource.com/506461 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* CR50: configure AES rand stallsnagendra modadugu2017-05-152-0/+13
| | | | | | | | | | | | | | | | | | | | | | This change configures the AES engine to a) enable rand stalls at 25% during regular operation through AES API's, and b) disable rand stalls when doing fixed-key bulk-encryption (e.g. NVRAM ciphering). TCG tests continue to complete in ~20 minutes (i.e. no noticable slowdown). BRANCH=none BUG=b:38315169 TEST=TCG tests pass Change-Id: I2d26d232491a27bffbbe0b5aedfebaf04e0ad509 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/502717 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: replace dcrypto_memset with always_memsetnagendra modadugu2017-05-159-39/+46
| | | | | | | | | | | | | | | | | | | | | | | always_memset() implements a version of memset that survives compiler optimization. This change replaces instances of the (placeholder) call dcrypto_memset() with always_memset(). Also add a couple of missing memsets and fix related TODOs by replacing memset() with always_memset(). BRANCH=none BUG=none TEST=TCG tests pass Change-Id: I742393852ed5be9f74048eea7244af7be027dd0e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/501368 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* hammer: Add pull-up on write protect pinNicolas Boichat2017-05-151-1/+1
| | | | | | | | | | | | | | | | | We don't have an external pull-up on WP_L, so let's use an internal one instead. BRANCH=none BUG=b:35582031 TEST=gpioget WP_L shows 1 as default value, servo can control value, and when servo is not driving the pin, value goes back to 1. Change-Id: I75148cde9ab89c1dfb05f3182608894a3e1390fa Reviewed-on: https://chromium-review.googlesource.com/502849 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: flash: Add write-protect support for internal flash of npcx7 ecstabilize-9554.BMulin Chao2017-05-123-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | In order to support write-protect mechanism for the internal flash of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by controlling the WP_L pin of internal flash. During ec initialization or any utilities related to access status registers, we'll protect them if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we only can unlock write protection of internal flash by rebooting ec. This CL also includes: 1. Add protect_range array of npcx7's internal flash (W25Q80) for write-protect mechanism. 2. Add bypass of bit 7 of DEVCNT. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. (Besides gru) Build poppy board and upload FW to platform. No issues found. Passed flash write-protect checking on npcx796f evb. Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/501727 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: add LONG_LIFE bit to suppress RO uart.Marius Schilder2017-05-121-0/+6
| | | | | | | | | | | BRANCH=None BUG=None Change-Id: Icfb20bff28a593c9058d67ad09f188c567b7401c Reviewed-on: https://chromium-review.googlesource.com/454240 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* button: Recovery on power-on resetDaisuke Nojiri2017-05-121-4/+14
| | | | | | | | | | | | | | | | | | When cr50 detects recovery button (not keyboard) combo: recovery+power, volume-up+down+power, etc., it should (ideally) hard-reset the EC. This patch allows power-on reset in addition to reset-pin reset to enter recovery mode when recovery button combo is pressed. BUG=b:35585326 BRANCH=none TEST=make buildall. Tested on Poppy. Change-Id: I15aeef99d21ddc774441ead56fba56d459595cc9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/503573 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fizz: Add LED controlDaisuke Nojiri2017-05-122-0/+112
| | | | | | | | | | | | | This patch adds code to control the power LED. BUG=b:37646390 BRANCH=none TEST=Verify LED turns green, red, amber, off. Verify LED turns green or off when chipset is on or off, respectively. Change-Id: I1d7940d9bb4414d97c541ead802efeb8f279533e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/486947
* Fizz: Add recovery buttonDaisuke Nojiri2017-05-124-1/+24
| | | | | | | | | | | | | | | Cr50 masks the recovery button signal on a proto board when the power button is being pressed (b:37682117). This bug has to be fixed for the recovery button to work. BUG=b:37274183 BRANCH=none TEST=make buildall Change-Id: Ia413ffce84d67b6f24f983ccce8ae8277452ac2c Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/494069 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* CR50: enable dcrypto random stallsnagendra modadugu2017-05-121-3/+6
| | | | | | | | | | | | | | | | | | Clean up a lingering TODO; enable random stalls (NOPs) at ~6% for crypto operations. BRANCH=none BUG=none TEST=TCG tests pass Change-Id: I46b2755d9f501eb4ec98c3184d1e14fbf118c718 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/501349 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Paul Scheidt <pscheidt@google.com>
* g: allow to select the default USB PHY at startup.Vincent Palatin2017-05-122-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | When (USB-)resuming from deep-sleep, ensure that we avoid switching back and forth the selected USB PHY at boot, in order to avoid having a short disconnection at resume. To achieve this, allow the board configuration to select the PHY it is really using with the CONFIG_USB_SELECT_PHY_DEFAULT configuration variable, still keep the default USB_SEL_PHY1 as before. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:38160821 TEST=manual: build 'proto2' firmware with CONFIG_LOW_POWER_IDLE defined, with the chip connected to the host on PHY A, make the host issue a USB Suspend then resume and see no disconnection. Change-Id: I7abd5e338e5c688c2dd486293f520049cdfd273b Reviewed-on: https://chromium-review.googlesource.com/501947 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* uart: fix compile warning when !defined CONFIG_CONSOLE_ENABLE_READ_V1Wei-Ning Huang2017-05-121-2/+2
| | | | | | | | | | | | | | | Fix compile warning when CONFIG_CONSOLE_ENABLE_READ_V1 is undefined. BRANCH=none BUG=b:37584134 TEST=with CONFIG_CONSOLE_ENABLE_READ_V1 undefined, `make BOARD=rose -j` Change-Id: I86f57e6fe92032ad688e861688f99b3f430404f4 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/504687 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* stm32: add clock configuration for stm32f412 to run at 96 MHzWei-Ning Huang2017-05-122-5/+23
| | | | | | | | | | | | | | Add clock definition for stmf412. New stm32f4 chip variant will have to define their own clock definitions. BUG=b:37187312 TEST=`make BOARD=rose- j` Change-Id: Ie053298d2f1255d7bc152f6018a674281bda7004 Reviewed-on: https://chromium-review.googlesource.com/487848 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* mn50: initial checkinNick Sanders2017-05-1213-35/+832
| | | | | | | | | | | | | | | | This firmware supports a board used to initialize firmware on new cr50 parts. BUG=b:36910757 BRANCH=None TEST=boots on scribe board, spi/usb/uart/i2c functionality works. TEST=cr50 boots on reef, CCD EC+AP SPI/UARTS work Change-Id: I48818225393a6fc0db0c30bc79ad9787de608361 Reviewed-on: https://chromium-review.googlesource.com/437627 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Fizz: Enable/disable USB Type-A portsDaisuke Nojiri2017-05-113-0/+18
| | | | | | | | | | | | | This change makes Fizz enable USB type-A ports on resume and disable them on shutdown. BUG=b:38226666 BRANCH=none TEST=Boot Fizz off of USB flash drive on a USB-A port. Change-Id: I7f22438271ffc080e950f5f300937d89706e08a4 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/481078
* charger: Add dedicated (non-type-c) chargerDaisuke Nojiri2017-05-114-31/+57
| | | | | | | | | | | | | | | | This patch adds a dedicated charge port. The number of such ports is specified by CONFIG_DEDICATED_CHARGE_PORT_COUNT. It works as a sink only. The total number of charge ports is represented by CHARGE_PORT_COUNT. BUG=chromium:721383 BRANCH=none TEST=make buildall. Boot Fizz off of barrel jack. Change-Id: Ibbb11f3e1c66e35b5abe190e49161eeaa2009994 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/501468 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy: source 3A on one portNicolas Boichat2017-05-111-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Add a new source policy to provide 3A if there is only one port used as a source. Also ensure that the load switch on VBUS when sourcing power is properly configured to limit the current to 1.5A or 3.0A depending on the case. BRANCH=none BUG=b:35585396 BUG=b:35577509 TEST=On soraka (rev1), connect any USB device on port 0. On port 1 attach C-C cable to MacBook Pro. MacBook Pro charges at ~1.5A. Disconnect USB device on port 0, MacBook Pro charges at 3A. TEST=On soraka (rev1), connect USB key on port 0, see it enumerating, plug another USB key on port 1, it enumerates too, and the device on port 0 does NOT disconnect/re-enumerate. TEST=Repeat 2 tests above, but starting with port 1. Change-Id: I48e744c8edec89bc0a53b54c47f666ad53e47551 Reviewed-on: https://chromium-review.googlesource.com/481563 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rwsig: expose a new feature bit when RWSIG task is enabledWei-Ning Huang2017-05-113-0/+6
| | | | | | | | | | | | | | | | | | Expose EC_FEATURE_RWSIG if RWSIG task is enabled. This allows flashrom to run EC_CMD_RWSIG_ACTION and abort RWSIG jump, then perform regular firmware update flow. BRANCH=none BUG=b:37584134 TEST=on eve, `ectool --name=cros_tp inventory` should show 'RWSIG task'. Change-Id: Iea14f4f01fab201767dccd07d711ae9e1b638f6a Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/497788 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* CR50: constant time padding check routinesnagendra modadugu2017-05-101-23/+53
| | | | | | | | | | | | | | | | | Rewrite RSA padding-check routines to complete critical section in constant time. BRANCH=none BUG=b:35587381 TEST=TCG tests pass Change-Id: I8815f5fcabad1d966e6e17027bde836b53c5f6be Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/498856 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Fizz: Initialize board directoryDaisuke Nojiri2017-05-105-659/+224
| | | | | | | | | | | | | | | | | | | | | Noteworthy changes: * Remove motion sensors * Remove MKBP keyboard * Temp sensor (TMP432) * Remove BC1.2 * One TCPC port (PS8751) * Remove lid switch * Remove backlight * Switch PMIC to TPS650830 BUG=b:37271713 BRANCH=none TEST=Boot Fizz off of barrel jack. Change-Id: Id3b1ab1d10ad52786d75dc04bc3115c80ea31ee4 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/459114 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* g: fix build without CONFIG_RESTRICTED_CONSOLE_COMMANDSVincent Palatin2017-05-101-0/+5
| | | | | | | | | | | | | | | | | | console_is_restricted() function exists only if CONFIG_RESTRICTED_CONSOLE_COMMANDS is defined, and a stub if it doesn't. so we can use CONFIG_LOW_POWER_IDLE without the former. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:38160821 TEST=manual: build 'proto2' board with CONFIG_LOW_POWER_IDLE defined. Change-Id: I0c7fd201a1f07371aee2420eafd96ac62a5ae4ca Reviewed-on: https://chromium-review.googlesource.com/500148 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* poppy: Update detection values for rev1Nicolas Boichat2017-05-101-9/+2
| | | | | | | | | | | | | | | | | rev1 uses 604K pull-up on lid, 30.1K pull-down, 1% tolerance, so we can just reuse rev0 detection interval. We can consider narrowing the interval as rev1 should have tighter tolerance. BRANCH=none BUG=b:35582031 TEST=make BOARD=poppy; make BOARD=soraka TEST=Soraka (rev1): Base is detected. Change-Id: I7c3950a0b4c0bd0e1140e4a51447a3483cccc603 Reviewed-on: https://chromium-review.googlesource.com/500014 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* soraka: Add battery informationNicolas Boichat2017-05-101-0/+19
| | | | | | | | | | | | BRANCH=none BUG=b:35585396 TEST=soraka EC boots and charges battery Change-Id: I06e0ce7cb143ee039fecada0b4e15a64bcf5968b Reviewed-on: https://chromium-review.googlesource.com/497530 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* rwsig: protect flash with EC_FLASH_PROTECT_ALL_NOW whenever possibleWei-Ning Huang2017-05-101-13/+20
| | | | | | | | | | | | | | | | | | | Use EC_FLASH_PROTECT_ALL_NOW to protect all flash before jump if posisble. If EC_FLASH_PROTECT_ALL_NOW does not work, try EC_FLASH_PROTECT_ALL_AT_BOOT next. BUG=b:37584134 TEST=on rose: 1) `flashwp enable` 2) `reboot` 3) `flashinfo` flags contains 'all_now' Change-Id: I2773410e97fae082fc6c20d47bdae3d991c57063 Reviewed-on: https://chromium-review.googlesource.com/497155 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: system: Add support for npcx7 series ecMulin Chao2017-05-099-255/+542
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL implements two methods for hibernating on npcx7 ec. One is using PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The other is turning off the power of all ram blocks except the last code ram block. In order to make sure hibernate utilities are located in the last code ram block and work properly, we introduce a new section called 'after_init' in ec.lds.S. We also moved the hibernate utilities, workarounds for sysjump and so on which are related to chip family into system-npcx5/7.c. It should be easier to maintain. It also includes: 1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for hibernating. 2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of wake-up inputs during hibernating. 3. Add DEVICE_ID for npcx796f. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. Make sure AC_PRESENT and POWER_BUTTON_L can wake up system from hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is enabled or not on npcx796f evb. Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/493006 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* bd9995x: BD9995X_PMON_IOUT_ADC_READ_COUNT is a power of twoDino Li2017-05-091-1/+1
| | | | | | | | | | | | | | | | With the change, compiler won't use 64-bit division for bd9995x_psys_charger_adc() function. BRANCH=none BUG=none TEST=To replace "reg" variable and checking the return value if it is expected for both "bd9995x_psys_charger_adc()" and "bd9995x_amon_bmon_chg_adc()" functions. Change-Id: Ifc461e5a54ce583ff59281ad13421c640ec9e21e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/485083 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* button: Allow board to define recovery buttonsDaisuke Nojiri2017-05-096-6/+37
| | | | | | | | | | | | | | This patch declares recovery_buttons array, where each board lists recovery buttons. Pressing those while the board reboots makes the system enter recovery mode. BUG=none BRANCH=none TEST=buildall Change-Id: I1f204156efbd6d2a507d67ba90f75ce857b03559 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/486944
* Allow lid-less configurationDaisuke Nojiri2017-05-099-4/+42
| | | | | | | | | | | | | | | | | | | power_button_x86.c and switch.c assume there is a lid switch. This patch separate them so that a board with power button but with no lid can be configured properly. This patch also moves backlight control to the board directory so that only the boards with a backlight turn it on/off when power state changes. BUG=none BRANCH=none TEST=boot fizz. make buildall. Change-Id: If4070cdc4b1221fae68b35ec3497335d81f192fd Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/489602 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Eve,Gru,Poppy,Reef: forbid DR_SWAP in RO firmware.Vincent Palatin2017-05-095-13/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when we jump from RO to RW, we forget our USB PD state. To recover from this, we send a SOFT_RESET (resetting the counters...), then either the USB PD partner is happy about it and we can continue, or it will issue a HARD_RESET to recover from our mismatched vision of the current connection (e.g wrong role) resulting in a reset of VBUS. The following use-case is still problematic: if the system is not write-protected (ie it does USB PD negotiation in RO EC) and we have no battery (or fully drained-one) as buffer, when we are connected to a PD power supply, if it issues the HARD_RESET mentioned above, we are going to brown-out. It's happening with power-supplies supporting DR_SWAP, the RO EC will negotiate a power-contract (as a sink), then try to reverse data role (from UFP to DFP) to identify the power-supply. We end-up being Sink/DFP, then when we sysjump to RW, we reset roles and send the SOFT_RESET as Sink/DFP, the power-supply identifies the incorrect data role and issues the HARD_RESET browning us out. As a workaround, now we never ask for the DR_SWAP in RO firmware and stays Sink/UFP. This is not affecting regular write-protected machines (which are not doing USB PD in RO EC). For developers, we are no longer doing the DR_SWAP in RO mode, this is mostly innocuous for a regular power-supply, but this would break the docking use-case. Normally, we will do it as soon as we have jumped to RW, so the dock should still work unless the developer is using the machine with RO EC (eg EC development with soft-sync disabled). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=reef BUG=b:35648282 TEST=Boot Snappy without battery. Verify RO image doesn't swap data roles and soft reset issued by RW image as SNK/UFP is accepted by the HP adapter. Change-Id: Id184f0d24a006cd46212d04ceae02f640f5bda65 Reviewed-on: https://chromium-review.googlesource.com/461142 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Sam Hurst <shurst@google.com>
* kahlee: fix emerge errorYH Lin2017-05-091-0/+1
| | | | | | | | | | | | | | | Add the missing line which causes emerge ec to fail. BRANCH=None BUG=None TEST=emerge-kahlee chromeos-ec Change-Id: Icc8dce65f7628ba7f69d9165b6956b6db9b3e1d3 Reviewed-on: https://chromium-review.googlesource.com/500015 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Deepak Sharma <deepak.sharma@amd.com> Reviewed-by: YH Lin <yueherngl@chromium.org>
* pd: Make build of VIF utility less verboseSam Hurst2017-05-092-2/+3
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make -j buildall Change-Id: I37be7abde31d20e0f4227db97e6751c2998f418b Reviewed-on: https://chromium-review.googlesource.com/499871 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* virtual_battery: prevent access out of bounds of memoryphilipchen2017-05-091-2/+11
| | | | | | | | | | | | | | | | | | | BUG=chromium:717737 BRANCH=none TEST=manually run 'power_supply_info' a few times and see consistent battery parameters TEST=access cached smart battery registers from the host command and see it returns 0 for out of bounds of memory Change-Id: I87cf2900ff93a952dc88cd9c3da82321533e4eb5 Reviewed-on: https://chromium-review.googlesource.com/495628 Reviewed-by: Douglas Anderson <dianders@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> (cherry picked from commit 96514bb2d21dbe8b4cc6177db9e916384649e28f) Reviewed-on: https://chromium-review.googlesource.com/499607 Commit-Ready: Philip Chen <philipchen@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* hammer: Disable boot keys and runtime keysNicolas Boichat2017-05-081-1/+3
| | | | | | | | | | | | | | | | Those keys aren't very useful on hammer. BRANCH=none BUG=b:37422577 TEST=Flash hammer TEST=make newsizes shows 280 bytes size decrease on hammer/RW. Change-Id: I859c999ce796af53b9290cc5215f9b28a815b638 Reviewed-on: https://chromium-review.googlesource.com/495969 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* keyboard_scan: Add option to not handle boot key combinationsNicolas Boichat2017-05-083-1/+15
| | | | | | | | | | | | | | | | | | On some boards, the boot key combinations do not make a lot of sense, so we can just not process them and save a little bit of code space. BRANCH=none BUG=b:37422577 TEST=Flash hammer TEST=make newsizes shows we save 156 bytes in hammer RW. Change-Id: Ic96d7ed1dbee10f44f8b08568ab70b2f20961842 Reviewed-on: https://chromium-review.googlesource.com/495968 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* keyboard_scan: Add option to not handle special key combinationsNicolas Boichat2017-05-082-0/+10
| | | | | | | | | | | | | | | | | On some boards, the special alt-volup-r/h combinations do not make a lot of sense, so we can just not process them and save a little bit of code space. BRANCH=none BUG=b:37422577 TEST=Flash hammer, alt-volup-r/h does not do anything special TEST=make newsizes shows we save 124 bytes in hammer RW. Change-Id: I92770fd6b8ff90780162a6b1de428a550bb44e9b Reviewed-on: https://chromium-review.googlesource.com/495967 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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