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* eCTS: Fix alignment of test resultsstabilize-9693.BDaisuke Nojiri2017-06-284-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the alignment of test results. It also displays 'YES' or 'NO' instead of '1' or '0' for expected string columns: TEST NAME TH_RC DUT_RC TH_STR DUT_STR RESULT success_test SUCCESS SUCCESS YES YES PASS fail_dut_test SUCCESS FAILURE YES YES PASS fail_th_test FAILURE SUCCESS YES YES PASS fail_both_test FAILURE FAILURE YES YES PASS bad_sync_test BAD_SYNC SUCCESS YES YES PASS bad_sync_both_test BAD_SYNC BAD_SYNC YES YES PASS hang_test SUCCESS DID_NOT_END YES YES PASS did_not_start_test DID_NOT_END DID_NOT_START YES YES PASS BUG=chromium:664309 BRANCH=none TEST=Run cts.py -m meta Change-Id: I7d266b9a6458fcabafa4da484b54d9d1dffbad61 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/545257 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f4: fix flash_physical_protect_now behaviorWei-Ning Huang2017-06-283-115/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash_physical_protect_now(), which is called when EC_FLASH_PROTECT_ALL_NOW is set, should protect the entire flash temporarily until reboot. Current behavior enable flash protect on all region permanently. The correct implementation should be writing an invalid key to the flash controller to disable flash flash only temporarily until reboot. Since the implementation of flash-stm32f3 and flash-stm32f4 is almost the same after restoring the changes made in commit 35f4d8acaa40050f10158459a04e0bf9b24149c6, we merge to file by creating a symlink from flash-stm32f3.c to flash-stm32f4.c to reduce code duplication. BRANCH=none BUG=b:37584134 TEST=on eve: 1) `ectool --name=cros_tp flashprotect` Flash protect flags: 0x00000008 wp_gpio_asserted 2) `flashrom -p ec:type=tp --wp-enable 3) `ectool --name=cros_tp reboot_ec` 3) `flashrom -p ec:type=tp --wp-status` WP: status: 0x80 WP: status.srp0: 1 WP: write protect is enabled. WP: write protect range: start=0x00000000, len=0x00040000 4) `ectool --name=cros_tp flashprotect`, all_now should present Flash protect flags: 0x0000000f wp_gpio_asserted ro_at_boot ro_now \ all_now 5) `ectool --name=cros_tp reboot_ec; sleep 0.3; \ ectool --name=cros_tp rwsigaction abort` to stay in RO. In EC console, `flashinfo`, should show that only RO is actually flash protected: Protected now: YYYYYY.. 6) `flashrom -p ec:type=tp -w ec.bin -i EC_RW` works 7) `make BOARD=ryu -j` works (for testing flash-stm32f3.c) Change-Id: Ia7a60ae8b3084198abb468e4fc8074b4445d6915 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/549681 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* vboot_hash: Don't auto-start hashing in recovery modeShawn Nematbakhsh2017-06-271-1/+11
| | | | | | | | | | | | | | | | | | | | | If we have requested the host to go to recovery mode, the host will usually not need an RW hash because it won't do EC SW sync. Therefore, do not auto-start calculation of our hash if we've requested recovery. This may avoid past recovery-breaking bugs due to unexpected RW contents. If the host does need the hash after all, it will manually request that the computation start. BUG=chromium:612966 BRANCH=None TEST=Boot to recovery mode on kevin, verify that "hash start" print is not seen on UART. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I66d2d74398357dfe30e39882feec8cfba4cc945c Reviewed-on: https://chromium-review.googlesource.com/540695 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: delay flash_erase deferred task so EC_CMD_FLASH_ERASE can completeWei-Ning Huang2017-06-271-1/+2
| | | | | | | | | | | | | | | | | | | | Add a delay before flash_erase deferred started so the task does not halt CPU, and cause the response of EC_CMD_FLASH_ERASE to not be delivered. When the above situation happens the host I2C controller will timeout. A 100ms delay should be long enough on any board to allow the response to be sent. BRANCH=none BUG=b:38018926 TEST=on eve units where flashrom always fail: `flashrom -p ec:type=tp -w ec.bin` succeeds. Change-Id: I399a60064392da41a3e27f8630175ab427047ab7 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/547375 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com>
* eCTS: Convert mutex test suite to current formatDaisuke Nojiri2017-06-275-18/+22
| | | | | | | | | | | | | | | This patch updates the mutex test suite so that it can be run within the current framework. BUG=chromium:736155 BRANCH=none TEST=run cts.py -m mutex test name TH_RETURN_CODE DUT_RETURN_CODE TH_STR DUT_STR RESULT lock_unlock_test SUCCESS SUCCESS 1 1 PASS Change-Id: I69ee0857a0c633d7c6c8909f8c6f58ca6fd272ce Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/544790
* eCTS: Print start marker before syncDaisuke Nojiri2017-06-2723-352/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes each test print start marker before sync. This will allow us to distinguish the failure before even sync is attempted (CTS_RC_DID_NOT_START, thus probably caused by the previous test) and the failure caused by the hanging partner, in which case the one good and alive will be stuck in sync (and should return _DID_NOT_END or even better _BAD_SYNC once we implement timeout in sync). This patch also: * Adds did_not_start_test to and removes debug_test from meta suite * Consolidates test runner loops into common cts_main_loop * Removes dut_common.h and th_common.h * Removes debug print macro and CTS_DEBUG * Replaces all infinite loops after tests with task_wait_event(-1) * Removes meaningless comments and debug printfs * Removes CTS_TEST_ID_* * Adds sync() to task suite BUG=chromium:736104 BRANCH=none TEST=Run run_ects.sh and verify all tests pass Change-Id: I6ccdf26afac6b8e8cb16483c5d75e4e77e7962f4 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/545176
* eCTS: Convert hook test suite to current formatDaisuke Nojiri2017-06-275-195/+109
| | | | | | | | | | | | | | | | | | This patch updates the hook test suite so that it can be run within the current framework. BUG=chromium:736047 BRANCH=none TEST=cts.py -m hook test name TH_RETURN_CODE DUT_RETURN_CODE TH_STR DUT_STR RESULT test_init_hook SUCCESS SUCCESS 1 1 PASS test_ticks SUCCESS SUCCESS 1 1 PASS test_priority SUCCESS SUCCESS 1 1 PASS test_deferred SUCCESS SUCCESS 1 1 PASS Change-Id: I3e7f29da61e794b06b03241f3d7706c2db94b5be Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/545084
* eve: Check for left/right LED auto controlDuncan Laurie2017-06-271-2/+2
| | | | | | | | | | | | | | | | | | The Eve board defines left and right LEDs, but the LED control loop is checking for auto control to be disabled on the power/battery LED IDs. This is breaking factory testing for LED colors when the battery level is low because it is flashing RED and ignoring the colors that the factory software attempts to set. BUG=b:63049012 BRANCH=eve TEST=manual testing on Eve with low battery Change-Id: I65b822111b3054a5994d71ec4e2a089c487acf97 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/549740 Reviewed-by: Todd Broch <tbroch@chromium.org>
* chell: remove some console commands for space.Caveh Jalali2017-06-261-0/+10
| | | | | | | | | | | | | | | | the EC firmware build for chell ran out of space, so i'm turning off some CLI commands. i'm turning off all the commands we've already turned off for kevin (see board/kevin/board.h). TEST="make buildall -j" passes BUG=b:62356808 BRANCH=none Change-Id: Ie7191f841d826cefc8b17f5325b221842db2eb1d Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/544095 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* watchdog: Don't discard irqprio data due to CONFIG_LTOShawn Nematbakhsh2017-06-266-6/+6
| | | | | | | | | | | | | | | | | | | | | Don't discard irqprio data when the IRQ_PRIORITY macro is used directly (for watchdog / watchdog timer). This change is probably a NOP for all platforms, since the power-on default for the IRQ prio register seems to be zero, which is the same priority we're setting in our direct use of IRQ_PRIORITY. BUG=chromium:634701 BRANCH=None TEST=Verify 'prio_44' entry exists in irqprio section by checking ec.RO.map on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idaffc484a2ce4749c18212f179b3951ff570aed0 Reviewed-on: https://chromium-review.googlesource.com/545201 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add simplified sysrqDaisuke Nojiri2017-06-234-1/+51
| | | | | | | | | | | | | | | | | | | | On a keyboard-less, volume-button-less board, we support simplified sysrq handling. For Fizz, we use the recovery button to trigger sysrq event and holding it down to trigger warm reset. BUG=b:38418116,b:38417391 BRANCH=none TEST=On Fizz, try 1. Press recovery button and release -> sysrq sent 2. Press and hold recovery button -> warm reset 3. Press recovery button and power button -> enter recovery mode Change-Id: If8760319dba3df4545e9805b396ac89c241dae80 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/537817 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* genvif: Fix uninitialized variable accessShawn Nematbakhsh2017-06-231-3/+5
| | | | | | | | | | | | | | | Defects reported by Coverity. BUG=None TEST=`make buildall -j` BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I15e0809f8d97e75be522b6160346de6b59316395 Reviewed-on: https://chromium-review.googlesource.com/535837 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* eCTS: Add script to run tests and publish resultsDaisuke Nojiri2017-06-231-0/+118
| | | | | | | | | | | | | This script will run nightly in the lab and publish the results. Publishing results will be implemented later. BUG=chromium:735546 BRANCH=none TEST=Run run_ects.sh inside & outside chroot and verify all tests pass. Change-Id: I405ea601eff33f1a4328f2606c8bb4050ff8d253 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/543681
* nds32: add software floating point library routinesDino Li2017-06-232-0/+196
| | | | | | | | | | | | | | | | We need to add a few library routines for sensor task. Routines added are taken from nds32's library. BRANCH=none BUG=none TEST=Add sensor task to reef_it8320 board. Test screen rotation functionality on reef_it8320. Change-Id: I2eee33f897b38e05bddd30b16f875944259b2c0d Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/527537 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* eCTS: Close ttyDaisuke Nojiri2017-06-232-2/+7
| | | | | | | | | | | | | This patch makes cts.py close tty files explicitly. BUG=none BRANCH=none TEST=cts.py -m meta Change-Id: Ifebfdd9607a603075492a59b5fb588e3cbc4ab12 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/544106 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eCTS: Strip board serial stringDaisuke Nojiri2017-06-231-4/+11
| | | | | | | | | | | | | | | | | | If we don't strip a serial string read from a file, TH serial doesn't match with the one read from lsusb. It causes TH to be recognized as a DUT. This patch also makes error messages more helpful when DUT is not found or multiple DUTs are connected. BUG=none BRANCH=none TEST=cts/cts.py -m meta, task Change-Id: Ifcf96089b9620ef8809a7d2924dacf67d3af419c Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/542019 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eCTS: Switch execution environment to chrootDaisuke Nojiri2017-06-231-1/+1
| | | | | | | | | | | | | | | | Openocd is upgraded to 0.10.0, which supports stm32l476. So, now we can run eCTS inside chroot. This allows new developers to spend no time on setting up software as all necessary tools (e.g. specific version of make, openocd, lsusb, ARM toolchains) come with cros_sdk. BUG=chromium:653949 BRANCH=none TEST=cts/cts.py -m meta Change-Id: Iba7ba94e95ceadcedcb53b76e47054ba1b2b47dd Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/542017 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eCTS: Check order and expectation of test resultsDaisuke Nojiri2017-06-2319-199/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the framework verify not only the result but also the execution order of the tests. It also allows each test to specify expected return code and strings printed by TH and DUT. The final test results depends on the return code and the expectation. Therefore, the output now includes 'RESULT' column showing PASS or FAIL: test name TH_RETURN_CODE DUT_RETURN_CODE TH_STR DUT_STR RESULT test_task_switch SUCCESS SUCCESS 1 1 PASS test_task_priority SUCCESS FAILURE 1 1 FAIL test_stack_overflow DID_NOT_END DID_NOT_END 1 1 PASS Additionally, this patch: * Adds CTS_RC_DID_NOT_START and CTS_RC_DID_NOT_END to indicate whether the test did start or end, respectively. * Makes stack overflow test check whether stack overflow was detected and reboot occurred * Removes post_corruption_test and conflict test since now the test results are stricly compared against expected results. * Fixes gpylint errors. BUG=none BRANCH=none TEST=Run gpio, meta, timer, interrupt, and cts/cts.py -m task Change-Id: I3b7005236e705dcac0c8f4711b44c85ff9a4f676 Reviewed-on: https://chromium-review.googlesource.com/538878 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* eCTS: Add stack overflow testDaisuke Nojiri2017-06-232-1/+27
| | | | | | | | | | | | | | | | This patch adds a test for stack overflow detection. CTS task tries to overflow by calling a function recursively. This function sleeps to incur context switch, where stack overflow is checked. Reboot is expected but not checked. BUG=chromium:663873 BRANCH=none TEST=cts.py -m task Change-Id: I6ad98d209acf873d2d23b48bac6fc751fa8c2f74 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/410283 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power/rk3399: Table-based power sequencingPhilip Chen2017-06-221-76/+107
| | | | | | | | | | | | | | | | | We need to refactor power/rk3399.c to make it more flexible to support different power sequences for upcoming follower boards. BUG=b:62640322 BRANCH=none TEST=manaully test on scarlet and kevin: S0->S3->S0 and S0->S3->S5->G3->S5->S3->S0 work. Change-Id: I70cdcbaba046bfab4fe832eca58f30524e99e6de Reviewed-on: https://chromium-review.googlesource.com/540783 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Remove big and pit boardsShawn Nematbakhsh2017-06-2223-3435/+4
| | | | | | | | | | | | | | | | | Remove big and pit boards along with several now-obsolete CONFIGs / source files. BUG=chromium:735109 TEST=`make buildall -j` BRANCH=None CQ-DEPEND=CL:544681 Change-Id: Ieb784bd36157fd1f6240cd19de6e6d12191a8097 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/540667 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hammer: prepare and update the trackpad firmwareChun-Ta Lin2017-06-221-22/+168
| | | | | | | | | | | | | | | Implement the necessary bits for updating the trackpad firmware over I2C, primarily following the protocol from open source driver. BRANCH=none BUG=b:35587174 TEST=Manually update firmware and confirmed reported FW version changed. Change-Id: Ice5098269803f524de0b6a853f5a98f28382a7fb Reviewed-on: https://chromium-review.googlesource.com/532765 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core/cortex-m0/curve25519: Import fast curve25519 implementationNicolas Boichat2017-06-226-0/+3576
| | | | | | | | | | | | | | | | | | | | | Import finely tuned curve25519 implementation from https://munacl.cryptojedi.org/curve25519-cortexm0.shtml (http://munacl.cryptojedi.org/data/curve25519-cortexm0-20150813.tar.bz2) which is released in the public domain for some files, CC0 for others. This is a plain copy (only doing a pass of dos2unix conversion and removing trailing tabs/spaces), later patches integrate the code with the rest of the EC code. BRANCH=none BUG=b:62813194 TEST=None (see next patch) Change-Id: Ibd394d031433c31d4755a880b0e8d74b63540fbf Reviewed-on: https://chromium-review.googlesource.com/540961 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* g: cr50: update INFO1 mask when corrupting the second imageVadim Bendebury2017-06-213-17/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The INFO1 mask field contents serves as input for the rollback protection mechanism, when the RO decides if an RW is allowed to run on the device. The existing code updates INFO1 mask to match the lowest rollback priority of the two images (RW_A and RW_B) present on the device. INFO1 mask should be also updated when the current image is endorsed by the host. In this case the alternative RW is destroyed, so the INFO1 mask could be set based solely on the currently running image. This patch refactors the code to allow setting INFO1 mask based on one or both RW headers' contents. BRANCH=cr50 BUG=b:62138152 TEST=verified that "normal" INFO1 mask updates still work as before, the mask is modified to match the image with the lowest rollback priority. Also verified that when the VENDOR_CC_INVALIDATE_INACTIVE_RW command is received the INFO1 mask is updated based on the currently running image. Change-Id: I23172388674e1f3a4c2489e139dd197a84029f54 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/541738 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Add fizz-no-vmtest-pre-cq to the pre-cq setPrathmesh Prabhu2017-06-211-1/+1
| | | | | | | | | | | | | Because ec is used by the fizz board BUG=chromium:734783 TEST='cbuildbot --remote fizz-no-vmtest-pre-cq' passes BRANCH=None Change-Id: Ib3f7cf5b798e805ed197c79999ff6fc61b07f561 Reviewed-on: https://chromium-review.googlesource.com/540287 Tested-by: Prathmesh Prabhu <pprabhu@chromium.org> Reviewed-by: Aviv Keshet <akeshet@chromium.org>
* Poppy: Configure camera PMIC to low power mode.Divagar Mohandass2017-06-211-0/+6
| | | | | | | | | | | | | | | | This change will configure camera PMIC to low power mode in S3 and S0ix sleep state and resumes it in S0 state. BUG=b:62779726 BRANCH=None TEST=`Build/Flash EC and verify the PP3300_DX_CAM signal is toggling during S3/S0ix cycle.` Change-Id: I9f376762100ac9b208df4a39160e4acd3b7b925e Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://chromium-review.googlesource.com/539316 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rwsig: Fix mapped read location for rwsig / pubkeyShawn Nematbakhsh2017-06-213-13/+22
| | | | | | | | | | | | | | | | | | | | Mapped reads are relative to CONFIG_EC_*_STORAGE_OFF, not CONFIG_R*_MEM_OFF. The previous implementation happened to work for internal mapped storage (eg. stm32) but failed for external mapped storage which is copied to SRAM before execution (eg. npcx). BUG=b:62841029 TEST=Verify sysjump works again on eve/poppy/soraka. Verify sysjump and sig verification continues to work on fizz and stm32. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id51ce5697555eea38b246b58dbf47f22d4befaa7 Reviewed-on: https://chromium-review.googlesource.com/541861 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32f4: clock stm32f412 at 96MHzWei-Ning Huang2017-06-218-10/+54
| | | | | | | | | | | | | | | | | | | | | | On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks can be in the right range. When APBX prescaler != 1, it results in 2x timer clocks on both APB1 and APB2. We added a new clock_get_timer_freq() function for stm32 to get timer specific clock frequency so we can return 2x timer clocks when APBX != 1. Flash latencies also need to be changed when we clock at 96MHz, the FLASH_ACR_LATENCY defines are moved into the variant-specific switches so each board can defined latency when setting CPU clocks. BUG=b:38077127 TEST=`make BOARD=rose -j`, touch performance improved by 2x. Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444 Reviewed-on: https://chromium-review.googlesource.com/539375 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* ps8751: assert reset for at least 1ms.Caveh Jalali2017-06-202-4/+16
| | | | | | | | | | | | | | | | | | the 1ms reset hold time isn't in the ps8751 datasheets (yet), but that's what our parade support contact recommended. i'm applying this fix to reef (electro) and coral as these two boards were missing any sort of reset hold time. other boards using the ps8751 seem to already have a 1ms or 10ms delay. TEST=rebuilt, reload EC image on electro... no ill effects noted. BUG=b:62642003 BRANCH=reef Change-Id: I39a989375e789118d062f82e9baaa041e5e6b033 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/540742 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* g: remove obsolete dcrypto_init definitionMarius Schilder2017-06-201-2/+0
| | | | | | | | | | | | | | | | | No boards are referencing old dcrypto_init at this point; all have moved to dcrypto_init_and_lock BUG=none BRANCH=cr50 TEST=buildall Change-Id: I04c96608c5459470d87e67046912ca7c02e6332a Reviewed-on: https://chromium-review.googlesource.com/540779 Commit-Ready: Marius Schilder <mschilder@chromium.org> Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* stm32: flash: enable data and instruction cache properlyWei-Ning Huang2017-06-202-1/+19
| | | | | | | | | | | | | | | | | | | | | The flash controller of STM32F4 and STM32L4 supports data and instruction caching. Enable them properly. BRANCH=none BUG=b:38077127 TEST=on rose, > rw 0x40023c00 read 0x40023c00 = 0x00000701 Touch process loop is 5% faster. Change-Id: Ibb28c0ed0c6a293547d5f0f7c6962f36fa417dd3 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/497230 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec_commands: Fix portability issuesDuncan Laurie2017-06-201-2/+4
| | | | | | | | | | | | | | | Recent changes broke the portability of this header file. Fix the ACPI guards so it can be used in coreboot. BUG=b:36024430 BRANCH=none TEST=make -j buildall (as usual many haven boards fail) Change-Id: I0d737e7aad7ead90289b43db09352092ef7e3e98 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/539135 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* hammer: Adjust trackpad dimensionsNicolas Boichat2017-06-191-5/+4
| | | | | | | | | | | | BRANCH=none BUG=b:35582031 TEST=Flash and boot hammer, no more trackpad dimension mismatch error. Change-Id: If4bd9db456617a52d1890543e7cae34a563122dd Reviewed-on: https://chromium-review.googlesource.com/523502 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add system_can_boot_ap APIDaisuke Nojiri2017-06-192-0/+38
| | | | | | | | | | | | | This API checks battery charge level and current power supply to determine whether the AP has enough power to boot or not. BUG=b:38462249 BRANCH=none TEST=make buildall Change-Id: I489f7ea92f230701b8f18c94d3e698aad90b4a03 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/517272
* Fizz: Verify and jump to RW imageDaisuke Nojiri2017-06-193-1/+49
| | | | | | | | | | | BUG=b:37316498 BRANCH=none TEST=Boot Fizz Change-Id: Iaceb64bcf5d54145c26e86ce62a14d5732a22e78 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/517406 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* KBL/SKL: Add wait between DSW_PWROK and PWRBTNDaisuke Nojiri2017-06-195-0/+39
| | | | | | | | | | | | | | | | This patch adds wait between DSW_PWROK and PWRBTN assert. It is required to be 95 msec or longer for Kaby Lake and Sky Lake. Refer to the timing diagram for G3 to S0 on Sky Lake or Kaby Lake platform design guide for details. BUG=b:62584658 BRANCH=none TEST=On Fizz, measured time between DSW_PWROK high and PWRBTN assert for 1:AC plug-in, 2:recovery+power press, 3: reboot ec command. Change-Id: I89a14ac9a49e20a332bd662d90be62f8ea23b003 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/534901
* g: upgrade_fw: limit updates after a hard resetMary Ruthven2017-06-191-2/+19
| | | | | | | | | | | | | | | | | | | | | | | Reject updates for the first 60 seconds after a hard reboot. This should prevent people from using the reboot at the end of an update to get around the update rate limiting. Reboots don't happen during normal cr50 operation, so this should not prevent updates. It will just prevent updating cr50 many times in a row. This change does not limit updates after deep sleep or POR. BUG=b:62097097 BRANCH=cr50 TEST=Try to update cr50 two times. Verify that on the second time the update is rejected. Put cr50 into deep sleep, wake it up and verify it can be updated immediately. Get cr50 to do a POR and verify it can be updated immediately. Change-Id: I828ef210e1c5bcf59d4753b8178ee4e1369d5d36 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/520727 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* task: Wait for HOOK_INIT completion before scheduling tasksShawn Nematbakhsh2017-06-197-24/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until HOOK_INIT has completed, do not allow any tasks other than HOOKS or IDLE to be scheduled. Programmers often make the assumption that a HOOK_INIT function is guaranteed to be run before task code that depends on it, so let's make it so. BUG=chromium:649398 BRANCH=None TEST=Manual on kevin, compare boot without patch: ... [0.004 power state 0 = G3, in 0x0008] <-- from chipset task RTC: 0x00000000 (0.00 s) [0.004 power state 4 = G3->S5, in 0x0008] RTC: 0x00000000 (0.00 s) [0.005 clear MKBP fifo] [0.006 clear MKBP fifo] [0.006 KB init state: ... <-- from keyscan task [0.012 SW 0x05] [0.155 hash start 0x00020000 0x00019a38] [0.158 HOOK_INIT DONE!] ... to boot with patch: ... RTC: 0x58cc614c (1489789260.00 s) [0.004 clear MKBP fifo] [0.005 clear MKBP fifo] [0.010 SW 0x05] [0.155 hash start 0x00020000 0x000198e0] [0.157 HOOK_INIT DONE!] ... Also, verify kevin boots to OS and is generally functional through sysjump and basic tasks, and verify elm (stm32f0 / cortex-m0) boots. Change-Id: If56fab05ce9b9650feb93c5cfc2d084aa281e622 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/456628 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* math_util: Use HW instruction for int_sqrtf when availableShawn Nematbakhsh2017-06-192-1/+27
| | | | | | | | | | | | | | | | | | | | | | | Cortex-M4 supports a floating point square root function that takes 14 cycles to execute, which is a speed improvement over the existing binary search, and saves flash space. BUG=chromium:687624 BRANCH=None TEST=On kevin, verify that both sqrtf methods (binary search vs HW instruction) have identical results for fractional input (eg. sqrt(15.999999) = 3), except when floating point representation of square root rounds up to an integer. Verify identical results for all integers [-100, 16793602). Note that 16793602 is the first integer for which the floating point representation of sqrt rounds up to an integer. Also verify basic motion sense functions on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I8521c9a28c958b340ca83c37342253e424df0c91 Reviewed-on: https://chromium-review.googlesource.com/537734 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* eCTS: Refactor return code handlingDaisuke Nojiri2017-06-172-18/+44
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds host only return codes to cts.rc and derive names from there. BUG=chromium:664309 BRANCH=none TEST=cts.py -m task, interrupt, gpio test name TH DUT debug_test SUCCESS SUCCESS success_test SUCCESS SUCCESS fail_dut_test SUCCESS FAILURE fail_th_test FAILURE SUCCESS fail_both_test FAILURE FAILURE bad_sync_and_success_test BAD_SYNC BAD_SYNC bad_sync_both_test BAD_SYNC BAD_SYNC bad_sync_failure_test FAILURE BAD_SYNC hang_test SUCCESS NO_RESULT post_corruption_success NO_RESULT NO_RESULT Change-Id: I169b2466646d6236571a8a4c5d3e208d928b9dd2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/410282 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: handle board ID mismatch gracefullyVadim Bendebury2017-06-164-4/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If Cr50 happens to start on a chip where Board ID programmed in INFO1 does not match the contents of the RW header, it means that for some reason the other RW is not operational and the current image is the only viable one. In this case the Cr50 starts but operates in limited mode (only commands for updating the image and reporting state are handled). In this case the reason for recovery could be seen on the Recovery screen, and the update could be done once Chrome OS boots in recovery mode. BRANCH=none BUG=b:35586335 TEST=verified the following: - if an image with wrong board ID is started, it tries to fall back (sets the counter to a value above threshold and reboots) - if the fallback fails, the image keeps running in the limited capabilities mode but the update is possible, observed that the new image took over worked after powercycling the device. - observed proper error message on the recovery screen showing where the error comes from Change-Id: I46ba75392f8e891bb8503fb15aea2c56b5805e83 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/535978 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* eCTS: Limit tty reads by boot countsDaisuke Nojiri2017-06-162-242/+115
| | | | | | | | | | | | | | | | | | | | | | | | Currently, read_tty reads characters from tty as long as there is something to read. This causes read_tty to loop forever if the board is in reboot loop. This patch makes cts.py stop reading tty if boot count exceeds max_boot_count. Reboot is detected by detecting REBOOT_MARKER. This patch also does: - Remove debug option: This adds complexity for no real value. Developers should debug tests using regular tools (make, uart console, etc.). - Remove html output. Nobody use it. Should be redone when it's needed using proper libraries. BUG=chromium:664309 BRANCH=none TEST=cts.py -m task/gpio/interrupt Change-Id: I51d1dd51c4097e8115ef04ad46853720295141b4 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/410281 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eCTS: Hide expected messagesDaisuke Nojiri2017-06-162-34/+92
| | | | | | | | | | | | | | | | | | | | | | | This patch hides expected messages from output to the terminal and reorganizes log directory as follows: - All test output goes under /tmp/ects/$dut/$module - Openocd output is recorded in openocd.log - uart outputs are recorded in uart_th.log and uart_dut.log - build output is recorded in build.log - Check exit code from all subprocess calls - Dump build log if build fails - Dump openocd log if openocd fails BUG=chromium:664309 BRANCH=none TEST=cts.py --setup and build images in chroot then run cts.py -m meta outside chroot. Change-Id: I13294c3bf777ad7ae590459d3cf5aea405d59f96 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/409536 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mn50: fix usb_updateNick Sanders2017-06-165-4/+6
| | | | | | | | | | | | | | | Add support for update related vendor commands in mn50 by relocating relevant code from board/cr50 to chip/g. BUG=b:36910757 BRANCH=None TEST=./extra/usb_updater/usb_updater -d 18d1:502a build/mn50/ec.bin Change-Id: Iec0fe5585b5b6eb099f9254dfb0e5b02d5106abc Reviewed-on: https://chromium-review.googlesource.com/537999 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* eve: Make sure both LEDs are updated when charger is connectedScott Collyer2017-06-161-46/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an external charger is connected, only the LED on the side the charger is connected should be on, the other side should be off. The existing LED behavior was incorrect in that only the side that was charging was being updated and the other side would remain in its previous state. This CL adds a fix so that if only one LED is being controlled, the other side is always turned off. In addition, the logic for double tap events was changed slightly so that if a double tap event is in progress and a charger is connected, the new state will be updated as soon as the charge state is changed instead of waiting for the double tap event to complete. BUG=b:62481906 BRANCH=eve TEST=Manual With battery level < 15% so that both LEDs are red when the charger isn't connected, connect charger and verified that the LED on the side the charger is connected turns white and the LED on the other side turns off. Change-Id: I7462629409496383adb43445e732dd6ca2f9f589 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/537960 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* Use celes-pre-cq instead of strago-pre-cqBernie Thompson2017-06-161-1/+1
| | | | | | | | | | | | | | The stago build is not well kept after, as it is not used in production, celes however is. BUG=chromium:734103 TEST=None Change-Id: Ie62a4729192fe63d18348f47105a2585c9e4f5be Reviewed-on: https://chromium-review.googlesource.com/538571 Commit-Ready: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Yixiang Li <yixiang@google.com>
* cr50: prepare to release version 0.0.21Vadim Bendebury2017-06-162-2/+2
| | | | | | | | | | | BRANCH=cr50 BUG=None TEST=built an image, observed version number. Change-Id: I2717530abb92383e1d0260580bed81e00f4f21bb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/538162 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* npcx: i2c: change i2c settings for better timing.CHLin2017-06-151-16/+4
| | | | | | | | | | | | | | | | | | | | | The setup time of original i2c setting which i2c freq is 1MHz is closed to the margin of the spec. This CL improves the setup time with a new setting. (For example, in npcx evb, measured setup time now is about 480 ns.) This CL also removes the timing settings of higher i2c source clock frequencies which are not used so far to save the code size. BRANCH=none BUG=b:38217035 TEST=No build error for make buildall; run stress test with i2cxfer and i2cscan on gru with 400K and 1MHz i2c freq. Change-Id: I5428a7dab1d935fd428ee9012604813e752cead8 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/527739 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cleanup: motion_sense: Remove driver data structure externsShawn Nematbakhsh2017-06-1516-52/+64
| | | | | | | | | | | | | | | Driver data structs are now accessed through the drv_data pointer. BUG=chromium:733352 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I8fedb425708a08ae6900ade6f17967fe2bc75ebf Reviewed-on: https://chromium-review.googlesource.com/537217 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power/skylake: Ensure panic data is backed up before PMIC resetFurquan Shaikh2017-06-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On PMIC reset, VCC power rail goes down thus resulting in loss of panic data. Thus, provide a chance to the chip to backup panic data if available. BUG=b:62076222 BRANCH=None TEST=make -j buildall 1. > crash divzero > panic === PROCESS EXCEPTION: 06 ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :00000001 r5 :00000000 r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : Divide by 0 mmfs = 2000000, shcsr = 0, hfsr = 0, dfsr = 0 2. > crash assert > panic === PROCESS EXCEPTION: 00 ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :dead6663 r5 :000000a4 r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : mmfs = 0, shcsr = 0, hfsr = 0, dfsr = 0 3. > crash watchdog > panic === PROCESS EXCEPTION: 3c ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :dead6664 r5 :0000000a r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : mmfs = 0, shcsr = 0, hfsr = 0, dfsr = 0 4. > crash unaligned > panic === PROCESS EXCEPTION: 06 ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :200c0d9e r5 :00000000 r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : Unaligned mmfs = 1000000, shcsr = 0, hfsr = 0, dfsr = 0 Change-Id: Ife5c9bbc12dcf6c4922f18b7530b21a3b87e65b3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/530138
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