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* ectool: do not try other communication methods for none cros_ec devicesstabilize-9765.76.Bstabilize-9765.65.Bstabilize-9765.39.Brelease-R61-9765.BWei-Ning Huang2017-08-102-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are none cros_ec devices running EC codebase connected to chromebook, which can be accessed by ectool with `cros_ec --name=SOME_DEV ...`. In the case when SOME_DEV is not found, do not fallback to other communication methods such as LPC or I2C, since ectool will instead get the reply of real cros_ec device. BRANCH=none BUG=b:64468324 TEST=on poppy, `ectool --name=cros_tp version` should show: `Unable to establish host communication Couldn't find EC` Change-Id: I2ac232122e0f928703f7607da365d5c1dc6f7194 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/604977 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit 25d281a42bd1e3cbf997e658ff9ae784bbecea20) Reviewed-on: https://chromium-review.googlesource.com/609620 Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Commit-Queue: Wei-Ning Huang <wnhuang@chromium.org>
* cr50: modify tpm_endorse() error reporting logicstabilize-9765.7.BVadim Bendebury2017-07-202-10/+30
| | | | | | | | | | | | | | | | | | Using zero to represent success make it cleaner when processing return values of this function. Also, let's report different failures using different error values. Note that nobody checks this function's return value yet. BRANCH=cr50 BUG=b:63686091 TEST=none Change-Id: If25d30e637701f6c37f3ce75e5a5d5315e0e86e9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/579583 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* stm32f4: Set unique ID properlyGwendal Grignou2017-07-201-1/+5
| | | | | | | | | | | | | | | | | | Unique device ID register (96 bits) is at a different place on STM32F4 compared to other STM32. BUG=none BRANCH=none TEST=Using board_read_serial() from hammer/board.c in sweetberry/board.c, confirmed that we can extract and assign a unique USB serial number. Change-Id: Idb257f0f20422482c729a2b97b4b16ee231ca4d9 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/579575 Commit-Ready: Gwendal Grignou <gwendal@google.com> Tested-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: Add case closed debugging V1 configurationRandall Spangler2017-07-2011-11/+1249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the CCD configuration module, and the console commands to control it. It is not wired up to any of the CCD capabilities; that's coming in the next CL. Briefly: * CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to print it. * CCD can be Locked, Unlocked (some capabilities), or Opened (all capabilities), using the ccdlock / ccdunlock / ccdopen commands. * CCD config can be restricted by setting a password via ccdpass. * Individual config capabilities can be set via ccdset. Some of those will be used to gate access to things like write protect and UARTs. Others affect the requirements for ccdunlock / ccdopen (for example, is physical presenc required). * The entire config can be reset via ccdreset. If only unlocked, config that is restricted to Opened is not reset. * If CR50_DEV=1, ccdoops will force-reset and open the config. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual with CR50_DEV=1 build gpioget # make sure GPIO_BATT_PRES_L=0 ccdlock # lock, because CR50_DEV=1 builds start unlocked ccdinfo # locked, flags=0, all capabilities default ccdpass # access denied (we're locked) ccdreset # access denied ccdset flashap always # access denied ccdunlock ccdinfo # unlocked ccdpass foo ccdinfo # flags=2 (password set when unlocked) ccdset flashap always # access denied ccdset uartectx unlesslocked ccdinfo # yes, uartectx permission changed ccdlock ccdunlock # fails without password ccdunlock bar # wrong password ccdunlock foo # busy (wait 3 sec) ccdunlock foo ccdreset ccdinfo # no password, flags 0, capabilities all default ccdopen # requires physical presence; tap power or use 'pp' ccdset uartectx unlesslocked ccdset batterybypasspp ifopened ccdpass baz ccdinfo # password set, flag 0, ccdset changes worked ccdunlock ccdreset ccdinfo # uartectx back to ifopened, password still set ccdopen baz # still requires physical presence ccdset opennolongpp always ccdlock ccdopen baz # no pp required ccdset unlocknoshortpp unlesslocked ccdlock ccdopen baz # short pp sequence required (3 taps) ccdlock ccdunlock baz # short pp sequence required ccdopen baz # pp not required ccdset unlocknoshortpp always ccdlock testlab open # access denied testlab enable # access denied ccdunlock baz testlab open # access denied testlab enable # access denied ccdopen baz testlab enable # requires short pp ccdinfo # flags 1 ccdreset ccdinfo # no password, flags=1, caps all default ccdlock testlab open ccdinfo # opened testlab disable # requires short pp; let it time out ccdinfo # still opened, flags=1 ccdlock ccdoops # backdoor in CR50_DEV images to force-reset CCD ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab) ccdreset rma ccdinfo # flags = 0x400000, everything but Cr50FullConsole always ccdreset # back to flags=0, all default Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9 Reviewed-on: https://chromium-review.googlesource.com/569439 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kevin: disable reporting of unneeded host eventsNick Vaccaro2017-07-201-0/+15
| | | | | | | | | | | | | | | Disable reporting of EC events to the linux kernel that are not used by kevin's kernel. BRANCH=none BUG=chromium:637061 TEST=make buildall passes, lid close puts AP into suspend, lid open turns on display Change-Id: I7841294aec0853f4820a262ec14e8ad6037e1060 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/503536 Reviewed-by: Shawn N <shawnn@chromium.org>
* power/rk3399: Assert SYS_RST_L from S5 to S3Philip Chen2017-07-201-1/+1
| | | | | | | | | | | | | | | | To fix a previous mistake and align the SYS_RST control for all rk3399 boards. BUG=b:62640322 BRANCH=none TEST=build scarlet with 'CHIPSET_POWER_SEQ_VERSION == 2' Change-Id: Iab91ea713c512afd10f15df38fbdb2dd6c62cb23 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/578306 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* CNL: Don't build CNL in tests w/o chipset tasks.Aseda Aboagye2017-07-201-0/+1
| | | | | | | | | | | | | | | | | | | When compiling target tests for a board that defines CONFIG_CHIPSET_CANNONLAKE, the build would fail due to the chipset code being built without a chipset task. This commit removes the Cannonlake chipset code when building a test that does not have a chipset task (and use Cannonlake). BUG=None BRANCH=None TEST=make -j BOARD=zoombini tests; verify that build succeeds. Change-Id: I15a5729db64314a8d6566be879f7c356ffa95725 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/578316 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* flash_ec: add nefario for supportCaesar Wang2017-07-201-0/+3
| | | | | | | | | | | BUG=b:63408169 BRANCH=none TEST=utils/flash_ec --board=nefario Change-Id: Ic13d6257a548d6c759542f3e8e679b0ce2b4de51 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/578694 Reviewed-by: Philip Chen <philipchen@chromium.org>
* core: Fix missing debug symbol when enabling LTOChe-yu Wu2017-07-191-1/+1
| | | | | | | | | | | | | | | Add "-g" to "LDFLAGS" for preserving debug symbol when enabling LTO. BUG=chromium:742697 BRANCH=none TEST=make BOARD=eve -j arm-none-eabi-objdump -h build/eve/RW/ec.RW.elf | grep debug_loc 7 .debug_loc 00027bf0 00000000 00000000 0009a549 2**0 Change-Id: I6b2b00846ce71002262a10357fd4dccbe82b6e6f Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/575312 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* flash_ec: Add support for servo micro.Aseda Aboagye2017-07-191-30/+53
| | | | | | | | | | | | | | BUG=chromium:740026 BRANCH=maybe some FW branches. TEST=Use a servo_micro, flash kevin, verify kevin boots. TEST=Repeat above test with a servo_v2. Change-Id: I377384f44e85c4a6032871aa4eebd208fd6e3336 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/572142 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* hammer: adjust stack size for trackpad taskChun-Ta Lin2017-07-191-1/+1
| | | | | | | | | | | | | | | | | Current stack size is so well-calculated that printing debug message will cause stack overflow and triger reboots. BRANCH=none BUG=none TEST=make BOARD=hammer Change-Id: If90a4d99181e1e08b7ff69e12b5d54a19455cea9 Signed-off-by: Chun-Ta Lin <itspeter@google.com> Reviewed-on: https://chromium-review.googlesource.com/575116 Commit-Ready: Chun-ta Lin <itspeter@chromium.org> Tested-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: Che-yu Wu <cheyuw@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: Add physical presence state machineRandall Spangler2017-07-198-4/+403
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be used as part of case closed debugging configuration. Currently, this only adds the state machine, and a test command which is available when CR50_DEV=1. It also adds a new sleep mask flag for physical presence detect, instead of oveloading FORCE_NO_DSLEEP. The physical presence state machine supports both short (tap 5 times in 15 seconds) and long (short, followed by 4 more taps 1-5 minutes apart) sequences. It will call a callback function at the end of the sequence, so that multiple things can each request physical presence in turn. This will be used by ccdopen / ccdunlock / testlab commands for CCD V1. Eventually, CCD config will replace the unlock sequence handling in wp.c. But for now, we don't touch that. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual Short sequence: pp short pp pp pp # See "Physical presence good" Timeout pp short pp # 15 sec later, get timeout error Long sequence: pp long pp pp pp (wait 2 sec) pp (wait 2 sec) pp # See "PP good" Long sequence, presses too fast: pp long pp pp pp pp # See "PP L too soon" (wait 2 sec) pp (wait 2 sec) pp # See "Physical presence good" Abort: pp short pp abort # See "Physical presence aborted" Change-Id: I09da81ad11d328e7d7740c3fe838a5f67d7b8708 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/568796 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* zoombini: Add eSPI VW signals support.Aseda Aboagye2017-07-194-12/+23
| | | | | | | | | | | | | | | | | | This commit adds support for the virtual wire signals over eSPI. Additionally, the SLP_S0_L signal is added for the board and some minor changes are made to some GPIOs. BUG=None BRANCH=None TEST=flash zoombini image on npcx7 EVB with some modifications. Verify no panics or asserts are hit. Change-Id: I6ada270b3e3fc7e24b28a8da6ee9dcde707414fc Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/577054 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Allow core code to request its cross compilerPatrick Georgi2017-07-196-15/+24
| | | | | | | | | | | | | | | | | | | | | | | Instead of having to pass in both the board and the arch used there (which might be complicated in the light of different ECs with different arches), allow passing in the board and a set of cross compilers. The core/*/build.mk then pick the compiler that is responsible for them. The current method works just the same: If you've already set CROSS_COMPILE, no override happens. If you set neither CROSS_COMPILE nor CROSS_COMPILE_$arch, the same default as before this CL is set. BUG=none BRANCH=none TEST=emerge-{samus,kevin} chromeos-ec behave reasonably with adapted ebuild Change-Id: Icf1866f296412dd92ecfe134394224c49f7c3df5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/549344 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* skylake: Use SYS_RESET signal to trigger warm and cold resetFurquan Shaikh2017-07-181-23/+12
| | | | | | | | | | | | | | | | RCIN# signal is known to not work properly for performing a warm reset when the CPU is in a bad state. This results in the common key combo (Alt-Volup-r) not working to reset the host. Thus, use SYS_RESET signal instead to trigger both cold and warm chipset reset. BUG=chromium:721853 BRANCH=None TEST=make -j buildall Change-Id: I38663db96767d0aa03cd1aea0fe2a0cc5b771cd2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/575947 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* poppy: Keep power to base enabled in deep S3Furquan Shaikh2017-07-181-0/+27
| | | | | | | | | | | | | | | | | In deep S3, SLP_SUS# goes low which results in power to base being cut. For such cases, PMIC needs to be configured so that it keeps the power to base up. Use VREN register to keep PP5000_A rail enabled in deep S3. BUG=b:63251418 BRANCH=None TEST=make -j buildall. Verified that wake from base works in deep S3. Change-Id: Ice3ba56f1a7e52275c3afa332c29b5b252dded4d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/574619 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ec_commands: Fix more portability issuesShawn Nematbakhsh2017-07-181-1/+1
| | | | | | | | | | | | | | BUG=chromium:741711 BRANCH=None TEST=`make buildall -j`, also verify kevin kernel builds with new copy of ec_commands.h. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia7fab98d61ecac727a0007d6f59ab4c9047de049 Reviewed-on: https://chromium-review.googlesource.com/576231 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ec_commands: Add define for maximum number of PD portsShawn Nematbakhsh2017-07-182-0/+5
| | | | | | | | | | | | | | | | It's helpful for the host to know the maximum number of PD ports that can possibly exist in a cros-ec device. BUG=chromium:741711 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic8a9eb22dc0bf51c8f5e1dfe380ca8f187481070 Reviewed-on: https://chromium-review.googlesource.com/576138 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* power/rk3399: Fix the new power sequencing to support new boardstabilize-9756.BPhilip Chen2017-07-171-3/+6
| | | | | | | | | | | | | | | BUG=b:62640322, b:62269890 BRANCH=none TEST=build scarlet with POWER_SEQUENCING_VERSION == 2 && CHIP == stm32 Change-Id: I314b21a909324a7d4666569525d9daddd300abdb Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/572338 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* hammer: Enable Link-Time-Optimization CONFIG_LTONicolas Boichat2017-07-173-2/+3
| | | | | | | | | | | | | | | | | | | | | | | We need to add __keep to the USB descriptors, otherwise they get thrown away. Also, for some reason the optimized RWSIG task uses a little bit more stack space, so account for that: 1 RWSIG 00000000 0.264350 1096/2048 BRANCH=none BUG=b:63610290 TEST=make BOARD=hammer -j make newsizes build/hammer/RO/ec.RO.flat shrank by 2052 bytes: (37336 to 35284) build/hammer/RW/ec.RW.flat shrank by 3172 bytes: (50508 to 47336) Flash hammer, touchpad, keyboard, update all still work fine. Change-Id: I39ffd320dae883596ce481efc4adec6e3c23000b Reviewed-on: https://chromium-review.googlesource.com/567909 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: gpio: implement gpio_disable_interruptWei-Ning Huang2017-07-171-0/+13
| | | | | | | | | | | | | | | | gpio_disable_interrupt is missing for stm32, add it so board functions can use it. BRANCH=none BUG=b:63685022 TEST=`make BOARD=rose -j` Change-Id: Ibbdd8506540e7949fa110c26131dca028671be06 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/573981 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* eve: Remove discharge-when-full stateDuncan Laurie2017-07-161-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | With the bd99954 charger we do not need to discharge when full, so remove this config option and the setting of 94% for "full" battery. Note that this only affects the battery reporting state, the EVT systems (board <= 4) will still discharge when full (in order to prevent the charger noise) but they will now indicate that they are discharging in this state instead of appearing full. Newer boards (version > 4) will behave as expected. This is a compile time option so it isn't something I can easily support old boards with, but I think it is more important to do the right thing for new boards. BUG=b:35585628 BRANCH=eve TEST=test charge behavior when full on board version 6 Change-Id: I3dd46ae305107b17b3bf8e3ce71578d3400b0f79 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/573091 Reviewed-by: Shawn N <shawnn@chromium.org>
* eve: Remove PECI support from ECDuncan Laurie2017-07-161-0/+1
| | | | | | | | | | | | | Eve does not use PECI so disable it and remove from the resulting binary. BUG=b:35581264 BRANCH=eve TEST=build EC for Eve and ensure peci module is not included Change-Id: Ie87d789226b2b5f2162ea96cb001a5cb62359213 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/573083 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx7_evb: fix typos in the declaration of ADC3/4 channelsCHLin2017-07-161-2/+2
| | | | | | | | | | | | | | | | | | This CL fixes the typos of the enumeration values of ADC3 and ADC4 in the declaration of adc_channels[]. BRANCH=none BUG=none TEST=No build errors for make buildall. Test the image of npcx7_evb board on EVB. Change-Id: I510ad08f1dbc5ef668e28934d63cf73c7e5f5b5c Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/569498 Commit-Ready: Jun Lin <riverq@gmail.com> Tested-by: Jun Lin <riverq@gmail.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: Add support for chip variant npcx7m6gCHLin2017-07-162-3/+3
| | | | | | | | | | | | | | | | | | | | | This CL adds CHIP_VARIANT_NPCX7M6G to support another npcx7 ec SKU. Please note that the default setting in npcx7_evb is npcx7m6f. For the EVB using the 128-pins EC package, please change CHIP_VARIANT from npcx7m6f to npcx7m6g in build.mk. BRANCH=none BUG=none TEST=No build errors for make buildall; Set CHIP_VARIANT=npcx7m6g in board/npcx7_evb/build.mk; Build the image and test on EVB. Change-Id: I2f857e4f6524eab45930bac3cc209409d4a53ee8 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/569320 Commit-Ready: Jun Lin <riverq@gmail.com> Tested-by: Jun Lin <riverq@gmail.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* eve: Changes to incoporate gradients to LED transitionsScott Collyer2017-07-152-41/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current LED color changes are abrupt. This CL adds a new function which steps from one color (some RGB combo) to another gradually. When the new or old color is white, then precomputed steps computed from HSI space are used. Other transisions involving either just red/green use linear steps computed dynamially based on the total change. This CL also creates a new task for the LED code so that the color transitions won't hold off other hook tasks for too long a period of time. Changed the LED tick time to be 500 msec as it's no longer tied to the hook tick. BUG=b:35584895 BRANCH=eve TEST=Using EC console command 'battfake', changed reported battery charge level and verified that the LED patterns still work as expected. In addition, had debug code which printed to the console what the R, G, B duty cycle levels were for each transition and verified the expected values were achieved. Visually compared version with transitions to the previous version which changed abruptly. Change-Id: I4e7c19556db9ed6037f2afa05cf348d19aeb18bb Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/562543 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* util: ecst: Add support for chip variant npcx7m6gCHLin2017-07-151-6/+9
| | | | | | | | | | | | | | | | | This CL adds support for chip variant npcx7m6g in ecst utility. BRANCH=none BUG=none TEST=No build errors for make buildall. Build npcx7_evb board and upload firmware on EVB. No symptom found. Change-Id: I156e0a8f183397ad713c7134b3a0ad5fe78b0d83 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/567942 Commit-Ready: Jun Lin <riverq@gmail.com> Tested-by: Jun Lin <riverq@gmail.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* docs/usb_updater: Add more details about the update protocolNicolas Boichat2017-07-151-11/+90
| | | | | | | | | | | | | | | | | In particular, highlight more clearly cr50/common code differences, describe update over USB state machine, and common code commands. Also, replace all cr50/CR50 instances with Cr50. BRANCH=none BUG=b:36375666 TEST=~/chromium/src/tools/md_browser/md_browser.py -d docs Change-Id: I45e26a87c3455e1c67be186b403b1d4c4acade91 Reviewed-on: https://chromium-review.googlesource.com/558537 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* genvif: Prevent undefined referencer when using APIs not provided by genvifSam Hurst2017-07-141-1/+2
| | | | | | | | | | | | | | | | | | | | | Problem was detected while using ccprintf to debug a data role swap requests issue. To prevent errors similar to this, surround the API call as follows: ifndef VIF_BUILD ccprints("I won't generate an undefined reference when building genvif"); endif BUG=b:63664511 BRANCH=None TEST=`make -j buildall` Change-Id: Ieab9eaa638320cae67995a67c843d08b54acfbcb Signed-off-by: Sam Hurst <shurst@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/570820 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fizz: Boot automatically on recovery requestDaisuke Nojiri2017-07-141-0/+1
| | | | | | | | | | | | | | | | | | | | This patch clears RESET_FLAG_AP_OFF on recovery boot so that the system boots immediately regardless of the previous power state. BUG=b:63669512 BRANCH=none TEST=Verify the followings on reworked Fizz: 1. Press RB and PB in S0: FAIL(*1)/PASS 2. Press RB and PB in S5: FAIL(*1)/PASS 3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS 4. Unplug AC in S5 then press RB and plug in AC: PASS/PASS (*1: b:63668669) Change-Id: If300fc9ec28ff0f7833e84a02e174e501b6a5016 Reviewed-on: https://chromium-review.googlesource.com/570948 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* vboot: Jump to RW earlyDaisuke Nojiri2017-07-145-43/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes EC run vboot in the HOOK task. The vboot routine requires battery and charger info. It waits in a deferred call loop until the charge manager is initialized. BUG=b:63586051 BRANCH=none TEST=Verify the following cases: A. Hardware reboot (type-c/BJ) 1. Unplug AC in S0 then plug in AC: BOOT/BOOT 2. Unplug AC in S5 then plug in AC: S5/S5 3. Unplug AC after A.2 then plug in AC: S5/S5 4. Press PB in S5: BOOT/BOOT B. Software reboot (type-c/BJ) 1. Run EC reboot command in S0: BOOT/BOOT 2. Run EC reboot command in S5: BOOT/BOOT 3. Run EC reboot ap-off command in S0: S5/S5 4. Run EC reboot ap-off command in S5: S5/S5 5. Run host reboot command: BOOT/BOOT 6. Run host shutdown command: S5/S5 C. Recovery tests 1. Press RB and PB in S0: FAIL(*1)/PASS 2. Press RB and PB in S5: FAIL(*1)/PASS(*2) 3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS 4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2) *1: b:63668669 *2: b:63669512. Requires one more PB press. Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/568699 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* poppy/soraka: Enable host command for display backlightJagadish Krishnamoorthy2017-07-131-0/+1
| | | | | | | | | | | | BUG=b:63680313 BRANCH=none TEST=ectool backlight 0/1 should disable/enable display panel backlight. Change-Id: Idcbacb3b2a3145db7bfa44917842383569869944 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/570669 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* docs: Add USB updater documentation to docs folderNicolas Boichat2017-07-131-0/+120
| | | | | | | | | | | | | | | | Mostly copied from extra/usb_updater/usb_updater.c, makes it easier to reference from multiple locations (usb_updater, header files, etc.). BRANCH=none BUG=b:36375666 TEST=~/chromium/src/tools/md_browser/md_browser.py -d docs Change-Id: I6939ef74dd18b28ce5b8211c9a84f4adcf4e56b0 Reviewed-on: https://chromium-review.googlesource.com/486479 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kahlee: Modify pd control behaviorCloud2017-07-134-35/+60
| | | | | | | | | | | | | | | | | | | | 1. Fix a issue that user can't use type-c adapter and type-c device at the same time. ex. Plug in adapter in port1 and then plug in device in port2. Port1 will stop charge. 2. Update the vbus status when AC change to correct the charge source. 3. We use the typc adapter with capacity 5V/3A, 9V/3A, 15V/3A, 20V/2.25A. Add PD_PREFER_HIGH_VOLTAGE define to request voltage to 20V. BRANCH=None BUG=None TEST=Plug in type-c adapter and device to test Signed-off-by: Cloud Lin <cloud_lin@compal.com> Change-Id: I1927008a13651b8fa137d8d1a5000efd7db2e79f Reviewed-on: https://chromium-review.googlesource.com/485380 Commit-Ready: Lin Cloud <cloud_lin@compal.com> Tested-by: Lin Cloud <cloud_lin@compal.com> Reviewed-by: Martin Roth <martinroth@chromium.org>
* vboot: Move common code under common/vbootDaisuke Nojiri2017-07-1311-97/+347
| | | | | | | | | | | | | | | This patch moves the code which can be shared with other data verification schemes (e.g. RWSIG) under common/vboot. It also adds unit tests for it. BUG=b:38462249 BRANCH=none TEST=make run-vboot. Verify verification succeeds on Fizz. Change-Id: Icab4d96dd2c154a12b01c41ebe9b46286b4b590e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/563463 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* vboot: Verify and jump to RW_A or RW_BDaisuke Nojiri2017-07-133-15/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gives EC the capability of verifying and jumping to RW_A or RW_B. EC tries the slot stored in a persistent storage (e.g. BBRAM). If verification fails due to invalid contents, EC tries the other slot. AP's expectation and its reaction to the state of the slots and the currently running image are summarized below. Since the system is still unlocked (CONFIG_SYSTEM_UNLOCKED), EC won't try to verify or jump to RW yet. | AP expects X ----------+--------------------------- SLOT_A=X | proceed SLOT_B=X | proceed ----------+--------------------------- SLOT_A=X' | reboot to B SLOT_B=X | proceed ----------+--------------------------- SLOT_A=X | proceed SLOT_B=X' | reboot to A ----------+--------------------------- SLOT_A=X' | write X to B, reboot to B SLOT_B=X' | write X to A, reboot to A BUG=b:38462249 BRANCH=none TEST=Lock the system and boot Fizz on barrel-jack and type-c. Change-Id: I51e3abd4d9af44ab3d531561cb9bfa2e8d775f6a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/556286 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Build RW_B and support sysjump to itDaisuke Nojiri2017-07-136-19/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows a board to include another RW image in ec.bin. The size of each copy is a quarter of the flash size on Fizz. BUG=b:38462249 BRANCH=none CQ-DEPEND=CL:568297 TEST=Run sysjump RW/A/B. Verify there is no size change by running make savesizes/newsizes. Run objdump -h build/fizz/ec.obj: Idx Name Size VMA LMA File off Algn 0 .image.RO 0001700c 10088000 10088000 00008000 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .image.RO.key 00000340 1009f00c 100a7c40 0001f00c 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 2 .image.RW 00016ddc 1009f34c 100c8000 0001f34c 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 3 .image.RW.sign 000001b8 100b6128 100e7c00 00036128 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .image.RW_B 00016ddc 100b62e0 100e8000 000362e0 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 5 .image.RW_B.sign 000001b8 100cd0bc 10107c00 0004d0bc 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .padding 00000001 100cd274 10107fff 0004d274 2**0 CONTENTS, ALLOC, LOAD, DATA 7 .ARM.attributes 00000014 00000000 00000000 0004d275 2**0 CONTENTS, READONLY Change-Id: Iaa687c1d7d704fec4cccfa127376c8db102267fa Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/557305 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* servo_micro: add parity settingNick Sanders2017-07-136-6/+188
| | | | | | | | | | | | | | Add a control interface to set parity for USB-UART bridge. BRANCH=None BUG=b:37513705 TEST=parity settable on command line or by servod Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: Ib859a70981162be58edfa79c7cb267e0084e05e6 Reviewed-on: https://chromium-review.googlesource.com/564150 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* driver: sensor: tune MAX_FREQGwendal Grignou2017-07-132-3/+3
| | | | | | | | | | | | | | | | | | | | Reduce maximum frequency of BMM150 compass to 80Hz, 800Hz is a typo. Reduce SI1141 maximum frequency to 50Hz: 100Hz is too high when polling mode is used. Fix up of CL:482703 BRANCH=eve, glados BUG=chromium:615059 TEST=On eve, check CTS test android.hardware.cts.SensorBatchingTests#testMagneticField_fastest_flush passes. Observed that dumpsys sensorservice returns compass maxRate at 80Hz instead of 200Hz. Change-Id: If4e688ab59aa53c402d34714b6bb33ccd4a4ab96 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/570482 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* eve: Update static battery parameters for Simplo/LG packsScott Collyer2017-07-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | The Simplo_a50 battery had voltage_max = 8750 mV, which is not correct and it should be 8800. Since the voltage_max parameter is used with -0.5% margin, the 8750 mV value resulted in a charger setting of 8704 and does not provide enough of a voltage delta between the charger and the battery to fully charge packs that exceed the design capacity. In addition, had the tables for both battery types reviewed by the HW team and updated some of the temperature parameters. BUG=b:62483321 BRANCH=eve TEST=Tested with a dogood unit that was failing to reach 100% charge and showing very long "time to full" values as the battery charge approached 90%. After adjusting the voltage_max param, tested and verified that the battery reached 100% charge. In addition, verified the bd9995x 0x1A register had the correct voltage setting. Change-Id: I40e7bc111b048986e824fcb7843e57433a1def84 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/570380 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* motion_lid: Increase precision in noisy mag check.Aseda Aboagye2017-07-131-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit increases the precision used in the noisy magnitude deviation check by multiplying the scaled sensor data by 8 in the intermediate calculations. Prior to this, due to some bits being lost, certain devices would determine the lid angle as unreliable in specific angles, even though the device was at rest. BUG=b:63148973 BRANCH=eve,gru,reef TEST=Flash bob, set DUT on desk, run `while true; do ectool motionsense lid_angle; sleep 0.1; done`, slowly move the lid from 15 degrees until ~350. Verify that no particular angle results in a unreliable lid angle reading. TEST=Run `evtest` and examing cros-ec-buttons, fold screen all the way back to make tablet mode, shake device for at least 30s. Verify that there are no spurious transitions of the tablet mode switch. TEST=Repeat above tests on kevin. Change-Id: Iff06c1df2dd33c60e26a59183f62f29b71548729 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/567050 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* util/flash_ec: Support gang programmer mode for spi flash in npcx ecMulin Chao2017-07-131-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds support for updating FW to the internal spi flash in npcx ec by enabling gang programmer mode. We also added a new array, BOARDS_NPCX_INT_SPI, to indicate which boards will update FW through this mechanism. The preliminary of testing is listed below. Step 1: Connect npcx7 evb and servo v2 with following pins. NPCX796F Servo V2 ----------------------------------------- GP_SEL# --> (Pin 7, J7) FW_UP# VCC1_RST#--> (Pin 4, J7) DUT_COLD_RESET# GP_CS# --> (Pin 1, J11) DUT_SPI1_CS GP_SCLK --> (Pin 2, J11) DUT_SPI1_CLK GP_MISO --> (Pin 5, J11) DUT_SPI1_DO GP_MOSI --> (Pin 6, J11) DUT_SPI1_DI ----------------------------------------- Step 2: Npcx ec is powered up by PPDUT_SPI1_VREF (Pin 8, J11). Step 3: Add external PU on FW_UP#. Step 4: Execute "sudo servod --vendor 0x18d1 --product 0x5002". BRANCH=none BUG=none TEST=Move npcx7_evb from BOARDS_NPCX_7M6X_JTAG to BOARDS_NPCX_INT_SPI. Prepare two different ec images. Use following script "while :; do ./util/flash_ec --board=npcx7_evb --image=../ec1.bin; sleep 1; ./util/flash_ec --board=npcx7_evb --image=../ec2.bin; sleep 1; done" to test gang programmer mode. No errors occur over 2 hours. Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Change-Id: Ie813bf0191c06bb6e30a5e0dccb824f9f79ada53 Reviewed-on: https://chromium-review.googlesource.com/564742 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* poppy/soraka: Remove PECI support from ECRajneesh Bhardwaj2017-07-131-0/+1
| | | | | | | | | | | | | | | | | | | On Poppy and Soraka designs PECI_DATA is not physically wired to CPU PECI interface effectively rendering PECI feature dead. This patch disables PECI module to be built for Poppy & Soraka. BUG=b:63618104 BRANCH=None TEST=Build and boot on Poppy/Soraka, PECI module should not be built. Change-Id: Ibbf045f913a412cb68a1958527802c1e339ce860 Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://chromium-review.googlesource.com/567796 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* charger/rt946x: add Richtek rt946x charger driverPhilip Chen2017-07-134-0/+959
| | | | | | | | | | | | | | | | | BUG=chromium:736821 BRANCH=none TEST= 1) add RT9467 config to Scarlet and build the code 2) hook up rt9467 eval board with dummy load 3) verify the i2c traffic: set voltage, set current, and get device id Change-Id: Ie0dc2650711465b89eb4a5fbf69a326d6277b583 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/565055 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power/rk3399: Add a new power sequencingPhilip Chen2017-07-131-6/+51
| | | | | | | | | | | | | | | | | | This change is for Scarlet rev1. BUG=b:62640322 BRANCH=none TEST= 1) build Scarlet with 'CHIPSET_POWER_SEQ_VERSION == 2' successfully 2) build Kevin (CHIPSET_POWER_SEQ_VERSION == 0), and verify Kevin still boots Change-Id: I084a7b51fb1fdd8b6d50aa06189f34054162fc9a Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/568224 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Define load addresses using macrosDaisuke Nojiri2017-07-121-21/+25
| | | | | | | | | | | | | | | This patch defines load addresses of regions using macros to increase readability. BUG=none BRANCH=none TEST=Diff firmware_image.lds before and after the change. Change-Id: I24a13f4676b194efb748522f03c3134d1568f5ae Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/566940 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* usb_updater: fix transposed symbolic board ID representationVadim Bendebury2017-07-111-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | When usb_udpater reads board ID information from a binary blob, in case the ID field can be represented as a 4 character ASCII string the updater transposes the characters, resulting in a reversed string printed. Fix the transposition to verify that the result is printed properly. BRANCH=none BUG=b:63597142 TEST=ran the following commands: $ make BOARD=cr50 $ CR50_BOARD_ID='TEST:ff00:ff00' H1_DEVIDS='0x0169c181 0x04656742' \ ./util/signer/bs $ ./extra/usb_updater/usb_updater -b build/cr50/ec.bin read 524288(0x80000) bytes from build/cr50/ec.bin RO_A:4919.0.0 RW_A:0.0.21[TEST:0000ff00:0000ff00] RO_B:-1.-1.-1 ... Change-Id: I852cf9505d6b8b9e7133ca1008be1b22081a9d88 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/567681 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Always read LONG_LIFE_SCRATCH1 for brdprop.Aseda Aboagye2017-07-111-2/+7
| | | | | | | | | | | | | | | | | | | | | | The `brdprop` command simply returned board_properties, however, board_properties is just a cache of the properties from init time. When the `brdprop` command was issued, it would only return the cached value. This commit changes the functionality of the `brdprop` command to always query the LONG_LIFE_SCRATCH1 register. BUG=b:63456150 BRANCH=cr50 TEST=Flash bob. Unplug and plug in battery, verify that BOARD_WP_ASSERTED is set when running the `brdprop` command. Change-Id: I0a7feb5e63f3e528b554ed0820924ac0705f5517 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/566240 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* eve: Minor changes to LED patternsScott Collyer2017-07-111-8/+10
| | | | | | | | | | | | | | | | | | | | | The LED pattern for lowest battery level is supposed to indicate that there isn't enough battery present to boot the AP. The pattern_tbl array had this value set to 2. However, it's better to tie this to the constant defined in board.h so that it's consistent with when the AP will be allowed to boot. In addition, adjusted the battery level ranges to work correctly with the <= check. BUG=b:35584895 BRANCH=eve TEST=Used 'battfake' console command to verify that the patterns changed at the expected battery charge levels. Change-Id: Ie85a448ad4803be7e612c382b8e60fa42356d257 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/562542 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* board: Add initial support for zoombini.Aseda Aboagye2017-07-118-11/+966
| | | | | | | | | | | | | | | This commit adds the initial board support for zoombini. BUG=b:63508740 BRANCH=None TEST=`make -j buildall` Change-Id: I38a108d607ed1a33a0e5b588d4d463026919ac20 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/564800 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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