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* extra/stack_analyzer: Support to remove invalid paths.stabilize-9901.77.Bstabilize-9901.54.Bstabilize-9901.53.Bstabilize-9901.35.Brelease-R62-9901.BChe-yu Wu2017-09-013-201/+468
| | | | | | | | | | | | | | | | | | | | | | | | | Invalid paths (with arbitrary length) can be annotated and removed. Report set of possible function cycles. Sort the callsite outputs by filename and line number. BUG=chromium:648840 BRANCH=none TEST=extra/stack_analyzer/stack_analyzer_unittest.py make BOARD=elm && extra/stack_analyzer/stack_analyzer.py \ --objdump=arm-none-eabi-objdump \ --addr2line=arm-none-eabi-addr2line \ --export_taskinfo=./build/elm/util/export_taskinfo.so \ --section=RW \ --annotation=./extra/stack_analyzer/example_annotation.yaml \ ./build/elm/RW/ec.RW.elf make BOARD=elm SECTION=RW \ ANNOTATION=./extra/stack_analyzer/example_annotation.yaml \ analyzestack Change-Id: I9d443df6439b55d5b92a7624bdd93cb6e18494e2 Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/640393 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* scarlet: Limit the maximal acceptable VBUS to 13VPhilip Chen2017-08-312-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | When my 15V/30W charger is plugged in scarlet, I see rt946x (the battery charger on Scarlet) asserts OVP because VBUS(15V) > VBUS_OVP(14V) defined in rt946x datasheet. So we should limit the maximal VBUS to ~13V even if the source can provide higher voltage. Meanwhile, let's replace some numbers with macros for better maintainability. BUG=b:65118519 BRANCH=none TEST=manually verify charging works with a 15V/30W PD charger Change-Id: I19b7d8297bdbab0a722c488910fd872eb1395e16 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/639927 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_updater2: Add code to fetch touchpad informationNicolas Boichat2017-08-311-9/+35
| | | | | | | | | | | BRANCH=none BUG=b:63418037 TEST=./usb_updater2 -t Change-Id: Ibed7cfc1d706f0f0ff8072f3ec08997f40a89038 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/593001 Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
* ISH: added sleep mask for UART portKyoung Kim2017-08-311-0/+6
| | | | | | | | | | | | | | | added UART sleep mask not to allow to enter into deep sleep. BUG=None BRANCH=master Test='make -j buildall' Change-Id: I15e55c2c94276da99339465f2ea577b1f94e1ce4 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/644848 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Hammer : Add multi-ic support in touchpad_updaterKT Liao2017-08-311-11/+44
| | | | | | | | | | | | | | | | | | | | Elan has shipped other AVL IC in Chromebook recently. And it will support hammer project "charger" Original code use constant definition for FW page count. Unfortunatlly new IC's page count is different. I add a code to judge IC first, and then get the correct page count before FW updating Signed-off-by: KT Liao <kt.liao@emc.com.tw> BRANCH=none BUG=None TEST=Execute fw updating in hammer system Change-Id: Ibdd9f7c0b61118950d8e751b7bbaaefeaaa3fb27 Reviewed-on: https://chromium-review.googlesource.com/620451 Commit-Ready: Chun-ta Lin <itspeter@chromium.org> Tested-by: KT Liao <kt.liao@emc.com.tw> Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
* ISH: correction for HPET1 interrupt routingKyoung Kim2017-08-303-7/+10
| | | | | | | | | | | | | | | | | | | -Routing HPET1 timer requires HPET's General Config register's Legacy routing bit should be set. -For HPET0 interrupt, no need to set IRQ# to T0C register. -change IRQ# back to default values. BUG=None BRANCH=master TEST=`Build ISH and verify the timer interrupt via various console cmds` Change-Id: I9f83d62a1f7d999ebf6cedafd38691531ec91081 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/627628 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* scarlet: Initialize non-PD/USB-C charge suppliersPhilip Chen2017-08-301-0/+31
| | | | | | | | | | | | | | | | | | | Before all of the charge suppliers are initialized, charge_manager_refresh() wouldn't be called to update charging voltage/current. Since we don't define CONFIG_USB_CHARGER, we need to do the initialization in board specific files. BUG=b:65118519 BRANCH=none TEST=manually verify charging voltage/current are updated Change-Id: Ib0c226c236b8add0dcba7bf3610da47c26166732 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/639926 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: Split AP state machine into its own fileRandall Spangler2017-08-306-150/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device state machines aren't quite similar enough to use common code. Split the AP state machine out, the way we split out the EC state machine in the previous CL. BUG=b:35587387 BRANCH=cr50 TEST=manual, with Cr50 strapped (or hard-coded) not to use platform reset and not to use TPM reset to detect the AP: Pull CCD_MODE_L low, so Cr50 detects/enables CCD Pull AP_DETECT high. Pull INT_AP_L low (with resistor). Pull AP_DETECT low --> See 'AP off' message gpioget --> INT_AP_L=0 ccd --> AP UART disabled Pull AP_DETECT high --> See 'AP on' message gpioget --> INT_AP_L=1 ccd --> AP UART RX+TX Pull AP_DETECT low for <1 sec then back high (don't see AP off/on message) gpioget --> INT_AP_L=1 ccd --> AP UART RX+TX Reboot with AP_DETECT still low -> AP off at 1 second Reboot with AP_DETECT still low and then assert AP_DETECT within a second -> AP on immediately Repeat with Cr50 strapped/hard coded to use platform reset, but using TPM_RST_L instead of AP_DETECT. Note that this will also show TPM reset debugging output when TPM_RST_L is asserted. Change-Id: Ief9e4e5f2585ff925de1595cc8fbd5306c94a806 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/634248 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Only enable UART RX when EC/AP is onRandall Spangler2017-08-302-29/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, some code paths such as CCD permissions change could result in enabling EC or AP UART RX when the EC or AP is off. This could result in interrupt storms. BUG=none BRANCH=cr50 TEST=manual // Initial conditions Assert CCD_MODE_L Deassert DETECT_SERVO // Both RX and TX disabled when processor turns off // and re-enabled when it turns back on Deassert DETECT_EC ccd -> EC UART disabled Assert DETECT_EC ccd --> EC UART RX+TX Deassert DETECT_AP ccd -> AP UART disabled Assert DETECT_AP ccd --> AP UART RX+TX // TX disabled when CCD disabled Deassert CCD_MODE_L ccd --> EC UART RX, AP UART RX Assert DETECT_SERVO ccd --> EC UART RX, AP UART RX // Don't enable TX when detecting EC, if servo is connected Deassert DETECT_EC ccd -> EC UART disabled Assert DETECT_EC ccd --> EC UART RX // Don't enable TX when detecting CCD, if servo is connected Assert CCD_MODE_L ccd --> EC UART RX, AP UART RX // When servo disconnects, enable TX if CCD is connected Deassert DETECT_SERVO ccd --> EC UART RX+TX, AP UART RX+TX Change-Id: Icb144c23e949afb0384c242965aa729b078b03eb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/642349 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* sensors: Support device with only one accelerometerGwendal Grignou2017-08-301-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | LPC area for sensors support 3 sensors: up to 2 accelerometers and 1 gyro. If only 1 accelerometer is present, only the first accelerometer slot is populated. If there is no gyro, the gyro slot is not populated. Add tests and remove assumption in the code to be sure the rules above are enforced. BRANCH=none BUG=b:64232053 TEST=compile, check eve is still working. On soraka: ectool motionsense odr 2 10000 ectool motionsense output matches: grep . /sys/bus/iio/devices/*/in_*_raw Change-Id: Ifd791a6fa89d94bf91ad1a65b8987f69bada801e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639319 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ec_features / coral: Allow disabling keyboard backlight featurePatrick Georgi2017-08-305-2/+49
| | | | | | | | | | | | | | | | | Allow reporting that keyboard backlight doesn't exist even when the code is compiled in. Useful if there are multiple device models that should share firmware. BUG=b:64705535 BRANCH=none TEST=none Change-Id: I9c1fc370aedf66ef856a571f73831095d27e3d39 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/633926 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* acpi: Map EC features into ACPI EC memory spacePatrick Georgi2017-08-303-1/+48
| | | | | | | | | | | | | | | | | Reserve EC address space offset 0x0a-0x0d for device features. Same value as with the host command, just different way to access it. BUG=b:64705535 BRANCH=none TEST=none Change-Id: I420aed1ae8d0fb7da477fc72ac55ea75a9f9350b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/626976 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* ec_features: Move feature flags out of ec_command into its own unitPatrick Georgi2017-08-304-97/+121
| | | | | | | | | | | | | | | | | | Prepare for exposing the feature flags through EC ACPI memory space by moving the definitions and collection function into its own unit. BUG=b:64705535 BRANCH=none TEST=builds and returns the same value Change-Id: I66eabebe0d039fdcd14d11b9ecf77c0f1040d006 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/633925 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* presubmit_check: Check unittests results on extra/stack_analyzerNicolas Boichat2017-08-292-14/+34
| | | | | | | | | | | | BRANCH=none BUG=none TEST=util/presubmit_check.sh Change-Id: I6078377603719de1d633660c69ad3a40b29ffadf Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/640191 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Che-yu Wu <cheyuw@google.com>
* anx3429: force chip reset on PD_RESUMECaveh Jalali2017-08-297-58/+108
| | | | | | | | | | | | | | | | | | | | | | we need to properly restart the anx3429 after a firmware update. simply initializing the chip doesn't seem to get it to reload its firmware - at least not the portion of the chip that implements the firmware version register. so, we explicitly power down and reset the chip before reinitializing it to force it to run the new firmware. the chip also needs a 10ms "off" time so the reset is properly seen by the chip, so i did a light refactoring of the code paths that reset the anx3429. TEST=used 2 different firmware blobs and verified it switches between them during software sync. BRANCH=none BUG=b:35586895 Change-Id: I967898dd906f21bdc5bc4ce9c1dff9f873d198c1 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/631976
* cr50: Add vendor cmd to query rec btn state.Aseda Aboagye2017-08-293-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to test certain devices in the test lab using cased closed debugging (CCD), we need a mechanism to programmatically "press" the recovery button. Even though this signal is being buffered through the EC to the AP, and the EC could theoretically set it if needed, we cannot trust the EC in its RO image since it may speak to the outside world over USB PD. Instead, this commit introduces a console command on cr50 that can be used to force the recovery button state to be pressed. However, it is gated behind the CCD capabilities defaulting to the IfOpened state. Additionally, a new vendor command is added to query the trusted state of the recovery button. The AP should use this command instead of trusting the GPIO connected to it. BUG=b:37751915, b:64146626 BRANCH=cr50 TEST=Flash cr50. Press KEY0, verify that reported rec btn follows the state of the button. TEST=`recbtnforce enable` causes the button to be reported as pressed. Physical presses of the button do not alter the reported state. TEST=`recbtnforce disable` causes the reported state to follow that of the physical button. TEST=The `recbtnforce` command is set to the IfOpened capability by default. TEST=CCD locking the DUT and attempting to force the recovery button results in an error of access denied. The physical state is reported. TEST=From the AP, issue the vendor command to retrieve the button state and verify that it behaves as expected. Change-Id: Ib8c2928e75e5f9a1a83c5361664efc3fa0ae2ddb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/635955 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Let state machines print their own statesRandall Spangler2017-08-296-18/+78
| | | | | | | | | | | | | | | | | | | Add a function to translate device_state enum into a string, then use it for printing the ec and RDD state. Refactor ec_state so that all state transitions go through a set_state() function, which makes it easier to turn on debugging all state transitions. That's normally not compiled in because it would be spammy during debouncing. BUG=none BRANCH=cr50 TEST=ccd command prints EC and RDD states Change-Id: Ie7bc56c7b66beee23d1d1989711c640e5e39ce43 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/642121 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Configure AP detect GPIO based on correct configRandall Spangler2017-08-291-16/+21
| | | | | | | | | | | | | | | | | | | Now that there are separate board config functions, use !board_detect_ap_with_tpm_rst() to decide whether to configure DETECT_AP on DIOA3, not board_use_plt_rst(). BUG=none BRANCH=cr50 TEST=Boot cr50 strapped to use platform reset. See that 'gpioget' shows DETECT_AP does not respond to changes on the DIOA3 pin. Boot cr50 strapped not to use platform reset. See that 'gpioget' shows DETECT_AP responds to changes on DIOA3. Change-Id: Ieb05015c948b2bbafa744f00a11e6b3da143ca5b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/642120 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-297-11/+13
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* EFS: Add error codesDaisuke Nojiri2017-08-295-32/+57
| | | | | | | | | | | | | | | This patch defines more error codes to make the consle more descriptive. BUG=none BRANCH=none TEST=Boot Fizz. Change-Id: I84cc6cd7f309bb2f2e1f36dea6cf5a7f0f862f50 Reviewed-on: https://chromium-review.googlesource.com/639160 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* scarlet: Enable software-controlled input current limitPhilip Chen2017-08-291-0/+1
| | | | | | | | | | | | | | | | | | By default the input current on Scarlet is limited to 500mA, which is defined by ILIM pin. We need to disable the control from ILIM pin to draw more current from the source. BUG=b:64821815 BRANCH=none TEST=manually monitor the charging current Change-Id: Ia356a2397b3671c178479a581b44a17215fee83d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/639918 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charger/rt946x: Fix the function namePhilip Chen2017-08-291-1/+1
| | | | | | | | | | | | | | BUG=b:63739819 BRANCH=none TEST=build scarlet when 'CONFIG_CHARGER_ILIM_PIN_DISABLED' is turned on Change-Id: I692346031867160774344e67e0a7e936278820a1 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/639917 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* extra/stack_analyzer: Eliminate annotated indirect calls.Che-yu Wu2017-08-294-106/+289
| | | | | | | | | | | | | | | | | | | | | | | | Indirect calls can be eliminated by adding corresponding annotations. BUG=chromium:648840 BRANCH=none TEST=extra/stack_analyzer/stack_analyzer_unittest.py make BOARD=elm && extra/stack_analyzer/stack_analyzer.py \ --objdump=arm-none-eabi-objdump \ --addr2line=arm-none-eabi-addr2line \ --export_taskinfo=./build/elm/util/export_taskinfo.so \ --section=RW \ --annotation=./extra/stack_analyzer/example_annotation.yaml \ ./build/elm/RW/ec.RW.elf make BOARD=elm SECTION=RW \ ANNOTATION=./extra/stack_analyzer/example_annotation.yaml \ analyzestack Change-Id: I18c317f9c6478b5b431ee04d882453791df27891 Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/631082 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* sweetberry: converter tool for servo_inaNick Sanders2017-08-282-0/+86
| | | | | | | | | | | | | convert_servo_ina.py can convert power log config files from hdctools/servo/data into sweetberry configs BRANCH=None BUG=b:35578707 TEST=compare kevin_r0_loc.py output with kevin.board Change-Id: Iadc57fe4eb1f5b220c6bffe3a3fe8a10b0d6b5a2 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/634486
* tcpm: fusb302: Round VNC and Rd thresholds to nearest stepShawn Nematbakhsh2017-08-281-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | fusb302 determines attach / no-attach (and Rd / Ra) by comparing CC voltage against an MDAC output (42 mV steps). The previous 'floor' calculation was particularly bad for 3.0A Rp (2600 / 42 = 61, 61 * 42 = 2562 mV - 21 = 2551 mV actual threshold, ignoring other error sources). Reduce the chance of error by rounding our thresholds, which also matches the suggested thresholds in the datasheet. BUG=chromium:758608 BRANCH=gru TEST=Attach problematic dingdong, verify we don't enter an attach / detach loop. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9211782da0fdad8339246e272952ba1930b69851 Reviewed-on: https://chromium-review.googlesource.com/633276 Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 311b3e4e15fd37ea2ab151edb8b8a468e93355fd) Reviewed-on: https://chromium-review.googlesource.com/638694 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: Add USB-A charge control support.Aseda Aboagye2017-08-283-1/+14
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=make -j buildall Change-Id: I8ee0ec01d06343a158f4271e1f9ecdb3d8895659 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/634275 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_port_power_smart: Add CDP/SDP only option.Aseda Aboagye2017-08-288-21/+41
| | | | | | | | | | | | | | | | | | | | | | | | | For some boards, the control lines to the charging port controller are all tied to a power rail. In essence, this leaves the ILIM_SEL as the only signal able to be controlled, which means that we only support CDP/SDP. This commit adds a new CONFIG_* option which describes this. CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY Additionally, some cleanup is made to not always assume the number of smart power ports. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I080ccd67ffc20ccccf1e6b33a3cf9374a6b70ad6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/634274 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cortex-m0: Use assembly exception handlers for task switchingPaul Kocialkowski2017-08-282-26/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way Cortex processors handle exceptions allows writing exception routines directly in C, as return from exception is handled by providing a special value for the link register. However, it is not safe to do this when doing context switching. In particular, C handlers may push some general-purpose registers that are used by the handler and pop them later, even when context switch has happened in the meantime. While the processor will restore {r0-r3} from the stack when returning from an exception, the C handler code may push, use and pop another register, such as r4. It turns out that GCC 4.8 would generally only use r3 in svc_handler and pendsv_handler, but newer versions tend to use r4, thus clobbering r4 that was restored from the context switch and leading up to a fault when r4 is used by the task code. An occurrence of this behaviour takes place with GCC > 4.8 in __wait_evt, where "me" is stored in r4, which gets clobbered after an exception triggers pendsv_handler. The exception handler uses r4 internally, does a context switch and then restores the previous value of r4, which is not restored by the processor's internal, thus clobbering r4. This ends up with the following assertion failure: 'tskid < TASK_ID_COUNT' in timer_cancel() at common/timer.c:137 For this reason, it is safer to have assembly routines for exception handlers that do context switching. BUG=chromium:631514 BRANCH=None TEST=Build and run speedy EC with a recent GCC version Change-Id: Ib068bc12ce2204aee3e0f563efcb94f15aa87013 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://chromium-review.googlesource.com/362830 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charger: bd9995x: Disable topoff modeShawn Nematbakhsh2017-08-281-3/+1
| | | | | | | | | | | | | | | | Zero ITERM_SET to keep the charger out of topoff mode, since it has undesirable side-effects related to dead / low battery charging. BUG=b:35575421 BRANCH=reef TEST=Previous testing on kevin with same register setting. Change-Id: Ic1dd280e1069d410895498c0f72989654a6b8c63 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/636152 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tigertool: add power log and versionNick Sanders2017-08-251-1/+104
| | | | | | | | | | | | | | | | --power provides a single sample from the INA --powerlog [n] provides n samples --check_version returns the tigertail's firmware version --bus selects which bus to probe power on [vbus|cc1|cc2] BRANCH=None BUG=b:35849284 TEST=check power readings, version. Change-Id: I728d954b6649fe0401093bf3beb7ec89f27822a6 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/634566 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: Split EC state machine into its own fileRandall Spangler2017-08-256-52/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device state machines aren't quite similar enough to use common code. Split the EC state machine out, the way we split out BattPrsnt and CCD_MODE. BUG=b:35587387 BRANCH=cr50 TEST=manual Pull CCD_MODE_L high, so Cr50 detects/enables CCD Pull EC_DETECT high. reboot -> 'EC RX only', then 'EC on' at 1 second Pull EC_DETECT low --> See 'EC off' message ccd --> EC UART disabled Pull EC_DETECT high --> See 'EC on' message ccd --> EC UART RX+TX Pull EC_DETECT low for <1 sec then back high (don't see EC off/on messages) ccd --> EC UART RX+TX Reboot with EC_DETECT still low -> EC off at 1 second Reboot with EC_DETECT still low and then assert EC_DETECT within a second -> EC RX only, then EC connect at 1 second. Change-Id: I71687e651d625cadd656934f4cb2bbadc0b58816 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/619750 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* zoombini: fixed gpio.inc to make power enables push-pullRachel Nancollas2017-08-251-3/+5
| | | | | | | | | | | | | | | | Made EN_PP3300_TRACKPAD, EN_PP3300_WLAN, and EN_PP3300_WWAN push-pull and added USB1_ENABLE. BUG=None TEST=Check to make sure power enables are not floating. BRANCH=None Change-Id: I5e63b61a83e4c5504cead6d7b28d087fc5538c3b Signed-off-by: Rachel Nancollas <rachelsn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/630056 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* anx3429: read chip firmware version during initCaveh Jalali2017-08-251-0/+2
| | | | | | | | | | | | | | | | | | | | fetching the chip firmware version toward the end of the chip anx74xx_tcpm_init() sequence is a good place to do this. we need this info in any case and this is a safe place to access device registers and cache the values. subsequent chip firmware queries typically return the cached value. also, tcpci_tcpm_init() is already structured this way. TEST=verified with follow-up CL that firmware update succeeds and new version is reported BRANCH=none BUG=b:35586895 Change-Id: Ic3fd07bbf8a220bfd506d59d8a1f3ea25b14e94c Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/634513 Reviewed-by: Shawn N <shawnn@chromium.org>
* core/minute-ia: add __image_sizeli feng2017-08-242-0/+5
| | | | | | | | | | | | | | | | | For system using core/minute-ia, build will fail since __image_size is not defined. If later this variable is used, should adjust its value properly. BUG=none BRANCH=None TEST=Build passed for Soarka ISH which uses core/minute-ia. Change-Id: I8e179e0bac551a46d93ca10ba8b61b4ebade74fc Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/595151 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* anx74xx: enable driver "release".Caveh Jalali2017-08-241-1/+5
| | | | | | | | | | | | | | | | | | | TEST="make buildall" succeeds, "make runtests" passes for reef. returning SUCCESS instead of UNIMPLEMENTED from .release() means the pd_task() is allowed to reinitialize the TCPC when coming out of PD_STATE_SUSPENDED or similar scenario. TEST=verified anx3429 firmware update succeeds, USB port still usable for charging after update. BRANCH=none BUG=b:35586895 Change-Id: I1a624ccf25dfa6468de72f8564f936bc0a35edb1 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/596797 Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: add board property functionsMary Ruthven2017-08-242-3/+17
| | | | | | | | | | | | | | | | | | | | | Add some board property functions that describe what behavior we are checking instead of just using board_use_plt_rst. More devices are getting deep sleep support. This changes some function names to make the transition easier. This change adds board_use_deep_sleep and board_detect_ap_with_tpm_rst. Right now both of these just call board_use_plt_rst. This will eventually change with the expansion of deep sleep to new devices. BUG=none BRANCH=cr50 TEST=run firmware_Cr50DeepSleepStress with 10 suspend/resume cycles Change-Id: I8d9ef23f686dea788d26ac4973054ad027fdd3a4 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/633891 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: Change rdd 0.4V ref to 0.3V.Aseda Aboagye2017-08-241-0/+7
| | | | | | | | | | | | | | | | | | | On some boards, it was seen that SuzyQable wasn't detected by the rdd block. The voltage around 0.4V is marginal with a Vbus around 4.75V. This commit simply adjust the 0.4V comparator reference voltage to 0.3V in order to make the detection work. BUG=b:64847312 BRANCH=cr50 TEST=Find a soraka where SuzyQable didn't work. Verify with this patch, it does work. Additionally, verify that servo_v4 continues works. Change-Id: If54630ec469408031cd84ffb93ef5fea42bdee3b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/633403 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: Move chip pre-init to chip_pre_init()Randall Spangler2017-08-247-23/+57
| | | | | | | | | | | | | | | | | | | | Currently, chip/g uses jtag_pre_init() to do some chip pre-initialization that isn't actually related to JTAG. This has been harmless, but it's currently the only chip which actually does "JTAG" pre-init, and we'd like to get rid of that. So, move that functionality to a new optional chip_pre_init() function. BUG=chromium:747629 BRANCH=cr50 TEST=make buildall boot cr50 make all dis; confirm chip_pre_init() is called early in <main> Change-Id: I3cae0747ab0c3cc974fce9f108947207b38e035f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/629876 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* poppy: Enable base on sysjumpFurquan Shaikh2017-08-241-0/+7
| | | | | | | | | | | | | | | | | Now that we enable base only on chipset state transition, sysjump needs to be handled in a special way. On sysjump if chipset is already in S0, then enable base right away. BUG=b:64987346 BRANCH=None TEST=Verified that base is enabled and connected on sysjump. Tablet mode events work again in evtest. Change-Id: I917b0ca84d2735a4f2b32ecea3d310eccb7c008c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/631218 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* extra/stack_analyzer: Show indirect calls.Che-yu Wu2017-08-243-17/+62
| | | | | | | | | | | | | | | | | | | | | | | Show the indirect calls found in disassembly. BUG=chromium:648840 BRANCH=none TEST=extra/stack_analyzer/stack_analyzer_unittest.py make BOARD=elm && extra/stack_analyzer/stack_analyzer.py \ --objdump=arm-none-eabi-objdump \ --addr2line=arm-none-eabi-addr2line \ --export_taskinfo=./build/elm/util/export_taskinfo.so \ --section=RW \ --annotation=./extra/stack_analyzer/example_annotation.yaml \ ./build/elm/RW/ec.RW.elf make BOARD=elm SECTION=RW \ ANNOTATION=./extra/stack_analyzer/example_annotation.yaml \ analyzestack Change-Id: Ib82e68e0bc6c4be56ab679c297f256cbfe94bbb7 Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/628048 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Coral: Fix FAFT failure for firmware_ECUsbPortsRyan Zhang2017-08-231-2/+1
| | | | | | | | | | | | | | | | + Follow Change#386854 + Remove gpio41: gpio41 is used for ADC and already exist. BUG=b:64738358 BRANCH=master TEST=`make -j BOARD=coral`, `firmware_ECUsbPorts` passed on santa MB Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Change-Id: I1c08c68c5449a94a333aca3384a48244450155ab Reviewed-on: https://chromium-review.googlesource.com/613061 Commit-Ready: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* extra/stack_analyzer: Show callsite information.Che-yu Wu2017-08-233-50/+164
| | | | | | | | | | | | | | | | | | | | | | | | Show callsite details in the call trace. Handle another addr2line failure output. BUG=chromium:648840 BRANCH=none TEST=extra/stack_analyzer/stack_analyzer_unittest.py make BOARD=elm && extra/stack_analyzer/stack_analyzer.py \ --objdump=arm-none-eabi-objdump \ --addr2line=arm-none-eabi-addr2line \ --export_taskinfo=./build/elm/util/export_taskinfo.so \ --section=RW \ --annotation=./extra/stack_analyzer/example_annotation.yaml \ ./build/elm/RW/ec.RW.elf make BOARD=elm SECTION=RW \ ANNOTATION=./extra/stack_analyzer/example_annotation.yaml \ analyzestack Change-Id: I3f36584af85f578f1d298bcd06622ba8e7e5262d Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/628000 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: Don't enable CONFIG_CMD_FLASH_TRISTATE when internal flash is usedCHLin2017-08-231-0/+3
| | | | | | | | | | | | | | | | | | | The bit controlling the tri-state of FIU pins is reserved when the internal flash is used and should not be modified. This CL adds a compiler error to prevent this kind of misuse. BRANCH=none BUG=none TEST=No build errors for "make buildall". "BORAD=npcx7_evb make" with CONFIG_CMD_FLASH_TRISTATE defined, make sure the error message is printed. Change-Id: I020c8ab9e02b9a377879bbd2a337943e77a369d6 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/624828 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* coral: Enable TCPC init to happen in pd_task initScott Collyer2017-08-232-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL enables the config option CONFIG_USB_PD_TCPC_BOARD_INIT and modifies the board level tcpc init function to wait up to 2 seconds to ensure that the battery is out of its disconnected state. This change was put into Eve to ensure the PD chips are not reset until the battery is out of disconnect and delay start of the pd_task (and PD negotiation) until the battery is out of disconnect state. This is part of a change was initially done on Eve https://chromium-review.googlesource.com/c/592716. For Coral the delay of tcpc init relative to the PD task also addresses an issue where VBUS would be dropped by the external charger when attempting to boot with no battery connected. When no battery is connected there is a timing issue between the Analogix TCPC and the EC related to when the TCPC sends its auto GOODCRC. This results in a hard reset which causes the drop of VBUS. BUG=b:64375688 BRANCH=none TEST=Tested by Bitland using 500 iterations and showed no occurrence of the hard reset causing VBUS to drop. Prior to this CL, the failure rate was 1 out 300 attempts. Change-Id: I28fe3266eb1c0a2940e1bdacee65cf4e642d3483 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/627115 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* tcpc: Move board level TCPC init to happen in pd_task initScott Collyer2017-08-232-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the board level TCPC run as an init hook it will frequently lead to an EC reset when we are trying to recovery a disconnected battery, potentially even a reboot loop with the most unlucky timing. If we instead call it from the pd_task before tcpc_init is called then the board init hook can stall the pd_task init until the battery is out of disconnect mode, or giving up after 2 seconds in case the battery never seems to recover. This accomplishes two goals: ensure the PD chips are not reset until the battery is out of disconnect and delay start of the pd_task (and PD negotiation) until the battery is out of disconnect state. This change was done in the Eve FW branch. Pulling it into TOT so it can be used for other boards that have the same issue. https://chromium-review.googlesource.com/c/592716. The change to wait for the battery to be out of disconnect mode is in the board specific board_tcpc_init() function and so will be in subsequent board specific CLs. BUG=b:63957122 BRANCH=none TEST=manual Verify that 'make buildall' is successful. Change-Id: I14c3dbb89cdc05fa9231fbe9db2e1de19fa941b6 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/627114 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* battery: Check physical battery presence before inhibiting powerScott Collyer2017-08-239-8/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to satisfy factory testing requirements we need to boot a bare board with just an AC adapter without requiring a power button. However we also don't want to always allow booting of the battery is present but cut-off (which will indicate BP_NO so we can't use the existing battery_is_present function) or has critically low level as it may not immediately boot. To accomplish this add a function that allows the board to specify a custom "hardware presence" for the battery that is separate from the battery presence check. This CL is taking a change done for Eve and pulling into TOT so it can be used for other projects that have the same requirements. https://chromium-review.googlesource.com/c/582544 BUG=b:63957122 BRANCH=none TEST=manual Change-Id: Ib1dc4f659adbf0eebd3dc8c3c61b39b8fa36cb4a Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/627113 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* scarlet: Enable waking up AP by power buttonPhilip Chen2017-08-231-1/+1
| | | | | | | | | | | | | | | | | Meanwhile, we can disable waking up AP by key press, because there is no keyboard. BUG=none BRANCH=none TEST=when AP is in S3, verify 'powerbtn' command on ec console can wake up AP Change-Id: I60c58458cf6f7e1f16b5129c8748b386c9928415 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/627675 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_updater2: Add support for INJECT_ENTROPY commandNicolas Boichat2017-08-231-11/+45
| | | | | | | | | | | | | | | | | Necessary for pairing support. Cleaner implementation to be moved to hammerd. BRANCH=none BUG=b:38487027 TEST=Flash hammer. On host, reboot hammer to RO: usb_updater2 -r; sleep 0.5; usb_updater2 -s usb_updater2 -e (adds entropy) EC console: check that rollbackinfo shows secret is updated Change-Id: I7b354c7bb1b6d4260939dc33fe6cb4ab4ecd50e0 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/513809 Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
* pd_control: make DISABLE port specificCaveh Jalali2017-08-231-3/+3
| | | | | | | | | | | | | | | | | | | | this makes the PD_CONTROL_DISABLE subcommand of EC_CMD_PD_CONTROL port specific like all the other subcommands already are. the only place depthcharge uses PD_CONTROL_DISABLE is in anx7688.c and that code already passes the correct chip ID along, so this will not affect the current use case. ectool already does the right thing as well. TEST=used ectool to verify each port can be disabled independently. BRANCH=none BUG=b:64956885 Change-Id: I6514eb300793b8958ed78846298ec5b95f78e6dc Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/616259 Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: Don't enable GPIO interrupts by defaultRandall Spangler2017-08-231-29/+23
| | | | | | | | | | | | | | | | | | | | Each GPIO interrupt should only be enabled after its state machine is ready to accept interrupts. Enabling them all by default may cause undefined behavior if an interrupt occurs before state machine init. Also, EC_TX_CR50_RX was enabled, and then explicitly disabled in board_init() because we didn't want it. Simpler only to enable the interrupts we do. BUG=b:35587228 BRANCH=cr50 TEST=boot cr50; manually wiggle platform reset and the detect GPIOs and see that interrupts are still generated. Change-Id: If810eb6fee9945f0c6dfe0d4b592bdc5ff4be6e7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/619749 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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