summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* scarlet: Upgrade the charger IC to RT9467 on rev2stabilize-9998.BPhilip Chen2017-10-181-1/+1
| | | | | | | | | | | | | | | | WARNING: This will break charging on rev1 which uses RT9466 since RT9467 has different I2C address from RT9466. BUG=b:67917615 BRANCH=none TEST=manually verify charger works on rev2 Change-Id: I633ab783eece033cfe733401e09ee83359a5f265 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/725600 Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* scarlet: Use TCPC to detect VBUSPhilip Chen2017-10-181-1/+2
| | | | | | | | | | | | | | | | | | On Scarlet rev2, we see rt9467 has trouble detecting VBUS level reliably. Let's use TCPC to detect VBUS instead as we once considered in b:65698085. BUG=b:65698085 BRANCH=none TEST=verify usb mouse and charging works through usb-c hub Change-Id: I439cd3267bb26d5cdcbfd4a3c48179cf7942b870 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/725599 Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* chip/stm32/clock: Allow the host to reset rtc alarmPhilip Chen2017-10-022-1/+6
| | | | | | | | | | | | | | | | | | | | | When the host sets rtc alarm wake time = 0, it wants to reset and disable the alarm. Also, align the implementation in npcx with that in stm32 to check both delay_s and delay_us. BUG=b:66971951, b:63908519 BRANCH=none TEST='ectool rtcsetalarm 3'. After alarm goes off, run 'ectool rtcgetalarm' and then see 'Alarm not set'. Change-Id: I693f1c72cba492e837891c716f79e2aa4da59b2a Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/691256 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* cr50: enable rma_authVadim Bendebury2017-10-024-13/+40
| | | | | | | | | | | | | | | | | | Enable necessary flags for the Cr50 to start supporting RMA authentication. This also requires that the RMA server public key definition is split between the actual and test. Even though they are the same at this time, the actual public key would be defined in the new future and it would be different from the test key. BRANCH=cr50 BUG=b:65253310 TEST=make buildall -j passes. More tests were conducted on the full patchset. Change-Id: I5a3f9d8c71374d78192e3f0a2752391b842da962 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/691554 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: add TPM vendor command to support RMA authenticationVadim Bendebury2017-10-023-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | The new vendor command operates in two modes: when received with a zero size payload, it triggers the Cr50 to generate a new RMA authentication challenge and the expected authentication code value. When receive with the payload, it compares the received payload with the pre-calculate authentication code, and returns to the host the comparison result (passed/not passed). A care is taken not to accept payload until at least there is a valid calculated auth code present (to avoid reporting a match on a payload of all zeros). Test config needed to be modified to allow compiling of the ccprintf wrapper. BRANCH=cr50 BUG=b:37952913 TEST=with the rest of the patches applied observed expected behavior of generating challenge/response and verifying the auth code. Change-Id: I30638b0ceef68830565f222dd1f4af17cfc8d7ef Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/690992
* commom: generalize rma_auth to and make it match server expectationsVadim Bendebury2017-10-022-4/+37
| | | | | | | | | | | | | | | | | | | | | | | Different devices could have different sized unique device IDs. Let's just use the IDs as is if they are no larger than the rma_challenge:device_id field, or the first 8 bytes of the HMAC_sha256 value of the unique device ID, where the unique device ID is used both as the key and the payload. The server expects the board ID field in big endian format, let's swap it before calculating the RMA auth challenge. The test's server side implementation needs to be also adjusted. BRANCH=cr50 BUG=b:37952913 TEST=make buildall -j passes. With the rest of the patches applied RMA authentication process generates sensible values. Change-Id: Ia1fbf9161e01de30a2da8214258008f6e5f7d915 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/690991 Reviewed-by: Michael Tang <ntang@chromium.org>
* common: allow rma_auth to work with both crypto and dcryptoVadim Bendebury2017-10-021-2/+21
| | | | | | | | | | | | | | | | | On Cr50 the crypto library has a slightly different API, as indicated by the presence of the CONFIG_DCRYPTO configuration option. This patch provides a wrapper which allows to calculate a SHA256 HMAC hash using either underlying crypto API. BRANCH=cr50 BUG=b:37952913 TEST=make buildall -j Change-Id: Ibb8c60e50139fd5506a4dd5f2ed19653c68af8cb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/690440 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gsctool: improve vendor command processing robustnessVadim Bendebury2017-10-021-11/+20
| | | | | | | | | | | | | | | | With upcoming RMA authentication extensions the size of the vendor command responses is going to increase. Let's allow 500 bytes per response (the expected maximum is 80 bytes plus TPM header). BRANCH=cr50 BUG=b:37952913 TEST=verified that gsctool (aka usb_updater) still allows to retrieve Cr59 information and update Cr50 image. Change-Id: Ic61b6b89ffe20e534029bd12fea4140882a9afc8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/690442 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* rma_reset: fix board ID ordering and add the missing breakVadim Bendebury2017-09-301-1/+6
| | | | | | | | | | | | | | | The Board ID is stored in Cr50 in reversed byte order, make sure it is used in the challenge calculation in the same form. BRANCH=none BUG=b:37952913 TEST=verified that the proper byte order is used when challenge source is created. Change-Id: I6c6b46431005ce9438a4be9aa43aafed30a645aa Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693615 Reviewed-by: Michael Tang <ntang@chromium.org>
* vboot: Add error message in hash commandJagadish Krishnamoorthy2017-09-291-0/+1
| | | | | | | | | | | | | | | | Hash command expects second parameter to be either abort, RO, RW. If not then exit the function by displaying error message instead of calculating hash. BUG=NONE BRANCH=NONE TEST=On EC console 'hash help' should display error message with usage info. Change-Id: I4fcad97ce0da1cd48a458de1c659aa3c6b2a60b9 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/691436 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* g: limit compiling in crypto tests to cases where CR50DEV > 1Vadim Bendebury2017-09-293-3/+5
| | | | | | | | | | | | | | | | | | | To aid with severe flash space shortage, let's enable CRYPTO_TEST_SETUP only if CR50_DEV is set to a value exceeding 1. board/mn50/board.h used to define CR50_DEV without any value assigned to it, correct this so that the check in dcrypto.h works when mn50 is built. BRANCH=cr50 BUG=b:65253310 TEST=compiling with CR50-DEV=1 vs CR50_DEV=2 saves more than 17.5 Kbytes per RW image. Change-Id: Ic77fa45b1a8f7631efa91c08e63438d412196eed Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/690993 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* sweetberry: adding a flag to print milliwattsMengqi Guo2017-09-291-5/+13
| | | | | | | | | | | | | | | | | | Adding a flag to print power numbers in milliwatts instead of microwatts, to be the same as servo ina board. This will make it easier for power team to keep track of power numbers in the future. BRANCH=None BUG=b:35578707 TEST=./powerlog.py -b xxx.board -c xxx.scenario --mW python -m unittest -v stats_manager_unittest Change-Id: I397da26561324227682404e62ee025384e7624eb Signed-off-by: Mengqi Guo <mqg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/688743 Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
* cr50: Add ccdblock command to block portsRandall Spangler2017-09-291-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when CCD is opened, there is no way to disable the EC and/or AP UARTs. But if there is some problem with the EC and/or AP, and their UARTs are spamming interrupts, it can make debugging more difficult. If servo detection malfunctions, then CCD may drive the ports and interfere with servo. Add a new ccdblock command to disable the AP UART, EC UART, or any ports shared with servo, until the next cr50 reboot. BUG=b:65639347 BRANCH=cr50 TEST=manual with CR50_DEV=1 image, AP/EC powered on, suzyq connected ccdblock --> (none) ccdstate --> UARTAP+TX UARTEC+TX I2C SPI ccdblock AP on ccdstate --> UARTEC+TX I2C SPI ccdblock EC on ccdstate --> I2C SPI ccdblock -> AP EC ccdblock AP off ccdstate --> UARTAP+TX I2C SPI ccdblock EC off --> (none) ccdstate --> UARTAP+TX UARTEC+TX I2C SPI ccdblock SERVO on ccdstate --> UARTAP UARTEC ccd lock ccdblock AP on --> access denied Change-Id: I3dcc8314fc98a17af57f2fe0d150ecd1a19ccf52 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693041 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* sweetberry: calculate statistics for sweetberry readingsMengqi Guo2017-09-294-27/+278
| | | | | | | | | | | | | | | | | | | This CL provides the tool to calculate statistics for sweetberry readings and present them in a clear & easy to read format. It also provides the flag to store raw data and statistics summary, should the need arise. There are also some code cleanup for powerlog.py. BRANCH=None BUG=b:35578707 TEST=./powerlog.py -b xxx.board -c xxx.scenario --print_stats \ --save_stats --save_raw_data python -m unittest -v stats_manager_unittest Change-Id: I4aa732756fe6512f37acfcb59b11d950101887d7 Signed-off-by: Mengqi Guo <mqg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667241 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* Fizz: Initialize PMIC after AP power is readyDaisuke Nojiri2017-09-292-14/+18
| | | | | | | | | | | | | | | | | On proto3, PMIC isn't powered on POR, thus board_pmic_init fails. With this change, EC waits until AP power is ready before it notifies HOOK_CHIPSET_PRE_INIT where PMIC will be initialized. When AP power is ready, PMIC should be ready as well. BUG=b:65839247,b:64944394 BRANCH=none TEST=Run reboot [/cold/ap-off] command on BJ and Type-C. Change-Id: I7e7e07b5acf92167584966ded0a5f14fb6b04f0b Reviewed-on: https://chromium-review.googlesource.com/672152 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Update rma_reset command line interface.Sam Hurst2017-09-291-45/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Usage: rma_reset --key_id <arg> --board_id <arg> --device_id <arg> --hw_id <arg> | --auth_code <arg> These value are used for generating the challenge response and all are mandatory. -k,--key_id Index of the server private key -b,--board_id BoardID type field -d,--device_id Device-unique identifier -w,--hw_id Hardware id The -t parameter, not listed, will use the default values to generate the challenge response This value is the authorization code and any other parameters are ignored -a,--auth_code Reset authorization code BUG=b:37952913 BRANCH=none TEST=make buildall Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: Idc916b123928328a3425fa4eee22afc2ec179fc1 Reviewed-on: https://chromium-review.googlesource.com/665388 Commit-Ready: Sam Hurst <shurst@google.com> Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Michael Tang <ntang@chromium.org>
* Fizz: Show critical error on LED for recovery requestDaisuke Nojiri2017-09-293-2/+12
| | | | | | | | | | | | | | | | Fizz EC verifies RW by itself and jumps to RW before AP boots. If this fails, the system needs recovery. Since EC isn't capable of showing any info on a display, we use the power LED to inform the user. BUG=b:66914368 BRANCH=none TEST=Make Fizz fail RW verification. Observe LED illuminates in red. Change-Id: Ia07de60a316b40e74b1917903996d78750b4ae43 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/683218
* Fizz: Blink LED to request more powerDaisuke Nojiri2017-09-294-17/+39
| | | | | | | | | | | | | | | | | | This patch makes the LED blink to alert the user when there is not enough power to boot the system. This patch also changes minimum boot power to 50W. It's common for all SKUs. BUG=b:37646390 BRANCH=none TEST=Power Fizz with 15W, 45W, 60W chargers. Verify LED blinks as expected. Change-Id: If269897f5022f6cba80f37ce03e2315cfb2cf504 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/682876 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rma_reset: hide generated files from gitVadim Bendebury2017-09-281-0/+5
| | | | | | | | | | | | | | | | | This prevents the files from showing in 'git status' output. BRANCH=none BUG=none TEST=verify that the running the following does not show any generated files: make -C extra/rma_reset; git status Change-Id: Ib3ff7772cf4a66e4a0d23ed859c30ac05c2e507d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/691016 Reviewed-by: Michael Tang <ntang@chromium.org>
* it83xx: gpio: remove 5.1K resistor connected to GND of CC pinsDino Li2017-09-281-0/+7
| | | | | | | | | | | | | | | | If we don't use IT8320's PD module, we should dis-connect resistor to GND and disable CC related function to make sure these pins can work as other function. BRANCH=none BUG=none TEST=CCCSR register setting is 0xff after initialization if we don't enable CONFIG_USB_PD_TCPM_ITE83XX. Change-Id: I97e019ec1c9c852cd758b364a5e7913de1fc84f4 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/689435 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* board: reef_it8320: Report device orientation isn't tablet modeDino Li2017-09-282-0/+12
| | | | | | | | | | | | | | | We need to response EC ACPI device orientation command or keyboard/trackpad didn't work on OS image version R58 and after. BRANCH=none BUG=none TEST=keyboard and trackpad work on R58 and after. Change-Id: I49f9c90e73a5e529eb228169e4148f4dcd4a45e6 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/689715 Reviewed-by: Shawn N <shawnn@chromium.org>
* servo_v4: add pd commandsNick Sanders2017-09-281-0/+1
| | | | | | | | | | | | | | Add CONFIG_CMD_PD into servo v4, to enable more console PD commands, BRANCH=None BUG=b:65497998 TEST=run the sommands. Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I85c3f585779ccd51cff48c564083fd42fe5c454b Reviewed-on: https://chromium-review.googlesource.com/663840 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* npcx: espi: Fixed the bug which ec cannot enter deep sleep on npcx7.Mulin Chao2017-09-281-0/+8
| | | | | | | | | | | | | | | | | | | In npcx7, we introduced a new bit, VWUPDW, in ESPISTS register to indicate a Master-to-Slave VW signal was updated and the relevant WE bit is 1. But there's no relevant IE bit in ESPIIE for VWUPDW, old mechanism for clearing pending bits of ESPISTS will ignore this bit. And ec cannot enter deep sleep anymore since this bit is set. This CL fixed this bug by setting bit 17 of mask variable if ec is npcx7 series. BRANCH=none BUG=none TEST=No build errors for npcx5/7 series. Change-Id: I80c57d3c230e9d06ba134538ccdcd29f290bb7bf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/672183 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
* npcx: espi: Add new bit fields of eSPI regs and remove useless ones.Mulin Chao2017-09-281-36/+71
| | | | | | | | | | | | | | | | | | | | | | | | | In this CL, we introduced new bit fields of eSPI registers on npcx5/7 for the incoming patches. We also remove useless registers such as VWGPMS, VWGPSM and PING in order to let the driver look more clearly. This CL also includes: 1. Fixed typo from ESPIIWE to ESPIWE. 2. Introduce ESPIWE bits fields on npcx5/7. 3. Introduce new bit fields in ESPISTS of npcx7. 4. Remove useless VW1-4, VW1IE1-4 bits in ESPISTS and ESPIIE registes. 5. Introduce new bit field, WE, in VWEVMSn register of npcx7. BRANCH=none BUG=none TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c 1000" to do stress test and no symptom occurred on poppy. Both warmboot and coldboot stress test for 3 hours and no symptom occurred on poppy. Change-Id: Ie8aa3dbd148588b0d9a756572d66604a6836a760 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/672026 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
* tigertool: add serial number checkNick Sanders2017-09-281-0/+24
| | | | | | | | | | | | | Add --check_serial to check serial number. BRANCH=None BUG=b:35849284 TEST=check serial number. Change-Id: I1e2d5617bcf65e2388b88aca7ed63b9cdc096d87 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/676723 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* chip/stm32/clock: Wakeup AP when rtc alarm goes offPhilip Chen2017-09-282-0/+21
| | | | | | | | | | | | | | BUG=b:63908519 BRANCH=none TEST='powerd_dbus_suspend --wakeup_timeout=10' and see AP do S0->S3(10 secs)->S0 Change-Id: I35e248627e2f3b68b0ed3f27d6bae65eb73a745b Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/674054 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charge_manager: Support no-BC1.2 configurationShawn Nematbakhsh2017-09-285-33/+12
| | | | | | | | | | | | | | | | If BC1.2 isn't supported, don't waste space + time checking for inputs that don't exist. BUG=chromium:759880 BRANCH=None TEST=`make buildall -j` Change-Id: I47e81451abd79a67a666d1859faf2610ee5c941a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/663838 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* poppy: cleanup GPIOsNicolas Boichat2017-09-283-21/+0
| | | | | | | | | | | | | | - Deprecate poppy rev0. - Remove FP_INT_L BRANCH=none BUG=b:65104436 TEST=make buildall -j Change-Id: Ie2afae95a4fed43e8c2dc9e18031cf3e82eb3536 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/689817 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* chip/stm32/clock: Incorporate RTC date registerPhilip Chen2017-09-276-93/+177
| | | | | | | | | | | | | | | | | | | | | | | The current stm32 rtc driver only uses RTC_TR and RTC_SSR. So we son't be able to use rtc for applications which need time > 24 hours. To support such applications, this patch adds operations for RTC date register (RTC_DR). BUG=b:63908519 CQ-DEPEND=CL:666985 BRANCH=none TEST=manually with 'ectool rtcset/rtcset' and '/sys/class/rtc/rtc0', verify the conversion between calendar time and Unix epoch time works. Change-Id: Iacd5468502e4417a70880d7239ca5e03353d9469 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/659337 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* vboot: Modify the parameter offsetJagadish Krishnamoorthy2017-09-272-1/+6
| | | | | | | | | | | | | | | | | For the Host Command vboot hash EC_VBOOT_HASH_GET case, if the input parameter offset and size is 0 then change offset to data_offset to obtain the latest hash value. Else retain the offset to get the hash value at offset. BUG=b:66957716 BRANCH=NONE TEST=On Soraka, ectool echash commands (RO, RW) should result in hash information. Change-Id: Ife17d35b0dfeecb5ec799c9ed722ae48dbec5b5b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/685738 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* scarlet: enable console help and historyBrian Norris2017-09-271-2/+0
| | | | | | | | | | | | | | | We're not hurting for flash space. And this helps us stupid kernel developers, who haven't memorized all EC commands. BUG=none BRANCH=none TEST=build and boot scarlet Change-Id: I9046ff3802512d24f17acffa7e0b2faddb702c0b Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/688506 Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: compress array of prime deltasVadim Bendebury2017-09-271-273/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The array storing deltas between sequential prime numbers could be compressed, as the vast majority of the values in the array does not require more than 4 buts to store. The new storage format is as follows: - each differential value (difference between two consecutive primes) is halved and stored in 4 bits, two halved values are packed per byte. - I the first one of of the two sequential halved values exceeds 0xf, it is stored in the array followed by a zero, stored as is (without halving), thus taking two bytes. - if the second one of the two sequential halved values exceeds 0xf, both values are stored in the array as is, both prepended by zeros, thus taking 4 bytes. The code calculating the sequential primes parses the array according to this format. Storing the primes in this format allows to shave from the image size 1848 bytes. BRANCH=cr50 BUG=b:65253310, b:65287300 TEST=verified that test_rsa test from the tpmtest suite passes. verified that the list of prime numbers printed out when PRINT_PRIMES is defined and test_rsa is ran is the same before and after this patch. Change-Id: Ifdc2858a48f868ef816ccb4e351d9f60703d16e7 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/664253 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Coral: Add LG battery for Santa and Porbeagle.david.huang2017-09-271-6/+87
| | | | | | | | | | | | | | | | | | | 1.Add LG battery for Santa and Porbeagle. 2.Santa LG battery manufacture name is same as BATTERY_LGC011, so use device name to recoginze Santa LG battery. 3.These two battery have different process to get FET status, make sure battery not use this process is before BATTERY_LGC15 to separate these two different process. BRANCH=none BUG=b:65426428, b:64772598 TEST=Make sure battery can cutoff by console "cutoff" or "ectool cutoff" and resume by plug in adapter. Change-Id: I7095b9d0915fb4d39aa6c9f8c8751aa22941e938 Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/674472 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Fizz: Set proper max powerDaisuke Nojiri2017-09-261-1/+2
| | | | | | | | | | | | | | | | This patch raises the max power for a type-c adapter to 60W (20V @3A). We can't go above the regular cable capacity (3A) until we add e-marked cable detection. BUG=none BRANCH=none TEST=Boot Proto3 on Zinger. Observe 60W (20V @3A) is selected. Change-Id: I9670d710e363c7db1136a7ce7a7f8401b0ad8240 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679210 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: i2c: remove instructions that aren't necessaryDino Li2017-09-262-227/+93
| | | | | | | | | | | | | | | | | | | | | | - To i2c channel(d/e/f), we remove instructions that aren't necessary. - Changes of i2c_reset(): Before the change, we try to send a START/STOP bit if we get a reset. But i2c_unwedge() already done it, so we just need reset i2c module in i2c_reset(). - Add enhanced_i2c_start() to channel(d/e/f) for each transaction start: We prepare transaction start by calling i2c_reset(), but this doesn't match the definition of i2c_reset(), so we correct it. BRANCH=none BUG=none TEST=1. console commands: "i2cscan", "charger" and "battery". 2. sensors, battery, charger and mux work on reef_it8320. Change-Id: I4e3595479e04a5994a5b19409cfc4e9a46f63d4f Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/674467 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7_evb: change the default setting of npcx7 evbCHLin2017-09-262-1/+7
| | | | | | | | | | | | | | | | | | | | | In this CL, we add the follow changes for npcx7 evb board: 1. Add comments in the build.mk to indicate how to set CHIP_VARIANT for EVBs which use different npcx7 ec. - npcx7m6f : 144 pins (default) - npcx7m6g : 128 pins 2. Turn on the eSPI host interface as default in board.h BRANCH=none BUG=none TEST=No build errors for "make buildall". Change-Id: Ib926e8596a09a28f547c35a0256be2aa394f9a36 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/674887 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rtc: Add functions and tests for time conversionPhilip Chen2017-09-267-0/+240
| | | | | | | | | | | | | | | | | | | | | To implement rtc driver for some ec chips, we need to convert between calandar date and seconds (since epoch time, 01-01-1970 00:00:00). Sicne these functions are HW-independent, let's add common/rtc.c, include/rtc.h, and unit test for this. BUG=b:63908519 BRANCH=none TEST=make buildall test -j Change-Id: Icb1e768d2b3674d5225b83e09475e984eb104d06 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/666985 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* g: Provide a pinhold interfaceNadim Taha2017-09-272-1/+36
| | | | | | | | | | | | | | | This change is required to reboot the chip without bringing down the entire platform on boards where GPIOs are wired to external active reset signals. BRANCH=none BUG=none TEST=Scoped a pin across a reset. Change-Id: I58d93697d39a8adcdac9324d5dd9da00745aec9a Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/644179 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: dcrypto: add debug function to print primesVadim Bendebury2017-09-261-0/+26
| | | | | | | | | | | | | | When compilation is enabled, this function prints all prime numbers generated using the PRIME_DELTAS array. BRANCH=cr50 BUG=none TEST=verified that prime numbers are printed out when running rsa_test.py Change-Id: I37961aad146c4aeecca9a84550f313450e6c5853 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/683074 Reviewed-by: Shawn N <shawnn@chromium.org>
* tpmtest: make the test work againVadim Bendebury2017-09-264-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TPM test directory has bitrotted and does not compile any more, leave alone pass tests. This patch updates the tests to match changed EC codebase: test/tpm_test/Makefile - look for include files in more directories test/tpm_test/bn_test.c - add implementation of always_memset() which for the EC tree now comes from a different tree and provide a plug for watchdog_reload() which is no used by dcrypto code (which in fact is not a good idea, but an issue for another day). test/tpm_test/hash_test.py - update to match new format of return messages test/tpm_test/upgrade_test.py - update to match the new format of return messages and limit the test to installing just 2K worth of data BRANCH=cr50 BUG=none TEST=./test/tpmtest/tpmtest.py now passes Change-Id: Ibcd7fcfba06cd83023e35a2ac4f37ec896492ad4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/665322 Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: fix hash test code memory managementVadim Bendebury2017-09-261-6/+18
| | | | | | | | | | | | | | | | | | | The hash test code memory management is somewhat loose: it does not clean up allocated buffer, but then uses it to check for presence of the previously created handles, which can result in false positives. Let's zero the buffer each time it is allocated and let's use hash_test_db.contexts as the indicator if the buffer is allocated or not. BRANCH=cr50 BUG=none TEST=ran ./test/tpm_test/tpmtest.py, observed rsa tests pass. Change-Id: Iad4b4e2662fc7266ee6f556f6ddfd0051e7172d7 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/665321 Reviewed-by: Shawn N <shawnn@chromium.org>
* samus_pd: Adjust input current limit downward to prevent OCShawn Nematbakhsh2017-09-261-5/+2
| | | | | | | | | | | | | | | | | | | | | | Based on measurements, Samus can pull more current than desired, even taking into account the existing INPUT_CURRENT_LIMIT_OFFSET_MA adjustment. Decrease the programmed current limit by an additional factor, determined by taking the worst-case power measurements across 15 different Samus devices, to ensure that Samus never pulls more current than desired. BUG=chrome-os-partner:55297 BRANCH=samus TEST=Verify with debug prints that curr_lim_ma becomes 256 when negotiated current limit is 500mA and curr_lim_ma becomes 2556 when negotiated limit is 3000mA. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6912d987c5a519f55a831698873a69c4cac817b8 Reviewed-on: https://chromium-review.googlesource.com/684696 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Kahlee: Provide functionality for apshutdownAkshu Agrawal2017-09-261-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trigger the power press for shutdown. Also, avoid powering up the AP by checking if we are not in G3, before triggering the power press. BUG=b:66698593 TEST= > apshutdown [7045.198370 chipset_force_shutdown()] [7045.198870 PB PCH force press] [7045.199368 PB PCH pwrbtn=LOW] > LPC RESET# asserted[7049.218062 power state 3 = S0, in 0x000c] [7049.218718 Pass through VGATE: 0] [7049.219281 power state 7 = S0->S3, in 0x000c] [7049.220647 chipset -> S3] [7049.221108 power state 2 = S3, in 0x000c] [7049.221763 power state 8 = S3->S5, in 0x000c] [7049.222522 USB charge p0 m0] [7049.223217 chipset -> S5] [7049.223716 power state 1 = S5, in 0x000c] [7049.224334 PB PCH force release] [7049.224840 PB PCH pwrbtn=HIGH] [7049.232875 SW 0x01] [7049.240557 TCPC p1 Low Power Mode] [7049.252249 TCPC p1 Low Power Mode] [7049.254363 TCPC p0 Low Power Mode] [7049.266006 TCPC p0 Low Power Mode] [7059.225553 power state 9 = S5->G3, in 0x000c] [7059.226188 chipset_force_shutdown()] [7059.226717 PB PCH force press] [7059.233871 PB PCH pwrbtn=LOW] [7059.234381 power state 0 = G3, in 0x000c] [7059.250255 power state 0 = G3, in 0x000f] [7059.256533 SW 0x05] Change-Id: Ibc27c90f806deed6a2ca7035869c4e10ca7fbf0b Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://chromium-review.googlesource.com/683956 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* virtual_battery: Avoid unexpected batt_mode_cache refreshingJeffy Chen2017-09-251-2/+4
| | | | | | | | | | | | | | | | | | | | | Currently we are assuming batt_mode would never be zero, but that is not always true. Some battery do report zero for batt_mode(bob for example). So everytime the batt_mode_cache been set to zero, the virtual_battery would consider it uninited, and tries to refresh the next time. Use -1 as uninited batt_mode_cache to avoid that. BUG=b:66555246 BRANCH=gru TEST=Check on bob, the battery level is correct. Change-Id: Ieb7ec9403f69a6b5bca93c6682ec6117fe95fe1e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/678135 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fizz: Limit input currentDaisuke Nojiri2017-09-254-54/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Fizz has an over current control system. There are two FETs connected to two registers: PR257 & PR258. They control the max input current as follows: PR257, PR258 For 4.62A (90W BJ adapter), on, off For 3.33A (65W BJ adapter), off, on For 3.00A (Type-C adapter), off, off BJ adapters are distinguished by reading GPIO71. This patch also removes ISL9238 driver and ramping code. The charger chip has been removed from the board since proto2. BUG=b:65013352 BRANCH=none TEST=Boot Fizz Proto3 on BJ and Type-C. Change-Id: I32c2467f4ab23adf3f9313a03914d74d64a722df Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/668119 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* twinkie: enable WebUSBVincent Palatin2017-09-251-0/+2
| | | | | | | | | | | | | | | | | | Prepare the future and return a WebUSB descriptor to be able to use the dongle from this website. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=twinkie BUG=none TEST=manual: enumerate WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome R61+. Change-Id: I6a36538667ac114fc4b40cb87b2d6e946e265c4d Reviewed-on: https://chromium-review.googlesource.com/677285 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Kahlee: FIXUP: Optimize g-sensor settingGwendal Grignou2017-09-242-1/+5
| | | | | | | | | | | | | | | | Kionix Accel does not have FIFO, enable force mode for it. Chrome needs sensor for screen orientation, set to to 10Hz in S0 in the EC. BRANCH=none BUG=b:62029360 TEST=none Change-Id: I5545580f2073e9d1145bd86cfcd594164119cae7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/675575 Tested-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Gwendal Grignou <gwendal@google.com>
* zoombini: Enable TCPC interrupts.Aseda Aboagye2017-09-231-0/+47
| | | | | | | | | | | | | | | | | | | The TCPC interrupts were setup, but they weren't enabled yet. This commit enables the interrupts. Additionally, a "tcpcdump" debug command is added. This can be removed later or expanded upon to be more generic. BUG=None BRANCH=None TEST=Flash zoombini; Verify that we respond to TCPC alerts. Change-Id: Iba9523cbfb96a570b76e7bdc0ba21dd782854f24 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/670063 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fizz: Pulse LED using deferred callDaisuke Nojiri2017-09-222-57/+74
| | | | | | | | | | | | | | | | | This patch makes LED pulse using deferred call to save RAM and CPU cycles. This patch also adds led_alert API. It blinks LED as a warning. BUG=b:37646390 BRANCH=none TEST=Verify LED on in S0, pulse in S3, and off in S5. Run 'led alert' command. Change-Id: I8c61f91f095eed562d2ee9582868879241df626f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/675749 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add WebUSB descriptor supportVincent Palatin2017-09-226-21/+163
| | | | | | | | | | | | | | | | | | | | | | | | | The WebUSB specification defines a specific Platform Descriptor in the Binary Object Store: https://wicg.github.io/webusb/#webusb-platform-capability-descriptor This descriptor provides a special 'Landing page' URL to the host browser and associated privileges for it. Bump the USB version for BOS descriptors to 2.1 to be compatible with Chrome implementation. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=none BRANCH=twinkie TEST=manual: on Twinkie (chip/stm32) and HG proto2 (chip/g), enumerate WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome R61+. Change-Id: I7211ab554f4a6c156c1e8e79a3d9f0d6644217c6 Reviewed-on: https://chromium-review.googlesource.com/664813 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
View Lorry Controller Status