| Commit message (Collapse) | Author | Age | Files | Lines |
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BRANCH=none
BUG=b:112441618
TEST=manually test adc command on a reworked rev2 board:
(1)When a Type-C charger is plugged, VBUS is measured ~5000mV.
(2)When a 15V PD charger is plugged, VBUS is measured ~15000mV.
(3)When no charger is plgged, VBUS drops to ~0mV.
Change-Id: I0340d1e4428260e6898eccdac930a9d96d9836bd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1196847
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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HOWTO set up an EC board such that plugging it in and turning it on Just
Works.
BUG=none
BRANCH=none
TEST=load docs in a markdown viewer for formatting.
Change-Id: Ib1b31fe0a3c26ac7aad95d362f89afc25f57bf99
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1180403
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BRANCH=none
BUG=b:111214767
TEST=boot grunt with artificially locked RO firmware. Observe that
depthcharge holds and waits on the firmware. Manually sysjump to rw,
and observe that PD negotiation takes place and depthcharge is released.
Change-Id: Id6add9fb7b3a40a67a945742a2e8df848233bc47
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1180402
Reviewed-by: Edward Hill <ecgh@chromium.org>
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The power signals, AP_RST_L and PMIC_FAULT_L, are floating when
switchcap off. Disable their interrupts. The PS_HOLD and POWER_GOOD
should be OK as they have pull-down.
BRANCH=none
BUG=b:78455067
TEST=Checked "power on", "power off", "apshutdown", and
"apreset".
Change-Id: I17e4c7e8f82e950b52d750961f4b5efc01c18ccf
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1180066
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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The AP_RST_L is not a good signal to indicate power good. For an AP
initiated warm reset (the Qualcomm way), AP pulls down PS_HOLD for a
short pulse, and then PMIC pulls down AP_RST_L for another short pulse.
This short pulse confuses EC from a power-lost. We use a confirmation
logic to differentiate this case as a workaround. This CL uses another
signal POWER_GOOD, which is SRC_PP1800_S4A from PMIC, as an indicator.
CQ-DEPEND=CL:1169952
BRANCH=none
BUG=b:78455067
TEST=Checked "power on", "power off", "apshutdown", and "apreset".
Verifed the power-off sequence:
* if the PMIC registers not programmed, it forces off switchcap.
* if the PMIC registers programmed, it does graceful PMIC shutdown.
Change-Id: I847eef5d4202485b70354b3f65ce24cd1ccb7ece
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1169953
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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This reverts commit 548e4d9708cc4402497ed290daf4df672114302c.
The following CL uses the POWER_GOOD signal as an indicator, instead of
the AP_RST_L which has a short low pulse during warm reset. So revert
the confirmation logic for the AP_RST_L.
BRANCH=none
BUG=b:78455067
TEST=Check the following CL.
Change-Id: Iec0a7592f8dd1686b1bce8304b42ad0407b6dfde
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1169952
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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Modify the USB charge mode setting.
SDP mode:
USB_A0_CHARGE_EN_L=High, USB_A1_CHARGE_EN_L=High
CDP mode:
USB_A0_CHARGE_EN_L=Low, USB_A1_CHARGE_EN_L=Low
BUG=b:112292707
BRANCH=none
TEST=Can detect the Pioneer BDR-XD06J-UHD and BDR-XS06T DVD rom
via USB port. And use the command "ectool gpioget" to check
the GPIO USB_A0_CHARGE_EN_L and USB_A0_CHARGE_EN_L the voltage
level is correct.
Change-Id: Ica5f3dae726adb82f5062bead3a7a73f566b5987
Signed-off-by: matt_wang <matt_wang@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1193562
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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On these devices we can't decide whether we should go in/out tablet mode
solely because base was attached or detached. Let's report the new "base
attached" event so that upper layers can figure the state properly.
Note that we disable CONFIG_DPTF_DEVICE_ORIENTATION switch since it
requires CONFIG_TABLET mode which we disable as well. That means that
EC_ACPI_MEM_DEVICE_ORIENTATION will always return '0', which should be
fine, as it is used by the TBMC (Tablet Motion Control) device which is
not enabled on Nocturne. Note that base attach/detach events, like
tablet mode switch events, will still wake up the AP as handles base
state transitions always notifies host of attach/detach events.
BUG=b:73133611
BRANCH=nocturne
CQ-DEPEND=CL:1183972,CL:1187120
TEST=Build and boot
Change-Id: Ide0693a50f041be876f42295bccf2896a13a625c
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1180539
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Starting with board_version 2, Bobba uses BMI160 instead of LSM6DSM for
base sensor support.
All Bobba boards with board_version < 2 should have SKU id set to 255,
and thus only have the lid sensor enabled. This change replaces the
LSM6DSM support with BMI160 support.
BUG=b:113369413
TEST=compile
BRANCH=none
Change-Id: Ib307e9c279162b445fb5fb8cae39b94bc401ecdb
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194880
Reviewed-by: Tino Liu <tino.liu@quanta.corp-partner.google.com>
Reviewed-by: Paris Yeh <pyeh@chromium.org>
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With the updates in the release process the location for saving a new
signed image has changed, let's update instructions printed by the
signer script.
BRANCH=none
BUG=none
TEST=none
Change-Id: I70901256f79bae2a4c20f59c00a51c5cc9309df7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194618
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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We are running out of RAM space for nautilus and the UART buffer does
not need to be 4KB. 1KB is almost enough, so 2KB should be plenty. In
the long term chromium:826592 will allow us to use even smaller buffers.
BRANCH=none
BUG=chromium:826592,b:112088135
TEST=builds and links with child CL stack
Change-Id: I054f884fea5761de26888a5b4fe26ded6c2ffbd9
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194082
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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There is a unneeded level on indirection for the anx74xx alert handler
that we can remove. This also make is more clear what is happening in
the child CLs.
See go/usb-pd-slow-response-time for more information.
BRANCH=none
BUG=none
TEST=no change on grunt device
Change-Id: I61f7caf09fc5cb5fa889fb727ee39bea681a97e9
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185726
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
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CapCnt variable will be reset in PD_STATE_SRC_STARTUP,
PD_STATE_SRC_DISCOVERY and PD_STATE_SNK_SWAP_COMPLETE states
which are according to PD3.0 spec. With this modify in order to
protect against future changes that allow other code path
that don't clear the variables first.
BUG=none
BRANCH=none
TEST=make buildall -j.
Change-Id: Ic2a249aff4410043ab18dd645aa1485ece9f63ca
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1195169
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Rammus uses EEPROM to store the device info like sku id, board version.
This patch adds the cbi config for rammus.
BUG=b:111815817
BRANCH=master
TEST=ectool cbi set/get
Change-Id: I776de02b66b8545a2998635a974933fadd1e4d7a
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194547
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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this enables the system to wake up from hibernate when charging power
is applied over one of the USB-C ports.
BUG=b:113543019
BRANCH=none
TEST=verified atlas wakes from hibernate on 1st AC-in
Change-Id: Ib9e724f38987c0a0798aef6d8fe6e6d73bb07809
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194998
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
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BUG=b:113045336
BRANCH=none
TEST=put EC in hiberate using EC console, verified lid-open wakes
atlas
Change-Id: Ic0380b660978a3ca09935cadb1c581840883a1c9
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194997
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
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It complements crrev.com/c/1137434 in the way EC Reset got released.
Instead of time-basis, it shall be released when the power button
is released.
The desired sequence of actions is:
0. (optional) Have a CR50 console and EC console connected to terminals.
1. Do a shutdown.
2. Press the power button and keep it pressed.
3. Plug a SuzyQ cable.
4. CR50 console shall be connected back, but not EC console.
5. Release the power button at any proper time, so that EC can restart.
To keep EC from resetting, do "ecrst true" in CR50 console right after
Step 4. It will invalidate Step 5.
BRANCH=cr50
BUG=b:37351386
TEST=manually on Duts, Bob (Chrombook) and Sion (chromebox).
(A) hard-reset
A-1. Binary Download + Hold power button => no delay in EC reset.
(B) Wake from hibernation
B-1. (EC console) hibernate
B-2. unplug all cables
B-3. hold "POWER BUTTON" + plug SuzyQ cable => no delay in EC reset.
(C) Power-on reset
C-1. "REFRESH" + "POWER BUTTON" + unplug power cable.
C-2. unplug SuzyQ cable
C-3. plug SuzyQ cable => no delay in EC reset.
(D) Power-on reset
D-1. "REFRESH" + "POWER BUTTON" + unplug power cable.
D-2. unplug SuzyQ cable
D-3. hold "POWER BUTTON" + plug SuzyQ cable. => EC reset gets held.
D-4. release "POWER BUTTON" ==> EC gets reset.
(E) Power-on reset + explicit "ec_rst true"
E-1. "REFRESH" + "POWER BUTTON" + unplug power cable.
E-2. unplug SuzyQ cable
E-3. hold "POWER BUTTON" + plug SuzyQ cable. => EC reset gets held.
E-4. (CR50 console) ecrst true
E-5. release "POWER BUTTON" ==> EC reset still gets held.
(F) Power-on reset + explicit "ec_rst false"
F-1. "REFRESH" + "POWER BUTTON" + unplug power cable.
F-2. unplug SuzyQ cable
F-3. hold "POWER BUTTON" + plug SuzyQ cable. => EC reset gets held.
F-4. (CR50 console) ecrst false => EC gets reset.
F-5. release "POWER BUTTON" ==> Nothing happens.
(common) Press "POWER BUTTON" again, and check CR50 doesn't have any
more "POWER BUTTON" release events.
Changes to be committed:
modified: board/cr50/board.c
modified: board/cr50/board.h
modified: board/cr50/power_button.c
modified: chip/g/rbox.c
Change-Id: Ic39c9ce7849fa3187e1d277320adf671f857d18d
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1192691
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Some boards are pretty tight on RAM space. Print out remain RAM bytes
for each board along with the tightest 3 boards during buildall.
BRANCH=none
BUG=none
TEST=buildall now outputs the tightest boards on RAM.
Change-Id: I819e554400e88937bb937f2ca51daf737588a9a5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194342
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
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Currently, charge_get_state checks battery_was_removed and returns
PWR_STATE_ERROR if it's set. battery_was_removed does not reflect the
current battery presence.
This patch makes charge_get_state check the current battery presence
(curr.batt.is_present).
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:111969858
BRANCH=none
TEST=Boot Pantheon with/without a battery. Verify LED is on/off before and
after sysjump expectedly.
Change-Id: Id7a9d57b9b4040c488405fb2d0fec0da238eaefc
Reviewed-on: https://chromium-review.googlesource.com/1180350
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This change sets booter RAM size to 2KB as it was orignally
configured. This was changed to 1KB in CL:858637, but there was no
explanation about the change. Because of that, panic data would be
lost on all NPCX7 boards.
BUG=b:113274400
BRANCH=nocturne
TEST=Verified that panic data is preserved on crash with various
options on yorp.
Change-Id: I15f578823ed06aed7cb064f3f76bd52d57fc6767
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1192701
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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BRANCH=cr50
BUG=none
TEST=none
Change-Id: I397dc1fe7d0382db995880a6963621ab1e4c0b38
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194346
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The base detection logic is similar to Lux base. But Cheza one doesn't
have a battery inside. So skip the dual-battery charging logic and give
the power to the base right after it is plugged.
BRANCH=none
BUG=b:112614067
TEST=Remove the base battery. Plug and unplug the base. Check the EC
messages showing the base connected and disconnected.
Change-Id: I363860609b17ae74c09ccdb681c99123f7a38a06
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1176732
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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Also, FORCE_RESET is open-drain, active-low. Also, set the default
to high.
BRANCH=none
BUG=b:112616655
TEST=boot rev1 to coreboot
Change-Id: I33bd4a97831313f7bc5c3f0044c5b44d88932060
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1192722
Reviewed-by: Yilun Lin <yllin@chromium.org>
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Passing empty auth code causes cr50 to generate challenge instead of
verifying the auth code. Change to return an error when the auth code is
empty.
BUG=b:112881027
TEST=make gsctool; manually test on DUT
BRANCH=none
[Before fix]
localhost $ gsctool -a -r
Challenge:
<80 characters challenge string>
(Wait for 10 seconds)
localhost $ gsctool -a -r ""
Processing response...RMA unlock succeeded.
[After fix]
localhost $ gsctool -a -r
Challenge:
<80 characters challenge string>
(Wait for 10 seconds)
localhost $ gsctool -a -r ""
Empty response.
Change-Id: Ifc2760176ff620dd45c5d62ced117c808ce1f111
Signed-off-by: Cheng-Han Yang <chenghan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1192822
Commit-Ready: Cheng-Han Yang <chenghan@chromium.org>
Tested-by: Cheng-Han Yang <chenghan@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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We set the baud rate in increments of 100 baud, to avoid
overflowing the 16-bit wValue integer (921600 is the highest we
are likely to use).
Also, increment the buffer size for USART3 to 1024 bytes. That
helps a bit to avoid losing characters, but we still can't keep
up if the host is printing at maximum speed.
BRANCH=servo
BUG=chromium:876651
TEST=baud usart2/3/4 115200 in servo_micro console
TEST=dut-control cpu_uart_baudrate:921600
seq 1 1000 shows numbers 1 to 226 before buffer overflows
Change-Id: Ifca266189f93def493f207dd29d2cceca4d8d68f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1189782
Reviewed-by: Nick Sanders <nsanders@chromium.org>
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No power sequence logic is chanaged. Add PS_HOLD, PMIC_FAULT_L, and
POWER_GOOD (the real one, not AP_RST_L) as power signals. If their
states change, the EC console will show it and the timestamp.
BRANCH=none
BUG=b:78455067
TEST=Ran "gpioset SWITCHCAP_ON_L 0" and showed the signals changed:
7 signal changes:
750.164712 +0.000000 AP_RST_L => 0
750.164810 +0.000098 PMIC_FAULT_L => 0
750.165312 +0.000502 PS_HOLD => 0
750.166565 +0.001253 POWER_GOOD => 0
750.206345 +0.039780 PMIC_FAULT_L => 1
751.190869 +0.984524 PMIC_FAULT_L => 0
751.233388 +0.042519 PMIC_FAULT_L => 1
Change-Id: I1237f4fff20e2256f504d3c9d11ed26da5224ecd
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1169951
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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BRANCH=None
BUG=b:112113303
TEST=w/ battery: check state transition behaves correctly when sourcing
and sinking.
TEST=w/o battery: check sinking behaves correctly when sourcing.
Change-Id: I2ae0d1f9266d14f91aa36d6974bf276aeba79b68
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1177466
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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DPDM_IRQ_MASK register address should be at 0xE6, rather than 0xE5.
Shift the mask init value to the right address.
TEST=make BOARD=kukui flash_ec; Attach DCP. Check chgsup type=3.
BUG=b:80160408
BRANCH=None
Change-Id: I44eac570bf2d8fe11a3f460ed97f024f4be3813a
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1192862
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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BRANCH=none
BUG=b:112616655
TEST=Flash P1
Change-Id: I585cc4f60be31ea41df40ca289f7f8824179cf70
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1192662
Reviewed-by: Yilun Lin <yllin@chromium.org>
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Add charge LED behavior to meet spec:
AC attached: solid on White.
Charging: solid on Amber.
Discharging(S0/S3/S5): Both(White/Amber) Off.
Battery Error: Blinking White (0.5 sec on, 0.5 sec off)
Fuel <10%: Blinking White (1 sec on, 1 sec off)
Force idle for factory: Blinking Amber (1 sec on, 1 sec off)
BUG=b:112825269
BRANCH=None
TEST=manual
Check charge Led off when battery is discharging.
Check charge Amber Led on when battery is charging.
Check charge White Led on when battery is full
and AC is attached.
Check charge White led blink(0.5 sec on, 0.5 sec off)
when battery error.
Check charge White led blink(1 sec on, 1 sec off)
when battery fuel less than 10%.
Check charge Amber led blink(1 sec on, 1 sec off)
when factory test.
Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com>
Change-Id: I2cc2f9d710a6b94fa48f6d2fb78ac7996a7615f5
Reviewed-on: https://chromium-review.googlesource.com/1184941
Commit-Ready: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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It was observed on multiple devices that Fingerprint MCU hangs and WDT
reboots MCU on fingerprint enrollment. This patch should fix/mitigate
the issue.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:112781659
BRANCH=none
TEST=Verify no crash is observed on Nocturne when enrolling
a fingerprint.
Change-Id: I6eec541650200cd2370e5505947e788f7a5e08b9
Reviewed-on: https://chromium-review.googlesource.com/1192102
Commit-Ready: Nicolas Norvez <norvez@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
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Instead of calling system_hibernate directly from hibernate console
command, set reboot_at_shutdown and trigger chipset_force_shutdown if
chipset is not already off. This allows hibernate to go through the
chipset task to allow it to put power rails into proper state before
EC hibernates. If chipset is already off, then system_hibernate would
be called directly.
BUG=b:113132913
BRANCH=None
TEST=Verified that system_hibernate is called from chipset task if
chipset is up.
Change-Id: Id3b4d8597f536c4854714f79bd5bd077a826ad22
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1188517
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It was observed that with the call to chipset_force_shutdown in
board_hibernate, PMIC_EN and EN_PP3300_A did not go low if hibernate
was requested by AP on shutdown. This is because board_hibernate gets
called from chipset task and so control never gets to
chipset_do_shutdown.
This resulted in two problems:
1. Unnecessary power consumption in PSL mode on different rails.
2. Failure to wake from PSL using normal wake sources.
The right thing to do when hibernating is to ensure that the chipset
power rails are properly brought down. Thus, this change makes a call
to chipset_do_shutdown if board_hibernate is called from within
chipset task which pulls down the chipset rails and thus
ensures proper power rail state before EC enters PSL hibernate.
BUG=b:113132913
BRANCH=None
TEST=Verified:
1. Enter PSL by running hibernate on EC console. EC enters hibernate
properly and wakes using power button.
2. Enter PSL by running following commands on AP console:
ectool reboot_ec hibernate at-shutdown
poweroff
EC enters hibernate properly and wakes using power button.
Change-Id: I7a4862461383072430a9cf01e257efa3589a0cc9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1187841
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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this enables active discharge for the PP5000_A rail.
BUG=b:112732855
BRANCH=none
TEST=flashed atlas with new EC build
Change-Id: Ib733eb6e649d9f22c7ce0d1e4bc565f9a2659520
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1187900
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
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change disable the keyboard for convertible
Get the motion sensor count by SKU
motion_sensor_count on clamshells is 0.
motion_sensor_count on convertibles is 2.
lid_angle_peripheral_enable() function disable
the keyboard for convertible systems.
BUG=b:112286331
BRANCH=none
TEST=Manual
change SKUID to 0x21 for convertible and verified the motion sensor
count and that the motion senors were initialized in the EC console log.
change SKUID to 0x01 for clamshell and the motion senors were
not initialized in the EC console log.
Change-Id: Ic9d6c910c9e56479414d30f1e2c53d73515842af
Signed-off-by: elthanhuang <elthan_huang@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1192903
Commit-Ready: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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When our SRC port is in SRC_READY state, the SNK
send GET_SRC_CAP to us. Our SRC port sends SRC_CAP,
but it doesn't wait power request just transit to
SRC_READY state immediately. According to 8.3.3.2
SRC state diagram of PD3.0 spec, when SRC pd port
receive GET_SRC_CAP in SRC_READY state, it should
send SRC_CAP and then transit to SRC_NEGOCIATE state
for waiting power request from SNK. With this modify
it can solve GRL-USB-PD compliance TDA2.2.9 test
fail issue.
BUG=none
BRANCH=none
TEST=GRL-USB-PD compliance test.
Change-Id: I1fe0c59e5a08863b360bbb3731c3620a4f23c1bf
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1170722
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Add a capability for opening cr50 without dev mode and a capability for
opening cr50 from the console. This will make it so cr50 can easily be
opened from the console after RMA open.
BUG=b:113266255,b:113267161
BRANCH=cr50
TEST=verify OpenFromConsole and OpenW/ODevMode are set to IfOpened with
CCD_OPEN_PREPVT isn't defined and set to Always when it is defined. Make
sure they are set to Always after factory mode is enabled.
Change-Id: Ic149b4163ee9a3ce5e0c051dc42634a31a4a0a7e
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1191386
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Mary Ruthven <mruthven@chromium.org>
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Occasionally cc1 and cc2 might be in a valid debug range for a short
time even if a debug accesssory isn't connected. The rdd hardware will
debounce the signals long enough to make sure they're stable before
triggering the Rdd interrupt. This change moves all rdd
connect/disconnect logic to the interrupt instead of sampling the
voltages in detect_rdd. In detect_rdd the samples of the cc lines
falsely triggered rdd connect whenever the cc voltages happened to be in
the valid debug range. We weren't waiting for Rdd to declare the voltage
stable before running rdd connect. Moving the logic from rdd_detect to
rdd_interrupt will ensure the signals are actually stable before we
change the rdd state.
BUG=b:113064204
BRANCH=cr50
TEST=manual
connect suzyq
reboot cr50
verify rdd is connected
disconnect suzyq
verify rdd is disconnected
boot nami
leave it up for a while
make sure there aren't any false connects
reconnect suzyq
verify rdd is connected
disconnect suzyq
verify rdd is disconnected
reboot cr50
verify rdd is disconnected
run firmware_Cr50CCDServoCap and firmware_Cr50DeviceState
Change-Id: I3eeaa39f79d2ccc3e997da291d8aae1f12103dc8
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1185967
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Mary Ruthven <mruthven@chromium.org>
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This reverts commit 3b39bc56d38511e10871447392b709b3b8e65637.
Reason: wedges consoles on servod.
BRANCH=None
BUG=b:113246887
TEST=reverting unbreaks servod
Change-Id: I2f4dd65727347ce4757c4863664e3b2e46c826fc
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1191383
Tested-by: Raul E Rangel <rrangel@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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UART3 and 4 had DMA collisions. Remove DMA from UART4.
BRANCH=servo-9040
BUG=b:112701646,chromium:865478
TEST=reboot EC, no crashy
Change-Id: Ic44b363dafe938d6420b350eb1c5ab796da81f3c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1188514
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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As documented in the datasheet, NPCX_DEVCNT_F_SPI_TRIS must be 1 for ECs
that use internal flash (e.g., NPCX79nF and NPCX797W).
BRANCH=none
BUG=b:112906111
TEST=No build errors for make buildall. Flash image on npcx7_evb; check
this bit is not cleared. Flash image on yorp; check the platform boots
up to OS screen.
Change-Id: I533553ad91ce0ecc79fc55b86aa83bbbcf514d89
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1188180
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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Enable running ccd open from the console. Do not require dev mode to run
the command.
PREPVT ONLY. DO NOT MERGE INTO MP.
BUG=b:112861587
BRANCH=cr50-prePVT
TEST='ccd open' can be run on the console, and it doesn't require dev
mode.
Change-Id: Ie666d3bdf56a525deb7764bbcd03676174745cd3
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1188928
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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On prePVT images we wan't to allow ccd open from the console without dev
mode enabled. This change adds a config option limiting ccd open.
BUG=b:112861587
BRANCH=cr50
TEST=ccd open is still disabled from the console unless the password is
set.
Change-Id: I2adbf9b0e900a693ab513a6bf6650b320b7320d4
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1188927
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BUG=b:113127952
BRANCH=firmware-nocturne-10984.B
TEST=Enable HW/SW WP, plug in a PD charger, verify no PD communication
is done in RO.
Change-Id: Idc9219c70662b1b51e228863e2bd51a72cecb2b1
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1188929
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Preserved bbram state causes failure to reinit on reboot.
Clear on board init.
BRANCH=None
BUG=b:111573811
TEST=PD reinits on reboot.
Change-Id: Ifdf98b5793cb99e2900ac5dc53263a86317b6b07
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1187883
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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status register and data
Modify LGC/BYD board_battery_info of
shipping mode reg_addr and LGC/BYD/Simplo
FET status of reg_addr/reg_mask
BUG=b:112322236,b:112237278
BRANCH=none
TEST=Use "ectool batterycutoff", system can shutdown.
Plugin AC can power on system and battery return
BATTERY_NOT_DISCONNECTED.
Change-Id: I0d7a2b2c9d27a058b67f7b48970aaaab2ebee9b8
Signed-off-by: elthanhuang <elthan_huang@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1170669
Commit-Ready: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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this adds definitions for some additional PMIC registers we're using
in our codebase.
BUG=b:112732855
BRANCH=none
TEST=flashed atlas with new EC build
Change-Id: Ibad7b11b3770f00c925c2d8fc3b24109147aa643
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1187899
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
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There are several ways to detect VBUS present. Using the BC1.2
to detect is through a GPIO. It is more effective than talking
to the TCPC chip over I2C comm.
Change the config from CONFIG_USB_PD_VBUS_DETECT_TCPC to
CONFIG_USB_PD_VBUS_DETECT_CHARGER.
BRANCH=none
BUG=b:112179392
TEST=Plugged and unplugged charger to port-0 and port-1. Verified
the charging state correct.
Change-Id: I9dd69cd17099b5794988efca9d8c7a82af3614a5
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1170126
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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This function is not called from outside this file so make it static. Also
drop a pointless comment, and rename the function since the 'system' prefix
suggests it is defined in system.h (which it is not).
BUG=chromium:876737
BRANCH=none
TEST=make -j50 BOARD=grunt
Change-Id: Ic429fb1da2e56e1888e008f4739c90e8ed2c1947
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1184975
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Right now, when the parent process dies ungracefully - say kill -9 -
then the interpreter, and console processes remain active.
This leads to bugs in the servod implementation from holding on to
sockets, to reinitialization issues of a new instance on the same servod
device.
This change quits the loops inside console & interpreter as soon as the
parent pid changes (i.e. the parent dies).
BRANCH=None
BUG=chromium:841121
TEST=sudo servod -b soraka
ps aux | grep servod
>xxxxx servod
>xxxxy servod
>xxxyx servod
>xxxaa grep servod
sudo kill -9 xxxxx
ps aux | grep servod
>xxxab grep servod
Before this, just kill -9 on the main thread did not take the children
with it.
Change-Id: I547bd92bf8732bff8aef2b72840417c809ba27d6
Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1186299
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
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