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* ish: remove lock; prefix from inline ASMstabilize-atlas-11177.BJett Rink2019-01-093-5/+19
| | | | | | | | | | | | | | | | | | | | | | | Since all instances of minute-ia core are a single core, the lock; prefix on statements does not have any meaningful affect other than a potential performance hit. We still want to mark inline asm where it would matter, so we introduce a new define that evaluates to empty today. BRANCH=atlas_ish BUG=none TEST=builds Change-Id: I47506951dfdabfdbd16ae825fe742b01b44205d1 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1401014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 7ced9b2e02cdb49b78384ecb93978c1bab5cd015) Reviewed-on: https://chromium-review.googlesource.com/c/1401808 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ish/uart: fix wrong register address access in uart_tx_start()Hu, Hebo2019-01-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | void uart_tx_start(void) { ... if ( REG8(IER(id) & IER_TDRQ) ) return; ... } the expression 'REG8(IER(id) & IER_TDRQ)' is wrong, '(IER(id) & IER_TDRQ)' is not a register address but a '0' value, '0' address is a invalid address in ISH. the correct expression of read IER register and check TDRQ bit should be: 'REG8(IER(id)) & IER_TDRQ'. BUG=b:122052562 BRANCH=none TEST=tested on arcada Change-Id: I811ce68ff17e197df83a8d44bffaa58799cbb3b6 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1390942 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> (cherry picked from commit a3a17f0013e294b9b9496d78b9b2ab6cefa45270) Reviewed-on: https://chromium-review.googlesource.com/c/1401215 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ish: remove unused codeJett Rink2019-01-072-45/+2
| | | | | | | | | | | | | | | | | | | | The variable need_resched_or_profiling wasn't being used in a way that was meaningful and added unnecessary complexity. Removing. BRANCH=none BUG=b:121343650 TEST=build with profiling disabled and task switching on aracarda still works Change-Id: Ic54bcb0f3c6b66aecbb8cf806ead5dd3695bdb35 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389057 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Caveh Jalali <caveh@google.com> (cherry picked from commit 08803b0ac80815332b07a5d8ecf3aa3c830665b8) Reviewed-on: https://chromium-review.googlesource.com/c/1397170 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: HID: enable HID subsystemHyungwoo Yang2019-01-021-0/+3
| | | | | | | | | | | | | | | | | | | | | enable HID subsystem. BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279433 Change-Id: I50ce44c76abe823a68745ee8114cc8f0fabbe36c Reviewed-on: https://chromium-review.googlesource.com/1279314 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit 2b0d9e6c40ea71e0f3e66759c758c07e8879ca07) Reviewed-on: https://chromium-review.googlesource.com/c/1392415 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: HECI: enable HECIHyungwoo Yang2019-01-022-0/+3
| | | | | | | | | | | | | | | | | | | | | enable HECI. BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279432 Change-Id: I3184f822e5ad026164b86efbd4b6dabf1102db86 Reviewed-on: https://chromium-review.googlesource.com/1279313 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit 1c9d56efdaa9d9b10df27a5c488c007e710f3544) Reviewed-on: https://chromium-review.googlesource.com/c/1392414 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: IPC: enable IPC for HECIHyungwoo Yang2019-01-022-1/+4
| | | | | | | | | | | | | | | | | | | | | enable IPC for HECI BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279363 Change-Id: I98568b537b4b812e97c22dff610e1147ed12701d Reviewed-on: https://chromium-review.googlesource.com/1279311 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit 3dceabb07dc76191ca56d97ee3941a1a84d0a27a) Reviewed-on: https://chromium-review.googlesource.com/c/1392413 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: HID: implement HID subsystemHyungwoo Yang2018-12-293-0/+531
| | | | | | | | | | | | | | | | | | | | | | | Introduce HID subsystem. HID subsystem provides interface for a HID device to communicate with host. Using this API, a HID device can use hid-core in host. BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279432 Change-Id: I0547a07e1c1cb5d34ba11b245ca539cf53b7d30d Reviewed-on: https://chromium-review.googlesource.com/1279433 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit fe24755501c10405f02da94f3179ceb0bcde4fc3) Reviewed-on: https://chromium-review.googlesource.com/c/1392412 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: HECI: implement HECI layerHyungwoo Yang2018-12-296-0/+1418
| | | | | | | | | | | | | | | | | | | | | | | | Introduce Host Embedeed Controller Interface for ISH. HECI is bi-directional fully asynchronous communication interface between host and ISH. It enables a host software to communicate with a ISH software(a HECI client). BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279363 Change-Id: I5fdc3018e9575c5fd0c804a883293f6c9f8aa2e7 Reviewed-on: https://chromium-review.googlesource.com/1279432 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit a2c87e75cc5b42b900832f0e80244c077b497f2c) Reviewed-on: https://chromium-review.googlesource.com/c/1392411 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: IPC: implement generic IPC layerHyungwoo Yang2018-12-295-0/+1009
| | | | | | | | | | | | | | | | | | | | | Introduce new IPC API supporting MNG and HECI protocols. Currently it supports communication with host(x64) BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. Change-Id: Iea6d1f96c89228b425861d045618d58f9d146f08 Reviewed-on: https://chromium-review.googlesource.com/1279363 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit 737317a19e54bb4dfa4d646b11354b4a9d275791) Reviewed-on: https://chromium-review.googlesource.com/c/1392410 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: fix atomicsHyungwoo Yang2018-12-291-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | this fixes a few wrong implementation on atomic. atomic_read_clear() and atomic_clear() were functinally broken. Due to this, key control flow which rely on these functions were out of order. Also modified ATOMIC_OP() and bool_compare_and_swap_u32() to give more accurate directives to compiler. BUG=b:119628522 BRANCH=none TEST=tested on atlas Change-Id: Ide8397e4f7b754a7094c66326ecc2450ef2f0cc9 Reviewed-on: https://chromium-review.googlesource.com/1305118 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit db9a02ec4110769b7300f45ade770205e70934de) Reviewed-on: https://chromium-review.googlesource.com/c/1392409 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: enable cacheKyoung Kim2018-12-201-0/+9
| | | | | | | | | | | | | | | | | | | | | Enable cache CR0.CD and CR0.NW Trackpad frame processing improved with cache on. BUG=b:120885570 TEST=check overall performance improvement including TP frame processing. Change-Id: I18d27b28255d5775c71b7562e18a1d102ee35feb Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1378659 Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> (cherry picked from commit fd13a286bc99cc2e56e3ef1bb82fcdb63734985a) Reviewed-on: https://chromium-review.googlesource.com/c/1387602 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* board/atlas_ish: remove CONFIG_ISH_30 flag in atlas_ish boardShine Liu2018-12-201-1/+0
| | | | | | | | | | | | | | | | | | | | As we have replaced all all CONFIG_ISH_xx flags in in chip/ish/* files with CHIP_FAMILY and CHIP_VARIANT, abandoning original CONFIG_ISH_xx flags. BRANCH=none BUG=b:112385410 TEST=Test host FW loading for main ISH FW. Change-Id: Ie0635a49585d456504bd1027406c5d6929dc5a8c Signed-off-by: Shine Liu <shine.liu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367011 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com> (cherry picked from commit c0f7b510be978963eef81af927655a5743e89fd7) Reviewed-on: https://chromium-review.googlesource.com/c/1385671 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* chip/ish: replace CONFIG_ISH_xx flags with CHIP_FAMILY and CHIP_VARIANTShine Liu2018-12-204-19/+17
| | | | | | | | | | | | | | | | | | | | | | Replace all CONFIG_ISH_xx flags in chip/ish/* files with CHIP_FAMILY and CHIP_VARIANT. Which provides more structural defines between ISH generations. BRANCH=none BUG=b:120295222 b:112385410 TEST=Test host FW loading for main ISH FW. Change-Id: Ica92eee11034447c9f0828aa986fb1736d20cf27 Signed-off-by: Shine Liu <shine.liu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367010 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit 0d28df409ea6fa112d1ffefef9e8349dd355d4fc) Reviewed-on: https://chromium-review.googlesource.com/c/1385670 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* board/atlas_ish: add CHIP_FAMILY and CHIP_VARIANT to atlas_ishShine Liu2018-12-201-0/+2
| | | | | | | | | | | | | | | | | | | | | To accommodate the changes coming to ISH chip generations including CHIP_FAMILY and CHIP_VARIANT instead of current defines of CONFIG_ISH_xx. BRANCH=none BUG=b:120295222, b:112385410 TEST=Test host FW loading for main ISH FW. Change-Id: I03af74aa1b45cd4d1f030489a171506064721b3c Signed-off-by: Shine Liu <shine.liu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367009 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit d352b810f72b381679839f2d60423cc5d627aaf6) Reviewed-on: https://chromium-review.googlesource.com/c/1385669 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: default_fp_ctx[] should be staticRushikesh S Kadam2018-12-201-1/+1
| | | | | | | | | | | | | | | | | | | | Define the default_fp_ctx[] for initial FP state as static variable. BRANCH=none BUG=b:120582727 TEST=Succesfully compile for ISH target Change-Id: Iac60a814ab7a9c3090b47472adebf05b1341c5fb Reported-by: Caveh Jalali <caveh@google.com> Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1365155 Commit-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> (cherry picked from commit 4790392940e3b70a843274e1acb952e8f22825f6) Reviewed-on: https://chromium-review.googlesource.com/c/1385486 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: Reset Task-switched flag during initRushikesh S Kadam2018-12-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is observed that CRO.TS may be set prior to main ISH FW entry. In such case, an ESC instruction such as fninit assembly instruction for FPU initialization, will cause a fault. The execution handlers are not setup this early in FW initialization phase, and will lead to ISH CPU reset. This patch resets the TS flag in early FW initilization. BRANCH=none BUG=b:120051132 TEST=Test host FW loading for main ISH FW. Change-Id: I7e330e2d1f39cc4a349f308ec0d046c19db281de Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1316702 Commit-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> (cherry picked from commit 4dd9607ff06416f09b5d91dc531a23c9c54d14ec) Reviewed-on: https://chromium-review.googlesource.com/c/1365153 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: Add missing #ifdef CONFIG_FPURushikesh S Kadam2018-12-181-0/+2
| | | | | | | | | | | | | | | | | | Fix compilation error generated with CONFIG_FPU disabled. BRANCH=none BUG=b:120051489 TEST=Disable CONFIG_FPU and verify code compiles fine. Change-Id: I0ddfe610a33cc2bdebebed4e149afbfa92f2543a Reported-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1316701 Reviewed-by: Caveh Jalali <caveh@google.com> (cherry picked from commit e5ddc233ebc2285e3d145c6206c86c483bfbae11) Reviewed-on: https://chromium-review.googlesource.com/c/1365152 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* chip/ish: change host command ready from 8 to 3Shine Liu2018-12-131-1/+1
| | | | | | | | | | | | | | | | | | | To accomondate upcoming arcada_ish board, changing MNG_HC_FW_READY from 8 to 3 BRANCH=none BUG=b:120295222 TEST=Test host FW loading for main ISH FW. Change-Id: Ibee24cb01c6078177ba9ef1ad30c360a3157a84e Signed-off-by: Shine Liu <shine.liu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367012 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit 01e6ca1ebb1a254d332347eb31b8ae1436eb6991) Reviewed-on: https://chromium-review.googlesource.com/c/1375569 Commit-Queue: Caveh Jalali <caveh@google.com>
* ISH3.0: Scaling timer from 12MHz to 1MHzSadashiva Rao Pv2018-12-133-4/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | -Added support to scale 12MHz to 1MHz -Fixes the timestamp issue -Changes under CONFIG_ISH_30 ISH 3.0 has 12MHz Main counter ISH 4.0 has 32KHz Main counter BUG=none BRANCH=master TEST=On Soraka board modified for ISH, ensure clock tick happens correctly. Ensure ISH probe and sensor info is seen in kernel logs Change-Id: Ib5d8a48bf99d1398a0424596399abd7df431e07a Signed-off-by: Naresh Solakni <naresh.solanki@intel.com> Signed-off-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/686434 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> (cherry picked from commit 80e6645b2d9876be58102c454cb0cf188f1d1eff) Reviewed-on: https://chromium-review.googlesource.com/c/1375099 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: Setup GDTRushikesh S Kadam2018-12-111-0/+29
| | | | | | | | | | | | | | | | | | | Setup GDT for main ISH FW BRANCH=none BUG=b:120051488 TEST=Verify that main ISH FW runs fine when loaded through host FW load flow. Change-Id: I8101de6c2482abb09ccc8fdc36321fa562e521d7 Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Signed-off-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1316700 Commit-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> (cherry picked from commit f645b4591de099c245dd8e69bdc785134fdfdb7a) Reviewed-on: https://chromium-review.googlesource.com/c/1365151 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH-i2c: support 1MHz, clock stretch, restartKyoung Kim2018-12-043-84/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | - Support for 2 or more bytes size of command register in slave device. - Adjust parameters for FAST and FAST+ modes. - added Restart and SCL stretch BUG=b:113238573 TEST=test with FAST/FAST+ mode Elan TrackPad slave device. Use i2c_xfer() API inside a test task which GPIO interrupt (Elan device's INT line) wakes. Change-Id: I1ebcef90d85d6ede90bb8687e20058bdf31bf4e8 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/996799 Commit-Ready: Caveh Jalali <caveh@google.com> Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> (cherry picked from commit 1aeb203a2feb48536454d888469a6bb4e9fb3b46) Reviewed-on: https://chromium-review.googlesource.com/c/1360075 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: add IRQ to vector entry for doorbell clearHyungwoo Yang2018-11-211-0/+1
| | | | | | | | | | | | | | add IRQ to vector entry for doorbell busy bit clear interrupt. BUG=b:79676054 BRANCH=none TEST=tested on Atlas board Change-Id: I3c168326b8c7e300eac0f80f828bcadf1585e54d Reviewed-on: https://chromium-review.googlesource.com/c/1347021 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: remove sending MNG_HC_FW_READYHyungwoo Yang2018-11-211-9/+0
| | | | | | | | | | | | | | | | remove sending MNG_HC_FW_READY from task. the sending MNG_HC_FW_READY should be done by IPC task that supports Host Command. BUG=b:79676054 BRANCH=none TEST=tested on Atlas board Change-Id: Iea2d2864c67763c8c8e18b520c5a776b5ce469fb Reviewed-on: https://chromium-review.googlesource.com/c/1347016 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* atlas_ish: remove HostCommand task related.Kyoung Kim2018-11-211-3/+1
| | | | | | | | | | | | | | | | | | | | Atlas is migrated from Host Command to HECI protocol. Remove Host Command task and old ipc task. BUG=b:79676054 TEST=none Change-Id: Ic77b1d16de7772a1c69cba6fcf5d7d7849a06213 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1263897 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> (cherry picked from commit b48cc28be9186d022013c9b997a13c2c93e2ec14) Reviewed-on: https://chromium-review.googlesource.com/c/1347019 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: IPC: send HC FW ready notification to hostHyungwoo Yang2018-11-212-0/+4
| | | | | | | | | | | | | | send Host Command FW ready notification to host driver. BUG=b:79676054 BRANCH=none TEST=tested on Atlas board Change-Id: I5148351d91151e964561c821c02634bd32163dfd Reviewed-on: https://chromium-review.googlesource.com/c/1347020 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* IPC/HECI: IPC/HECI uses lpc console channelKyoung Kim2018-11-211-1/+5
| | | | | | | | | | | | | | | | | | | IPC/HECI will shares same channels as LPC. BRANCH=b:79676054 TEST=none Change-Id: I2c423107df1fa7c7ab8084aa543519b0c9054e1d Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1263895 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> (cherry picked from commit 8024fb852bbfc72efe8c7135cb7d0f3e0f2e12dd) Reviewed-on: https://chromium-review.googlesource.com/c/1347017 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ish-ipc: remove IPC/Host command related flagKyoung Kim2018-11-211-1/+1
| | | | | | | | | | | | | | | | | | | | Remove flag related to IPC interface & Host command protocol to add new IPC & HECI protocol BUG=b:79676054 TEST=none Change-Id: I4707e2845c38a4d86ab8bffad93f7024fa9e5eb5 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1263896 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> (cherry picked from commit 42f0cd98f872f670b8f70b057ed9e8312beefa05) Reviewed-on: https://chromium-review.googlesource.com/c/1347018 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ish gpio: GPIO functionalityli feng2018-11-152-3/+120
| | | | | | | | | | | | | | | | | | | BUG=b:116451255 BRANCH=none TEST=Tested on Atlas board, ISH GPIO is working. Change-Id: I29121dd143a5bf44a7431d12d9e05a3510fb4654 Signed-off-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/954718 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit c9b5321774df82fa153644f0ef3bf05ed08dd48a) Reviewed-on: https://chromium-review.googlesource.com/c/1338600 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: fixes toolchain incompatibiltyKyoung Kim2018-11-131-1/+1
| | | | | | | | | | | | | | | | | | Default coreboot toolchain(gcc 8.1, linker) does not generate __bss_size_words absolute value. ABSOLUTE() built-in function is used to make both old(4.9) and new(8.1) toolchains compatible. BUG=b:118355015 BRANCH=none TEST=built code with both old(4.9) and new(8.1) and verified __bss_size_words abolute value and tested if ISH system boots. Change-Id: I07ca0b68b222a2754866abdacb0a5d8585d01566 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/1334530 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ish gpio: added GPIO interrupt to IOAPICli feng2018-11-133-1/+12
| | | | | | | | | | | | | | | | | | BUG=b:116451255 BRANCH=none TEST=none Change-Id: I3d6883554393c1733a902eff8ea3680ec9de33e1 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/884604 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> (cherry picked from commit 12eacd182f5fba9cc744037c04c8e6317752b9fa) Reviewed-on: https://chromium-review.googlesource.com/c/1334037 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: Add FLASH memory configurationPatrick Georgi2018-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | Even though it's not flash (and therefore rwx), the section layout indicates these parameters. Add them as Memory Configuration to meet the expectations of the "bytes free" report. BUG=none BRANCH=none TEST=no more atlas_ish board with -63k bytes free in flash after make buildall Change-Id: Ic476496d66bfc9c4e69a808542c778379d76c4b5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1318295 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: Fix FPU flagKyoung Kim2018-10-301-1/+1
| | | | | | | | | | | | | | | Fix bug in following CL. https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1154187 BUG=b:118628615 TEST=check if FPU-utilzing tasks can operate properly. Change-Id: Id7f6a5f7827a9ffc81684b7f91705b4c72f03eab Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/1306876 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* ISH: add FPU context save/restoreKyoung Kim2018-10-251-1/+10
| | | | | | | | | | | | | | | | | | | | | | | Add FPU context save for current task and restore for next scheduled task. BUG=none TEST=check if FPU-utilizing tasks can resume without FPU operation issues. Change-Id: Id3c5ff1c9a6b3702a27b8ffc5f6a825877671ce4 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1154187 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> (cherry picked from commit da7538ace6400aa95ba14dfc3c28b9af08014792) Reviewed-on: https://chromium-review.googlesource.com/c/1300374 Commit-Queue: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* atlas_ish: initial board files for atlas_ishli feng2018-10-255-0/+162
| | | | | | | | | | | | | BUG=b:117807679 BRANCH=none TEST=build with BOARD=atlas_ish is successful Change-Id: Iddb9a8a5ced24e9b99753a876ec52b0062b80344 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/1298698 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* atlas_ish: implement __shared_mem_bufCaveh Jalali2018-10-251-0/+11
| | | | | | | | | | | | | | | | | | | when building the atlas_ish using emerge, additional components are built that we weren't building previously. in particular test/utils was falling over due to a missing symbol. BUG=b:118355015 BRANCH=none TEST=tested in combination of a bunch of other patches, emerge-${BOARD} chromeos-base/chromeos-ec succeeds at building atlas_ish Change-Id: Icf588afae8ed5410e21db733a9132bbc23ed2310 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1298697 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: default to coreboot toolchainCaveh Jalali2018-10-251-1/+2
| | | | | | | | | | | | | | | | | this sets the default toolchain for minute-ia to be the coreboot toolchain. BUG=b:118355015 BRANCH=none TEST=built using make from platform/ec, verified coreboot toolchain is used. Change-Id: I4078be8c1fafeee1e64c2ed008bb9f946f637077 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1298695 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: update linker script for coreboot toolchainCaveh Jalali2018-10-251-5/+7
| | | | | | | | | | | | | | | | | when using the coreboot toolchain, only C-line commends are allowed in linker scripts, so just fix the syntax. BUG=b:118355015 BRANCH=none TEST=tested in combination of a bunch of other patches to get atlas_ish to build with the coreboot toolchain Change-Id: I75094909d92eefade6d1756a06094dd537c5ce09 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1298694 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: fix code for coreboot toolchainCaveh Jalali2018-10-252-9/+2
| | | | | | | | | | | | | | | | this fixes some compilation issues when using the coreboot toolchain. BUG=b:118355015 BRANCH=none TEST=tested in combination of a bunch of other patches to get atlas_ish to build with the coreboot toolchain Change-Id: Id93822fa0a8112da45529b0ba4ab327b773a31d7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1298693 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia: clean up atomicsCaveh Jalali2018-10-253-82/+65
| | | | | | | | | | | | | | | | | | | | this cleans up the definitions in atomic.h. the coreboot toolchain wasn't very happy with the original declarations and definitions, and sure enough inline global functions don't make a lot of sense. so, i'm just going to apply the same definition style used for other architectuers here. BUG=b:118355015 BRANCH=none TEST=tested in combination of a bunch of other patches to get atlas_ish to build with the coreboot toolchain Change-Id: I654d1dd059b07484f724727d8546d8e7665d1b6c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1298372 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* core/minute-ia/panic: noreturn function should not returnli feng2018-10-251-0/+3
| | | | | | | | | | | | | | | | BUG=b:118296923 BRANCH=none TEST=build atlas_ish which use minute-ia and pass Change-Id: I7bd5ea67008e2f82c19390cee2d3a219bf376a30 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1287150 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> (cherry picked from commit 0cbe32e30f489f9ed7e396e07406e9b910c8b0f0) Reviewed-on: https://chromium-review.googlesource.com/c/1298370 Commit-Queue: Caveh Jalali <caveh@google.com>
* common/led_onoff_states.c: fix indentationPatrick Georgi2018-10-201-1/+1
| | | | | | | | | | | | | | | | gcc 8.1 warns about (and due to -Werror fails due to) misleading indentation. BUG=b:65441143 BRANCH=none TEST=compiling with coreboot-sdk works Change-Id: Ifda34a16a612dc4faa2faa8699159a27694ff5ae Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1290890 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* Keyboard: Allow keyboard size to be set at run timeDaisuke Nojiri2018-10-1919-56/+72
| | | | | | | | | | | | | | | | | | | | | | | Currently, the keyboard size (i.e. number of columns) is static. This patch allows it to be configured at run time. It's required to support a keyboard with/without keypad in a single image. KEYBOARD_COLS_MAX has the build time col size. It's used to allocate exact spaces for arrays. Actual keyboard scanning is done using keyboard_cols, which holds a runtime col size. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:117126568 BRANCH=none TEST=Verify keyboard functionality on Sona and Veyron. Change-Id: I4b3552be0b4b315c3fe5a6884cf25e10aba8be7c Reviewed-on: https://chromium-review.googlesource.com/1285292 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* board/meep: Add magnetometer configKarthikeyan Ramasubramanian2018-10-192-1/+31
| | | | | | | | | | | | | | | Enable the required modules to support magnetometer module and add magnetometer configuration. BRANCH=none BUG=b:115587004 TEST=Collect magnetometer readings through ectool motionsense Change-Id: Ibe2b624716b3a9a1ffba93e0b1b7edf3b718b6f9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1257505 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver/mag_lis2mdl: Add LIS2MDL magnetometer moduleKarthikeyan Ramasubramanian2018-10-194-0/+181
| | | | | | | | | | | | | | | Add support for LIS2MDL magnetometer module in cascade mode to LSM6DSM accelerometer module. BRANCH=none BUG=b:115587004 TEST=Collect magnetometer readings through ectool motionsense Change-Id: I06d11777543f14a557ebe6524f7ede15440f1f1e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1257504 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver/sensorhub_lsm6dsm: Add sensor hub support in LSM6DSM moduleKarthikeyan Ramasubramanian2018-10-195-0/+467
| | | | | | | | | | | | | | | Add support for sensor hub in LSM6DSM accelerometer module so that external sensors module like magnetometer can be supported. BRANCH=none BUG=b:115587004 TEST=Collect magnetometer readings using ectool motionsense Change-Id: Id0fd4eea56b7106a89d55925ae488af6b0300119 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1257503 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* include/motion_sense: Add a parent motion sensor fieldKarthikeyan Ramasubramanian2018-10-191-0/+6
| | | | | | | | | | | | | | | Add a parent motion sensor field in the motion sensor data structure so that the sensors in cascade mode can refer to their parents. BRANCH=none BUG=b:115587004 TEST=Collect magnetometer readings using ectool motionsense Change-Id: I709013e00c09f478c5bf41c15415ff3747c782c5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1278099 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver/accelgryo_lsm6dsm: Export accelgyro_config_fifo helper functionKarthikeyan Ramasubramanian2018-10-192-8/+9
| | | | | | | | | | | | | | | | Rename config_fifo function as accelgyro_config_fifo and export it to configure the accelerometer FIFO to support magmetometer data. Also remove a redundant else code by initializing the local variables appropriately. BRANCH=none BUG=b:115587004 TEST=none Change-Id: I6f35245b45941adaafd49cc0e26e1f9307c480c2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1257502 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Ampton: implement the LED function to follow BipJames_Chao2018-10-193-1/+78
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=Flash to ampton, check the LED is working Change-Id: Ib81e1744540f3c4cae9cb5704a3fe0398a1c2281 Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1288649 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/stm32/usb_hw: include stdint.h and stddef.hPatrick Georgi2018-10-191-0/+3
| | | | | | | | | | | | | | | It uses it, and its includers shouldn't need to know that. BUG=none BRANCH=none TEST=none Change-Id: Icf13d558e4d0772841a06313b352f88d40f1e165 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1177709 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* Keyboard: switch column and row of scancode tableDaisuke Nojiri2018-10-195-68/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch switches column and row of scancode_set2. That is, scancode_set2[ROWS][COLS] = {0x00, 0x01, 0x02, ..., 0x10, 0x11, ..., 0x20, ..., becomes scancode_set2[COLS][ROWS] = {0x00, 0x10, 0x20, ..., 0x01, 0x11, ..., 0x02, ..., This will allow us to extend the table for a keypad without losing too much readability. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:117126568 BRANCH=none TEST=Verify keyboard functionality on Sona. Change-Id: I49a7c0796d5c91989f1d3686c80743fb4bcd5ba7 Reviewed-on: https://chromium-review.googlesource.com/1285291 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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