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* meep: Disable accel, gyro sensors and tablet mode switch for clamshellsstabilize-jetstream-11056.BDevin Lu2018-09-112-3/+38
| | | | | | | | | | | | | | | | | | | | meep and mimrock both share with the same board, but mimrock is unstuff accel, gyro sensors and using hall sensor instead of GMR, so we don't need to initial those sensors and disable tablet mode. BUG=b:111823716,b:113962628 BRANCH=none TEST=make buildall -j. make sure no initial event occurs with mimrock. make sure tablet mode was disabled with mimrock. Change-Id: I8141ad8160807288d7a886488b98e93ed9a257b9 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/1193103 Commit-Ready: Zick Wei <zick.wei@quanta.corp-partner.google.com> Tested-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* bobba: do not disable keyboard for clamshellJett Rink2018-09-101-2/+2
| | | | | | | | | | | | | | Like other octopus boards, do not disable keyboard for clamshell SKUs BRANCH=none BUG=none TEST=build Change-Id: I260ae76da9c5c0ab9989cf284141ca86816a6511 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1204690 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* octopus: disable tablet mode switch for clamshellsJett Rink2018-09-103-16/+29
| | | | | | | | | | BRANCH=none BUG=b:113837268 TEST=verified that free magnet cannot put a clamshell SKU into tablet mode Change-Id: I5d69ede2da04cb5d067b6ae5a483323054b584ab Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1204452
* it83xx/fpu: restore ALU at the beginning of exception handlerDino Li2018-09-101-11/+11
| | | | | | | | | | | | | | | | | | | This change prevents CPU might execute a arithmetic instruction before ALU is restored in the exception handler (Apply to floating point division by zero). We also make the change to use GP register to set system DLMB register, so we can save R4 properly and print the correct panic information. BUG=b:112452221 BRANCH=none TEST=get a panic information if we do a floating point division and divide by zero. Change-Id: I20cb20500569c004af0336d1358ab0dd4b9452b9 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1201641 Reviewed-by: Jett Rink <jettrink@chromium.org>
* servo_updater: more informative error on failNick Sanders2018-09-081-1/+2
| | | | | | | | | | | | | | 'Can't detect updater version' is replaced with an error specifying the failed regex string. BRANCH=None BUG=None TEST=None Change-Id: Ia3a52ee27e31d0b4aab0d8f04d5cf5f346498c37 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1213556 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Move Virtual NVRAM indexes into header file.Louis Collard2018-09-082-19/+49
| | | | | | | | | | | | | | This is so that they can be referenced outside of the cr50 codebase. BUG=b:110971075 TEST=build BRANCH=none Change-Id: Id0754d2b1c9817aeb3db4d4d01ee9fbce8ca2a10 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1193563 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: make EC RST synchronousVadim Bendebury2018-09-081-14/+39
| | | | | | | | | | | | | | | | | | | | When the RBOX register controlling the EC reset output is written, RBOX does not act immediately, as it is controlled by its own clock. This results in the program continuing executing before RBOX output value change. This patch makes sure that execution does not continue until RBOX reacted to the request to change the EC RST output value. BRANCH=cr50. cr50-mp BUG=b:75976718 TEST=verified with logic analyzer that processing does not continue until EC RST output value changes. Change-Id: I72814d3c9ea11721e1b361e7f6d300658306562d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1214101 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: Change sleep in flash_wait_ready to 10usecFurquan Shaikh2018-09-071-15/+14
| | | | | | | | | | | | | | | | | | | | | | | flash_wait_ready had a sleep of 1 msec to check for busy bit status. This is too long of a wait for flash chip operation to complete and hence adds unnecessary delay during flash write. Changing the delay to 10usec helps cut the flash write time by 50%. This change reduces the delay to check busy bit to 10usec and also organizes the code slightly differently to use timestamp_expired() instead of decrementing timeout and checking it against 0. BUG=b:113530328 BRANCH=nocturne,grunt TEST=Verified that EC SW sync time is down to 3.4 seconds with this change. Change-Id: I5796ac3c493031c9623a9e5171ce9c5a7087089e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1213553 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb-pd: disconnect USB SS MUX when S5 or lowerJett Rink2018-09-072-41/+85
| | | | | | | | | | | | | | | | | | | Especially for SS MUX that have redrivers in them, we should disable the MUX while the chipset is off because the data line will not be used. This give decent power savings for redriver MUXs (e.g. PS8751) BRANCH=none BUG=b:112136208,b:111196155 TEST=On Phaser the 3300_pd_a drops from 92mW to 32 mW when the charger is plugged into C1 and the SoC is in S5. The rail also says at 32mW after removing and plugging the power back in while the SoC is in S5. Also ensured that power is low upon first insertion and AP does not come on automatically. Change-Id: I0601fbb506ad3eff902cf6562a6408292ef70e3a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185485 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* power: add chipset_in_or_transitioning_to_stateJett Rink2018-09-072-0/+43
| | | | | | | | | | | | | | | | | | | | | | | We need a method that we can call from the chipset notify hooks that can clearly distinguish which state you are about to be in. This is made evident by the child CL for putting a MUX into low power mode in S5. Without this method, we have to put chipset state into the PD task variable and use that instead (since chipset_in_state won't work because we are in the S3S5 state) BRANCH=none BUG=b:112136208,b:111196155,chromium:736508 TEST=On Phaser the 3300_pd_a drops from 92mW to 32 mW when the charger is plugged into C1 and the SoC is in S5. The rail also says at 32mW after removing and plugging the power back in while the SoC is in S5. Also ensured that power is low upon first insertion and AP does not come on automatically. Change-Id: I93cce2aa319c9689efce222919e5389471001a00 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1211368 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* keyboard: Ignore refresh button at bootDaisuke Nojiri2018-09-073-6/+0
| | | | | | | | | | | | | | | | | | | | | | | Any buttons except esc, left-shift, and down-arrow are considered as 'other key' and can cancel recovery mode entry if it's pressed at boot. On some chromebooks (e.g. Grunt, Nami), the refresh key is not scanned early enough (i.e. before the power button is released). Thus, the refresh key unintentionally cancels recovery mode entry. This change makes the EC ignore the refresh key at boot. This is already done for Grunt using CONFIG_KEYBOARD_IGNORE_REFRESH_BOOT_KEY. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:114134666 BRANCH=none TEST=Put Akali in recovery mode without holding power button long. Change-Id: I57d7cb8fb320a4960125cd96d4d3ae84687a74df Reviewed-on: https://chromium-review.googlesource.com/1208229 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tcpc: Add driver for TI TUSB422 tcpcScott Collyer2018-09-074-0/+84
| | | | | | | | | | | | | | | | | | | Initial driver for TUSB422 TCPC which is a tcpci compliant TCPC. This TCPC does not inlude a Type C mux and uses the tcpci driver for all of the methods. BUG=b:111281797 BRANCH=none TEST=Verified operation as sink on DragonEgg. Have not verified source operation, or low power/auto-toggle modes as those config options can't be enabled on ITE at this point. Change-Id: I783a5e2c4a13bc0b8fa4da4b134588382542024c Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1178994 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* grunt: Use higher priority TCPC interrupt tasks.Jonathan Brandmeyer2018-09-0710-68/+35
| | | | | | | | | | | | | | | | | | See also go/usb-pd-slow-response-time. Lift tcpc_alert_event interrupt handler to baseboard.c to reduce duplication. BUG=b:112848644, b:111909282 BRANCH=none TEST=Observe response time after SrcCap to Sink Request is 15ms on Careena and Grunt hardware after forcing a sysjump. Repeat test on Careena Port 0 with the DB disconnected (containing Port 1), also 15ms. Change-Id: I501bd86d84ba84eea0a705731e59e2431fc9a2ac Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194669 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* octopus: use higher priority TCPC interrupt tasksJett Rink2018-09-0712-65/+32
| | | | | | | | | | | | | | See go/usb-pd-slow-response-time for more information BRANCH=none BUG=b:112088135 TEST=CL stack on fleex and bobba consistently meet PD timing spec Change-Id: I9eabf8de8d866f5a0af7d1daba5ab585b418d26c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185729 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* tcpm: add higher priority tasks to handle TCPC intJett Rink2018-09-072-0/+61
| | | | | | | | | | | | | | | See go/usb-pd-slow-response-time for more information BRANCH=none BUG=b:112088135 TEST=CL stack on fleex and bobba consistently meet PD timing spec Also tested that PD firmare upgrade still works (uses PD suspend) on phaser. Change-Id: If789e79dcb9b69bc7ab5cb729189ca7b651b3a46 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185728
* tcpm: add TCPC RX circular buffer in ECJett Rink2018-09-0720-108/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The alert line for TCPC will stay asserted as long as there are RX messages for the TCPM (i.e. EC) to pull from the TCPC. We should clear all of the RX messages we know about during a single alert handling session. This CL can stand on its own, but it is a part of a CL stack that will tighten the critical section of time between received messages from the TCPC and sending follow up message out through the TCPC. See go/usb-pd-slow-response-time for more details. BRANCH=none BUG=b:112088135,b:112344286,b:111909282,b:112848644,b:113124761 BUG=b:113057273,b:112825261 TEST=Reduces reset issue in most cases for phaser, bobba. Does not seem to adversely affect state machine negotiation. Full CL stack consistently sends a REQUEST at 18ms after a SRC_CAP GoodCRC, which is well below the 24 ms threshold we need to be under for USB PD spec compliance. Also testing pd_suspend scenario manually and EC was responsive after port 1 suspend because of "bad behavior" Change-Id: I1654b46400e9881f2927a5f6d6ace589edd182de Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185727
* Add rules for building protocol buffers.Allen Webb2018-09-073-5/+16
| | | | | | | | | | | | | | | | | To facilitate using libprotobuf-mutator in fuzzing targets, rules for generating sources from proto files and compiling those to object files were added. BRANCH=none BUG=chromium:876582 TEST=rm -rf build && make -j buildfuzztests && ./build/host/cr50_fuzz/cr50_fuzz.exe (after cr50_fuzz.proto is added) Change-Id: Id645d0b60397bfeb71d60d601c4f65eefcbdf228 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1184106 Reviewed-by: Mattias Nissler <mnissler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* makefule.rules: Add cxx_to_o rule for building c++ files.Allen Webb2018-09-072-7/+17
| | | | | | | | | | | | | | | This adds a rule for building c++ object files to make it possible to use libprotobuf-mutator in fuzzing targets. BRANCH=none BUG=chromium:876582 TEST=make -j buildfuzztargets && ./build/host/cr50_fuzz/cr50_fuzz.exe Change-Id: I1355c313e47a1a83a599eb0f0b9142fefdf6de8b Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1183535 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50_fuzz: Add minimal fuzzer for pinweaver.Allen Webb2018-09-075-3/+148
| | | | | | | | | | | | | | | | | | | This adds a minimal pinweaver fuzzer as a foundation for further work. It will not be able to achieve good coverage because it doesn't have a proper description of the protocol, however it demonstrates that the prerequisites to build against dcrypto, nvmem_vars, and nvcounter are satisfied for the host board. CQ-DEPEND=CL:1183532 BRANCH=none BUG=chromium:876582 TEST=make -j buildfuzztests && ./build/host/cr50_fuzz/cr50_fuzz.exe Change-Id: I520d71c224d583c51dc3292dc051ee8de4a4116a Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1183534 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: flash and nvmem fixes for compatibility with the host board.Allen Webb2018-09-073-3/+11
| | | | | | | | | | | | | | | | | | This CL 1) Forces alignment of __host_flash so it can be used with nvcounter 2) Disables a compile time check for the host board that failes because the host board uses a variable to emulate flash memory. 3) Disables nvmem_vars console commands that are specific to a unit test for fuzzing targets. BRANCH=none BUG=chromium:876582 TEST=make -j buildfuzztests (with cr50_fuzz CL) Change-Id: Id6257132d8f2dd73ae07e796efd0da3df83b30d6 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1183533 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* host: Add dcrypto definitions that can be used by fuzzing targets.Allen Webb2018-09-0711-16/+199
| | | | | | | | | | | | | | | | These definitions provide the necessary dcrypto functionality for fuzzing pinweaver. They can be built out as needed to support further fuzzing. BRANCH=none BUG=chromium:876582 TEST=make -j buildfuzztests && ./build/host/cr50_fuzz/cr50_fuzz.exe (with the cr50_fuzz CL) Change-Id: I36ce874efab5dbc59825d126f6079b7b6d0da9ef Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1180573 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* fuzz: Hide conflicts with cstdlib and use clang++ for linking.Allen Webb2018-09-077-24/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | This creates a build target called libec.a by setting the visibility of functions that conflict with cstdlib to hidden. It then links those symbols locally into one large object file that makes up libec.a Fuzzing targets are linked against libec.a so that they can invoke ec functionality while depending on outside libraries that need cstdlib. When linking a particular object against cstdlib, to avoid conflicting function declarations put the following before any includes from the ec codebase: #define __stdlib_compat(...) The fuzzing targets are now linked using clang++, so that c++ libraries and objects can be used as part of the fuzzers. BRANCH=none BUG=chromium:876582 TEST=make -j buildfuzztests && ./build/host/host_command_fuzz/host_command_fuzz.exe Change-Id: Ifdfdc6a51c6ef23b4e192b013ca993bf48a4411b Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1180401 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tcpm:it83xx: GRL-USB-PD TDA2.1.2.2 BIST testRuibin Chang2018-09-0710-0/+45
| | | | | | | | | | | | | | | | | | | | In our design once enter BIST test data mode, Hw don't interrupt Fw due to any Rx received packet. But when port partner re-connect in this mode, it will cause that our pd port doesn't respond packet which port partner transmits. When port partner disconnects, so we need to reset our pd port protocol layer and PHY to leave BIST test data mode and let Hw can interrupt Fw. With this modify it can pass GRL-USB-PD compliance TDA2.1.2.2 test item. BUG=b:112602596 BRANCH=none TEST=GRL-USB-PD compliance test. Change-Id: I30526b5d796e3eabc9af2f524071c98bb0ef5abf Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1170718 Reviewed-by: Jett Rink <jettrink@chromium.org>
* rammus: add CONFIG_BOARD_VERSION_CBI to enable board version queryZhuohao Lee2018-09-071-0/+1
| | | | | | | | | | | | | | | The board version is queried from the EEPROM. This patch adds CONFIG_BOARD_VERSION_CBI to enable the board version query via host command. BUG=none BRANCH=master TEST='mosys platform version' returns the correct value Change-Id: I87a591a00a4335031ee38eb3c0553f1be8c3b676 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1201222 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Liara: Add supported batteriesJonathan Brandmeyer2018-09-053-6/+79
| | | | | | | | | | | | | | These are two of the three batteries for Liara. Retain the Grunt reference design battery for testing purposes only. BUG=b:113823864 TEST=buildall BRANCH=none Change-Id: Ibfdfa08298ec142504b24477746ebb87aebc913c Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1204696 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: Decide erase size based on ro/rw region sizeFurquan Shaikh2018-09-055-10/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change updates the erase operation in npcx chip to use 64k/32k/4k block erase depending upon the alignment of CONFIG_RO_SIZE. This helps reduce the EC SW sync time from ~9.5 seconds to ~5.4 seconds on NPCX7. Ideally, we would want to check the offset and size of region to be erased dynamically and decide which erase operation to use. However, common flash code checks against CONFIG_FLASH_ERASE_SIZE to ensure that the area being erased is aligned to that size. Thus, even if we add dynamic erase at chip level, it isn't going to help. This change also updates CONFIG_FLASH_BANK_SIZE to be the same as CONFIG_FLASH_ERASE_SIZE since it is checked by common code. I am honestly not sure why the CONFIG_FLASH_BANK_SIZE is tightly coupled with CONFIG_FLASH_ERASE_SIZE. But, based on the usage, it seems to be a safe change. On the other hand, changing CONFIG_FLASH_BANK_SIZE helps reduce the write time as well, thus overall helping with the EC SW Sync time. Please see go/cros-npcx7-ec-sw-sync for more details. BUG=b:113530328 BRANCH=nocturne TEST=Verified that EC SW sync time goes down from 9.5 seconds to 5.4 seconds. Change-Id: I5908eeeb3e4207a27abe804db8eb9d39ef9d73c4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1195598 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* grunt: Enable CONFIG_I2C_BUS_MAY_BE_UNPOWEREDEdward Hill2018-09-052-1/+11
| | | | | | | | | | | | | | | | Enable CONFIG_I2C_BUS_MAY_BE_UNPOWERED option to avoid attempting to unwedge the I2C bus when sensor power is off in S5 (and G3). This will avoid the unwedge causing a watchdog reset. BUG=b:112553833 BRANCH=none TEST=Verify that board_is_i2c_port_powered() is called. Change-Id: I4e37ab17cba0d947bc8840b507a191541894d36c Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1186067 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* bip: use PS8751 HPD status function for C1Jett Rink2018-09-051-1/+1
| | | | | | | | | | | | | | | | | | We were using the incorrect HPD status update function since HPD is a funciton of the MUX with is the PS8751 for C1 on bip (and similar octopus variants) BRANCH=none BUG=b:110937880 TEST=Verified by connecting DP monitor at boot; Verified plug / unplug of DP cable works; Change-Id: I2221e38a80f4b789647214ca8da73927a5a5e93f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200063 Commit-Ready: Gaggery Tsai <gaggery.tsai@intel.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* ss-mux: update semantics for TCPC/MUX only used as MUXJett Rink2018-09-0518-176/+181
| | | | | | | | | | | | | | | | | | | | | | | | This converts the compile time option of CONFIG_USB_PD_TCPM_TCPCI_MUX_ONLY into a runtime option to better support draggon egg designs and reduce CONFIG complexity in general. Introduce new mux_read/write to read from tcpc_config_t or mux driver depending on new flag setting. Audited all mux drivers for any use of tcpc_read/write and updated to mux_read/write. BRANCH=none BUG=b:110937880 TEST=On Bip with CL stack: Verified by connecting DP monitor at boot; Verified plug / unplug of DP cable works; Change-Id: I968893b886ff0ccc4074beae5ec42973814ae77c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200062 Commit-Ready: Gaggery Tsai <gaggery.tsai@intel.corp-partner.google.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: Make SN data available through vNVRAM.Louis Collard2018-09-051-1/+14
| | | | | | | | | | | | | Defines a new virtual NV index, 0x13fff01 for SN data stored in INFO1. BUG=b:111195266 TEST=tested locally on soraka BRANCH=none Change-Id: I7a057938a14effe9a5bd93b06a3450aa823d9ff5 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1187860 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: Add commands to get/set serial number bits.Louis Collard2018-09-0512-31/+416
| | | | | | | | | | | | | | | | | | | | | Allocates 16 bytes of INFO1 space, in the 'board' section, and after the current Board ID data, to store the serial number data for use by zero-touch enrollment. Adds a console command to read / set this data. Adds TPM vendor commands to set initial sn data, and update it during RMA. CQ-DEPEND=CL:*657450 BUG=b:111195266 TEST=tested locally on soraka BRANCH=none Change-Id: I752aefad9654742b7719156202f29d635d2306df Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1127574 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* flash_ec: add rammus boardZhuohao Lee2018-09-051-0/+2
| | | | | | | | | | | | | This patch adds rammus to flash_ec script. BUG=b:111579280 BRANCH=master TEST=flash_ec --board rammus --image ec.bin Change-Id: I30193835d1d3bb8097751ed0de0e2eb12264dd51 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1149946 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* driver: accel: Prevent ODR from crashing the ECGwendal Grignou2018-09-053-32/+21
| | | | | | | | | | | | | | | | | | For accelerometers which are interrupt driven, setting ODR too high may exhaust the EC and trigger the watchdog timer. Use config variable to verify the ODR requested is not too big. Return an error when setting unsupported parameters. BUG=b:112672627 BRANCH=nocturne,eve TEST=Without this change, ectool motionsense odr 0 500000 crashes the EC Now, it returns EC result 3 (INVALID_PARAM) Change-Id: I64a4e522dcad450d619a7fc48a1330479f1cf81f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200068 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* driver: lsm6dsm: Allow roundup to work below 13HzGwendal Grignou2018-09-051-1/+1
| | | | | | | | | | | | | Recalculate ODR properly after rounding up the requested rate. BUG=b:112179405 TEST=Check ODR is set properly BRANCH=none Change-Id: I3f5abd5a1720f21d666cd3029000c2cec257c6f1 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200067 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* iteflash : enable global resetDonald Huang2018-09-051-8/+16
| | | | | | | | | | | | | | | | | | | | This patch let servo can perform a cold reset after flashing. Add reset flag after erase. BUG=none BRANCH=none TEST=1.make -j BOARD=reef_it8320 2.sudo servod -b reef & 3.~/trunk/src/platform/ec/util/flash_ec --board=reef_it8320 Change-Id: I35620f6a48edce16e028888beed413a8f32a7d8b Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1174191 Commit-Ready: Donald Huang <cguwinds@gmail.com> Tested-by: Donald Huang <cguwinds@gmail.com> Tested-by: Jett Rink <jettrink@chromium.org> Tested-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ICL: Modify force_shutdown to meet PCH timing requirementsScott Collyer2018-09-051-3/+10
| | | | | | | | | | | | | | | | | | Time between RSMRST going low and the _A rails dropping 5% must be > 400 ns. To meet this timing set the PCH pass through low at beginning of chipset_force_shutdown. Similarly, set EC_PCH_DSW_PWROK low to meet its timing requirement relative to _A rails dropping 5%. BUG=b:112170058 BRANCH=none TEST=Verified that timing meets the specifications. Change-Id: I88573a4b926f5804d1a0df5702078eb32a6d0221 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1179142 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Add support to Type C port 1Scott Collyer2018-09-046-4/+53
| | | | | | | | | | | | | | | | | | | | Port 1 uses the ITE builtin TCPC, Silergy SYV682A PPC, and the parade PS8818 redriver. Port 1 is intended to use the EC ADC to detect VBUS, but port 0 and 2 require different methods. The Silergy can detect VBUS (not safe0V or safe5v), so currently the PPC is being used to detect VBUS. BUG=b:111281797 BRANCH=none TEST=Verified that port 1 can attach as both a sink or source. Change-Id: Iad0c3d509961c836cd55f77cd5f276c1a3e5aacf Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1159829 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ppc: Add driver for Silergy SYV682x PPCScott Collyer2018-09-044-0/+396
| | | | | | | | | | | | | | | | | | | Initial version of driver for Silergy SYV682x PPC. This version of the driver does not support the Alert line from the SYV682x. Alert will need to be support for FRS and to detect OVP or OC cases that cause the power path to be disabled. BUG=b:111281797 BRANCH=none TEST=Tested on DragonEgg and verified that can attach as both sink or source port. Change-Id: Ia0450db666b50f90d6e074024bd9b89ea7d50ed6 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1159828 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* hwtimer: Tidy up and clarify some hw_clock commentsSimon Glass2018-09-041-3/+20
| | | | | | | | | | | | | From what I can tell the counter has to tick over at the rate of 1MHz. Update the comments to make that clear. BUG=chromium:876737 BRANCH=none TEST= make buildall -j50 Change-Id: Ib04731c10a68c544973b810cf70ce9ffba556b89 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185230
* chip/npcx: Tidy up comments for init_hw_timer()Simon Glass2018-09-042-2/+9
| | | | | | | | | | | | | | The comments suggest that this function only operates with ITIM16 timers but it seems to support ITIM32 as well. Also it allows selecting the clock source. Update the comments, hopefully making them correct. BUG=chromium:876737 BRANCH=none TEST= make buildall -j50 Change-Id: Ic4ec2457cde2de55d51371f781d49bae80365989 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185225
* octopus: consolidate identical definesJett Rink2018-09-047-24/+9
| | | | | | | | | | | | | | All of the octopus board define the table mode option the same, so move them into baseboard. BRANCH=none BUG=none TEST=fleex still works Change-Id: Ibed874a609a2e5947d7aee39f915dc3046a0cc19 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1204700 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* octopus: enabled DPTF device orientationJett Rink2018-09-046-13/+2
| | | | | | | | | | | | | | | | | | | | | | | All octopus boards should have this enabled by now. We are consolidating this option in octopus baseboard. This turns on DPTF on: - Fleex This turns on DPTP_DEVICE_ORIENTATION on: - Bip - Bobba - Fleex BRANCH=none BUG=b:113348027 TEST=fleex has tablet mode icon Change-Id: I0d25895785c6a8fcce25b3b6bf587b6030119045 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1204699 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* bip: add tablet mode for consistencyJett Rink2018-09-043-0/+8
| | | | | | | | | | | | | | | Hardware has supported tablet mode for a while, add firmware support for tablet mode. BRANCH=none BUG=none TEST=on bip, can use magnet to enter tablet mode. Change-Id: I97202f1638732c9dcae641d3cf834a8d08b4a134 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1204698 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* cr50: fix sps driver sync problemsVadim Bendebury2018-09-043-90/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPM SPI hardware flow control mechanism allows the slave to stall the master until slave is ready to receive more data or has prepared data to return to the master. While stalling, the slave keeps sending zeros in the LSB of the bytes on the MISO line until it is ready to proceed. As implemented before this patch this presents a challenge when processing write transactions: by looking at the SPI frame header the Cr50 detects that master intends to write, removes the stall bit, and then tries to determine how many bytes are already there in the receive buffer (those extra bytes were sent while Cr50 was stalling the master), so that it can discard the extra bytes and know exactly where in the buffer the actual data will start once stalling condition is removed. To make this determination the code is looking at the controller's RX FIFO write pointer. It turns out that this pointer change is happening slower with slower SPI bus clocking, and this causes occasional errors in detecting the boundary in the receive buffer at slower SPI clock rates. Come to think of it, all this complexity is unnecessary in the first place: the master will finish transmitting of the write transaction after stall is removed and all required data bytes have been transferred and then remove the CS. At this point the Cr50 can look at the received data, which would consist of a 4 byte header, variable number of bytes sent while stalling was active, and then the rest of the SPI frame. The number of data bytes in the SPI frame is in fact included in the 4 byte header. So, all there is to do is to pass upstack these tail bytes of the received frame (the register address these bytes are written into is derived from the SPI frame header). This patch implements the new scheme and cleans up the low level driver, namely removes a now unused accessor function and ediits a few comments. BRANCH=cr50, cr50-mp BUG=b:113082214 TEST=modified Cr50 code to add a 32 bit scratch register the master could write and read. Modified Scarlet AP firmware to keep writing ever incrementing value to this register and read it back. Before this fix when clocking at 300 KHz this would fail after second or third write attempt, with the fix there is no problems for thousands of transactions on both 300 KHz and 1.5 MHz clocks. Change-Id: I845d2d18dc054e2a0ca2c8afd9f62bec37ad6ad9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194621 Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* Add CONFIG_GPIO_INIT_POWER_ON_DELAY_MSEdward Hill2018-09-045-3/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | On power on, H1 releases the EC from reset but then quickly asserts and releases the reset a second time (so that the EC comes out of reset the second time after the SPI buffers have been configured by H1). Add a delay so the EC can wait for this second reset before configuring GPIO outputs, to avoid extra output toggles. Unfortunate the timer is not set up by the time gpio_pre_init() is called, so we add a new __hw_early_init_hwtimer() function to set it up so that mdelay() worked. Without that, mdelay() hangs. BUG=b:72132384 BRANCH=none TEST=GPIO_OUT_HIGH has a single rising edge after power on (before it would rise-fall-rise) Check that mdelay(10) delays for about 10ms (actually perhaps a little more using a scope line on KB_BL_EN Change-Id: Iadc96fceb190e43ac0758f291f22e03aef81c379 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/879353 Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Phaser: support quick charge function of batteryHuangGe Haha2018-09-041-0/+44
| | | | | | | | | | | | | | | | | It uses normal mode of battery in S0 state and quick charge mode is used in other states. BUG=b:77306829 BRANCH=none TEST=The maximum charging current is about 2000mA in S0 state and in other states is about 3500mA. Change-Id: I975fc51af6f15445dabea246c8beaf41547caa47 Reviewed-on: https://chromium-review.googlesource.com/1188206 Commit-Ready: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Tested-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cbi: fail set command early if WP is assertedJett Rink2018-09-041-5/+12
| | | | | | | | | | | | | | | | We are changing the in-memory version of CBI but cannot write it out to the EEPROM. This causes weird behavior when reading the CBI setting out again because it does not match the EEPROM values BRANCH=none BUG=b:113577856 TEST=Values aren't written to CBI in-memory when WP is asserted. Change-Id: Ie74fd3e47b3fabe6436e2787931b7238a112ec94 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1196846 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* flash_ec: Look for npcx_monitor.bin in the same dir as ec.binRaul E Rangel2018-09-041-0/+10
| | | | | | | | | | | | | | | | crrev.com/1194646 makes it so chromeos-ec installs the monitor.bin as part of the build. The script just needs to be updated to use it. This will allow using flash_ec for downloaded firmware or firmware built using emerge chromeos-ec. BUG=b:113288489 BRANCH=none TEST=emerge-grunt chromeos-ec && flash_ec --board=grunt Change-Id: Ie92b75a750dbf8ce4e01eafec7a01479915b1270 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194354 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tablet-mode: add disable functionJett Rink2018-09-042-0/+26
| | | | | | | | | | | | | | | | For clamshell SKUs, we do not want to ever enable tablet mode. Since the firmware is shared between convertibles and clamshells, we need to compile in the tablet mode switch support but have a way to disable it at run-time BRANCH=none BUG=b:113837268 TEST=verify that a clamshell SKU does not go into tablet mode when a free magnet gets close to the sensor (with CL stack) Change-Id: Icc0f72253014f05598d658601eb8437bfe0ff488 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1204451
* Bobba: Set motion_sensor_count to 0 for clamshellsTino Liu2018-09-041-2/+2
| | | | | | | | | | | | | | | | Clamshell Bobba has no motion sensors, motion_sensor_count should be 0. BUG=none BRANCH=none TEST=make buildall Change-Id: I59b0154ecad636e4cdfdbaca2bffe33d67e1df13 Signed-off-by: Tino Liu <tino.liu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1196566 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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