summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
...
* Boten initial EC imagePeichao Wang2020-06-048-0/+1329
| | | | | | | | | | | | | | | | | The starting point for the Boten EC image copied from waddledee BUG=b:158023819 BRANCH=none TEST=make BOARD=boten Change-Id: Ie06c2b54b3b8c873c0b302561f5f86a9d8e8939a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227769 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Tested-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Auto-Submit: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Commit-Queue: Marco Chen <marcochen@chromium.org>
* ec: Minor cleanup of magic number commonly used in STM32 USBBrian J. Nemec2020-06-045-4/+8
| | | | | | | | | | | | | | | | | Minor cleanup of a commonly used magic number in the STM32 USB interface. BUG=none BRANCH=none TEST=Builds Signed-off-by: Brian Nemec <bnemec@chromium.org> Change-Id: I2c0b7947810aae651e452db42ac27221ab19b99b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224763 Tested-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org>
* TCMPv2: Handle DP mode exit.Andrew McRae2020-06-041-2/+34
| | | | | | | | | | | | | | | | | When DisplayPort alt mode is in effect, and the system is powered down, send a Mode exit message to cleanly reset the mode of the partner. BUG=b:156306710 TEST=Shutdown and power up with type-C monitor connected. BRANCH=none Signed-off-by: Andrew McRae <amcrae@google.com> Change-Id: I656eeeeaeb517f2d5f49281bdd26e91a5fb6fc6d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2219792 Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Bobba: add PPC syv682x configDavid Huang2020-06-045-6/+44
| | | | | | | | | | | | | Supoprt PPC SYV682X on bobba. BUG=b:154772847, b:156711950 BRANCH=octopus TEST=Check usb dongle/typec adapter worked properly in any power state. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I1b87d3de4a749005b5bf4c1d42cb4bf1fa61f1ec Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227772 Reviewed-by: Marco Chen <marcochen@chromium.org>
* Kaisa: Reset TCPC after system reset.Andrew McRae2020-06-041-3/+7
| | | | | | | | | | | | | | | Reset the TCPC even in RW if there has been a system reset or after power on. BUG=b:155145509 TEST=Confirm on Kaisa that type-C power replug works. BRANCH=none Change-Id: Ib9fc1298cf165aed2ee386a7f158ee73ba15eb37 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227788 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* chip/mt8192_scp: support UARTTzung-Bi Shih2020-06-044-8/+262
| | | | | | | | | | | | BRANCH=none BUG=b:146213943 BUG=b:156221696 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I95a547b9d1763dc7faa6d7a1c18cf9ae675bae39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2198821 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* chip/mt8192_scp: support INTCTzung-Bi Shih2020-06-043-9/+435
| | | | | | | | | | | | BRANCH=none BUG=b:146213943 BUG=b:156223049 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I1916d12bf92154853c90bf06050587ad1e73a093 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2198820 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: remove return valuesTzung-Bi Shih2020-06-043-21/+9
| | | | | | | | | | | | | | | | | | Return values of chip_enable_irq(), chip_disable_irq(), and chip_clear_pending_irq() are not using. Removes them. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ic7e3e80483f76f35bfe7781ddea48515ab8e3361 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227778 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: add error handling for chip_get_ec_int()Tzung-Bi Shih2020-06-042-10/+21
| | | | | | | | | | | | | | | | | | chip_get_ec_int() returns -1 if it cannot find the corresponding interrupt source. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I5021ed80f50a99b15d9b9a90a9181077f63bd4be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227777 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* nightfury: enable FIFO interrupt for lid accelInno.Park2020-06-043-4/+4
| | | | | | | | | | | | | BUG=b:154299214 BRANCH=none TEST=build EC, flash 'ec.bin' and boot device. run "watch -n .1 'ectool motionsense; ectool gpioget LID_ACCEL_INT_L'" Change-Id: I6d5fc7cd196f71e49cecf6cf0172666b087281e5 Signed-off-by: Inno.Park <ih.yoo.park@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2219788 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Bob Moragues <moragues@chromium.org>
* driver: lis2ds: add a setting if interrupt active low or notInno.Park2020-06-041-3/+12
| | | | | | | | | | | | | | | | H_LACTIVE bit setting has been added to support both active high or low interrupt. And return value in lis2ds_load_fifo() also has been corrected. It returns a byte count, seen as if an error code and never used. BUG=b:154299214 BRANCH=none TEST=build EC and flash 'ec.bin'. boot device and check the interrupt line high or low Change-Id: I71bb0ecd99ce1b5319c10238980098dfa001f4c1 Signed-off-by: Inno.Park <ih.yoo.park@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2217608 Reviewed-by: Bob Moragues <moragues@chromium.org>
* test: Add script for running unit tests on deviceTom Hughes2020-06-041-0/+346
| | | | | | | | | | | | | | | | | | This is still a prototype, but is functional and useful for verifying all the unit tests pass on device. BRANCH=none BUG=b:151105339 TEST=With dragonclaw v0.2 connected to Segger J-Trace and servo micro: ./test/run_device_tests.py TEST=With dragonclaw v0.2 connected to Segger J-Trace and servo micro: ./test/run_device_tests.py -t mpu Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Iab39c092b6637544ac37ca32a0b0c94274f05868 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2212623 Commit-Queue: Yicheng Li <yichengli@chromium.org> Reviewed-by: Yicheng Li <yichengli@chromium.org>
* raa489000: Add support for DVCAseda Aboagye2020-06-042-0/+135
| | | | | | | | | | | | | | | | | | | | | This commit adds support for DVC, Dynamic Voltage Compensation, which is supported by the RAA4890000. In DVC mode, the battery can be charged through an auxiliary RAA489000 operating as a Voltage Regulator. DVC mode is used to autonomously fine tune the charge current without significant involvement from the system. BUG=b:155225932 BRANCH=None TEST=Build and flash waddledoo, verify that battery can be charged from the sub-board. TEST=`make -j buildall` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ie6af4fa4abcda2c8695919e30d231d812d7171b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2191299 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* OCPC: charger: Add support for VSYS compensationAseda Aboagye2020-06-043-1/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | Some charger ICs can compensate VSYS for losses across the board when charging from an auxiliary charger in an OCPC scheme. This commit adds that support to the common charger and OCPC framework such that it can be leveraged. Charger ICs which can dynamically compensate and don't need continuous adjustments should return EC_SUCCESS as the PID won't be needed. Other chargers should return EC_ERROR_UNIMPLEMENTED since they require continuous adjustments. BUG=b:147440290,b:148980016 BRANCH=None TEST=With driver changes made for RAA48900, build and flash on waddledoo, verify that charging from the sub board works on board revs 0 and 1. TEST=`make -j buildall` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ie6fb27260b2d6e040dbfdc0aaa5b64b52173037c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2191298 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* waddledoo: Enable OCPCAseda Aboagye2020-06-042-0/+28
| | | | | | | | | | | | | | | | | | This commit enables OCPC for waddledoo. BUG=b:148980016 BRANCH=None TEST=Build and flash on waddledoo, verify that I can charge the battery from the sub-board at desired current in G3. Additionally, verify that adapter is nearly maxed out when system is running in S0 and battery is charging heavily. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I5c0732b21760980cc3bb3f4c6006fd57e48cfc21 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2135965 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* zork: enable CONFIG_USB_PD_DISCHARGE_TCPCDenis Brockus2020-06-031-0/+1
| | | | | | | | | | | | | | | | | | | Add TCPC Vbus Forced Discharge to bring us to Safe0V faster when we should be disconnecting BUG=b:157755939 BRANCH=none TEST=look at Vbus after PR Swap for speed to Safe0V Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Idfc5771eb84a56ecab0879dd0a352a48c4c767ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228088 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* TCPMv2: Aborted PR Swap should not re-enable AutoDischargeDenis Brockus2020-06-034-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a recovery path exit a TCPCI I2C FAULT occurs when we set the CC lines to open/open if AutoDischargeDisconnect is currently enabled. The TCPCI I2C FAULT is not a status of the I2C interface but rather a status of the last TCPCI I2C write performed with regards to the current state/settings of the TCPCI. This is usually caused when AutoDischargeDisconnect is enabled/disabled when it should not be. This change will make sure this path will not re-enable and that entering the recovery path will make sure AutoDischarge is disabled. We will wait to re-enable until the TC state machine is restarted. BUG=b:157755939 BRANCH=none TEST=ThinkPad Dock G2 attach should not cause FAULT-0x01 Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: If70ccd90b045949e54c131512d1fb294c61dd1dd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2223722 Tested-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org>
* bc12/pi3usb9281: Fix max ilim for SDPAseda Aboagye2020-06-031-1/+1
| | | | | | | | | | | | | | | | | | | Per the USB Battery Charging 1.2 specification Section 1.4.13 "Standard Downstream Port", a standard downstream port can support a maximum of 500mA. This commit fixes a bug where we were assuming we could pull a maximum of 1A from an SDP. BUG=b:158094711 BRANCH=nami,rammus,poppy,glados,oak TEST=make -j buildall Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I9875743c2c3d570845f1171f34d91fc8967164b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228393 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* lisdw12: add missing header fileTing Shen2020-06-031-0/+1
| | | | | | | | | | | | | | | | lis2dw12_load_fifo() references motion_sense_fifo_stage_data() and motion_sense_fifo_commit_data. Add the required header file. BUG=none TEST=compile with CONFIG_ACCEL_LIS2DW_AS_BASE enabled BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I8bd619a5f85484da641b7a504b6425bd30d4fb8b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228078 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* asurada: enable base motion sensor interruptTing Shen2020-06-032-1/+5
| | | | | | | | | | | | | BUG=b:150341271 TEST=`accelinfo on`, see sensor data is updating BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ib2918d79dd319a82ce3ce74d3214aacb4c702f0c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228409 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* usb_pd_protocol: Don't reset msg_id on ACCEPT when in SOFT_RESET statePatryk Duda2020-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DUT is running new TCPMv2 stack. PD3.0 enabled When ServoV4 sends PD_CTRL_SOFT_RESET message to DUT it assigns 0 to msg_id because PD_CTRL_SOFT_RESET always has msg_id equal to 0. DUT performs soft reset and responds with PD_CTRL_ACCEPT message. ServoV4 receives PD_CTRL_ACCEPT and calls execute_soft_reset() which again resets msg_id to 0. Next message sent by ServoV4 is dropped by DUT due to msg_id duplication. This issue was found by running firmware_PDResetSoft test against nocturne with TCPMv2/PD3.0 stack. Test was failing after power swap (DUT as SRC) when soft reset was initiated by ServoV4. When DUT was SNK soft reset from ServoV4 was passing, however debugging showed that it was going to hard reset due to negotiation failure, eg. pd 1 soft C1 st33 SOFT_RESET C1 CTRL[13]>1 C1 RECV 0063/0 C1 st18 SRC_DISCOVERY C1 Soft Rst C1 srcCAP>1 C1 st19 SRC_NEGOCIATE C1 st34 HARD_RESET_SEND C1 st35 HARD_RESET_EXECUTE C1 HARD RST TX C1 st16 SRC_HARD_RESET_RECOVER BRANCH=none BUG=b/157600843 TEST=Flash nocturne with EC compiled with TCPMv2/PD3.0 support. Flash ServoV4 with this fix. Run firmware_PDResetSoft, test should pass. Check if ServoV4 is not entering hard reset states Change-Id: Ifb7c031969eb48f740e16117de72ba8bdd36fc0b Signed-off-by: Patryk Duda <pdk@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224804 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* vilboz: Initial EC imageLu Zhang2020-06-038-0/+843
| | | | | | | | | | | | | | | | | | Create the initial EC image for the vilboz variant by copying the dalboz reference board EC files into a new directory named for the variant. (Auto-Generated by create_initial_ec_image.sh version 1.0.2). BUG=b:157499341 BRANCH=none TEST=make BOARD=vilboz Signed-off-by: Lu Zhang <lu.zhang@bitland.corp-partner.google.com> Change-Id: I511548fb432a0eb318b5f0281205c2c28ee1c7ae Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224680 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* tcpci: use the correct register to configure extended alertsPeter Marheine2020-06-031-1/+1
| | | | | | | | | | | | | | | | | The extended alert mask should be written to the mask register, not the alert status register. Writing to the wrong register clears any active alerts for sink FRS and left the extended alert mask at the default of all interrupts enabled. BUG=b:146393213 TEST=Still builds BRANCH=None Change-Id: I1938e36b3278565f620cd5f6efbaf9f36af10852 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227771 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org>
* TCPCI: acknowledge extended alertsPeter Marheine2020-06-031-1/+6
| | | | | | | | | | | | | | | | TCPCI alerts were cleared when handled, but not for alerts flagged in the ALERT_EXTENDED register. Clear the extended alerts first, then ALERT as specified in TCPCI specification rev 2.0 v1.0 section 4.4.7. BUG=b:146393213 TEST=trembyle now clears ALERT_EXTENDED when servicing FRS alerts BRANCH=None Change-Id: I7b45e415048ebcb7227d9f5c7f012ca8288dceac Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227770 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org>
* Zork: Switch PS8743 from IOEX_USB_C1_DATA_EN to I2CEdward Hill2020-06-035-79/+23
| | | | | | | | | | | | | | | | | Align all Zork devices on using I2C control of PS8743 mux mode, and stop using IOEX_USB_C1_DATA_EN signal/pin. This matches what we were already doing for Dalboz, and gives power savings in both S0 and S3 when nothing is plugged in and mux is set to none. BUG=b:157951317 BRANCH=none TEST=external display and i2ctrace on ezkinil Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Id1c8b172a99bb25bed8b57e90686d933447432f2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227589 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* berknip: add SMP battery configurationZick Wei2020-06-032-19/+20
| | | | | | | | | | | | | | BUG=b:157950071 BRANCH=none TEST=test berknip can power on with battery only. Battery can charge, discharge, cut-off command work normally. Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: Ib8cbf7badca81103c7707dbb24f4f43f5d09d351 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2206938 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* berknip: add pi3usb221 driverZick Wei2020-06-032-0/+33
| | | | | | | | | | | | | | | | Add pi3usb221 support on berknip, this chip use as SBU mux of usb c0 port. BUG=b:148757952 BRANCH=none TEST=verify USB type C monitor can work on both side cable on USBC0 port. Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: Ie800682fe12db3d2df1eb2da40fe9c39c996a580 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2216138 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* morphius: Fix PS/2 device not work after sysjumpZick Wei2020-06-031-2/+2
| | | | | | | | | | | | | | | | | This CL fix PS/2 device not work when EC jump from RO to RW. BUG=b:157206963 BRANCH=none TEST=enable software sync and press refresh+power button, check PS/2 device can work after boot into OS. Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: I22584b040b5f3a76089620948f686971e61c2c20 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224687 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* Zork: Power off USB-A1 retimer in S3Edward Hill2020-06-032-4/+4
| | | | | | | | | | | | | | Fix from CL:2209659 for Trembyle is also needed for Dalboz and Ezkinil. BUG=b:156696798 BRANCH=none TEST=USB-A still works Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Id62bb9668042642eb3b0a64798a2aa4c763a604d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227590 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* TCPMv2: CPU wake from suspend should not change alt modeAndrew McRae2020-06-031-13/+10
| | | | | | | | | | | | | | | | | Handle the CPU wake from suspend by not overriding existing alt mode settings. BUG=b:157708283 TEST=Use powerd_dbus_suspend to suspend DUT, check wake-up will work. BRANCH=none Signed-off-by: Andrew McRae <amcrae@google.com> Change-Id: Ia56b57c3a46cb5568ed76c2aa20e7ad48a9b8ea0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2219799 Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* chip/stm32: Don't reset the backup domain when initializing clockYicheng Li2020-06-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | For the STM32F4 chip family, this software reset of the backup domain causes the RTC backup registers to be reset, which causes all backup data to be lost. The reset flag was not impacted because it's copied out before this reset. BRANCH=none BUG=b:157059753 TEST=make -j BOARD=bloonchipper test-scratchpad On console: > runtest => PASS > reboot > runtest => FAIL, which is CORRECT Signed-off-by: Yicheng Li <yichengli@chromium.org> Change-Id: I85777b7d8a99561198d0b9dc1f795b8f8f6e26c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226955 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Tom Hughes <tomhughes@chromium.org>
* BB retimer: Add 'vPro_Dock_Detect/DP_Overdrive' bitAyushee2020-06-033-6/+23
| | | | | | | | | | | | | | | | | For DFP, if SOP discover SVID supports Thunderbolt-Compat mode then, vPro_Dock_Detect/DP_Overdrive is set according to discover mode SOP response. Ref: Burnside Bridge spec Table 13: Connection state register BUG=b:152544514 BRANCH=None TEST=make buildall -j Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I7a53396725052a4dfa12e934919c2e1d601c8949 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2153825 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* chip/mt8192_scp: add basic system settingsTzung-Bi Shih2020-06-032-0/+40
| | | | | | | | | | | | | | Settings include: - default memmap BRANCH=none BUG=b:146213943 TEST=make BOARD=asurada_scp Change-Id: I581a22527df579a815f895c6ba370e2e8bc0397d Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2198819 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* asurada_scp: add dummy board implementationsTzung-Bi Shih2020-06-035-0/+91
| | | | | | | | | | | BRANCH=none BUG=b:146213943 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I2b3a93777fe912a6a6793963d331ebc781218f4e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2198818 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* chip/mt8192_scp: add dummy chip implementationsTzung-Bi Shih2020-06-039-0/+293
| | | | | | | | | | | BRANCH=none BUG=b:146213943 TEST=make buildall Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ib5da01056c5624eae1efc14e64638c052f74c50c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2198817 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: add in_soft_interrupt_context()Tzung-Bi Shih2020-06-032-0/+11
| | | | | | | | | | | | | | BRANCH=none BUG=b:146213943 BUG=b:156218912 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Change-Id: If8df1fb768ea9c83f025d8bd17010481389d7aa1 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2217596 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* test: Pass command line arguments to scratchpad unit testYicheng Li2020-06-021-1/+1
| | | | | | | | | | | | | | | Now that the main function of test files expects command line arguments, pass arguments to scratchpad test so that it can build. BRANCH=none BUG=none TEST=make -j BOARD=bloonchipper test-scratchpad Signed-off-by: Yicheng Li <yichengli@chromium.org> Change-Id: I042d91734b3cd46b9e14cfd647487b300a8f07ea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226521 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Tom Hughes <tomhughes@chromium.org>
* tcpci: Added some common tcpci debug helpersDenis Brockus2020-06-021-6/+109
| | | | | | | | | | | | | | | | | | Added some compile time optional debug functions (by default they are disabled). BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I09511b596da30aa122a92ff3437cac8becbbba61 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2223724 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* servo_v4p1: Initial checkin of firmwareSam Hurst2020-06-025-0/+586
| | | | | | | | | | | | | | | | | | | | | | | The flash is partitioned as follows: 96K for RO 40K for RW The bulk of the code is placed in RO and RW is used for software updates. This initial checkin implements the following functionality: 1) Software updates over servo_updater BRANCH=none BUG=b:146793000 BUG=b:141180763 TEST=make -j buildall Change-Id: I68f94c5110210c134e7ff7212d6ccc0854413457 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2107729 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* volteer: add support for USB4 Gen3Keith Short2020-06-023-12/+39
| | | | | | | | | | | | | | | | | | Latest Volteer motherboards and USB4 daughterboards support USB4 Gen3 speeds. Create new USB daughterboard type in CBI FW_CONFIG to support this configuration. BUG=b:157483704 BRANCH=none TEST=make buildall TEST=Set USB DB type to 3 (USB4_GEN3), verify TBT cable speed is reported as Gen3 to the kernel extcon-tcss-cros-ec driver. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I7873db70436cb9500387620a0e800c3ee79a384d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2223912 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* OCPC: Configure VSYS via secondary charger ICAseda Aboagye2020-06-025-5/+399
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the bulk of the work in getting OCPC functional. Since the secondary charger IC cannot directly sense the current entering the battery, with OCPC, we recruit the EC to do this work instead. Essentially, VSYS needs to be chosen such that we induce the desired current in the battery while also accounting for losses in the system between the output of the secondary charger IC and the battery. To start, a board needs to define the following CONFIG_* option: CONFIG_OCPC_DEF_RBATT_MOHMS This should be at least the R_ds(on) resistance of the BFET and the series sense resistance. The board should also define CONFIG_OCPC. With the combined system resistance, we can calculate the VSYS required to induce the desired current. However, we will also use a PID control loop to help drive our VSYS target to what it should actually be accounting for our error. The PID constants were found by tuning on a waddledoo board. It remains to be seen whether or not these will differ on a board to board basis. BUG=b:148980016,b:147440290 BRANCH=None TEST=Enable on waddledoo, verify that we can charge the battery from the sub-board. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Icd323546836fe41fa1fcc7c3b6071d822663ed05 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2135964 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* servo_updater: Updates the Servo V4.1 nameBrian J. Nemec2020-06-024-3/+5
| | | | | | | | | | | | | | | | | | | | | | Updates the Servo V4.1 name from 'servo_v41' to 'servo_v4p1' and the corresponding files and fields. As the VID:PID is used to identify the device, no other changes are required. BUG=b:157059356 BRANCH=servod TEST=Updated the ServoV4.1 from 'servo_v41_v2.0.3735+440cf71e0' to 'servo_v4p1_v2.0.4232-514cb4e92' to verify the servo_updater supports renames. TEST=Verified servo_v4p1 manually: Validated console, firmware update, and servod can connect to the device. Signed-off-by: Brian Nemec <bnemec@chromium.org> Depends-On: Ia05134179fab4ff118355ba9b3b1b92cdf0748f2 Change-Id: Ie470469bf9115bbfef14a08c02b156dcd5aed849 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2219124 Tested-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* asurada: fix incorrect sensor nameTing Shen2020-06-021-2/+2
| | | | | | | | | | | | | | | | | Rename incorrect "Lid Mag" to "Base Mag", and "Gyro" to "Base Gyro" for consistency. BUG=None TEST=`accelinfo` BRANCH=None Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Id9072f038cf5e484679e9d6b64249f008dcce274 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226094 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* asurada: update base sensor rotate matrixTing Shen2020-06-021-3/+2
| | | | | | | | | | | | | | | | | | | | | | Update rotate matrix based on our assembled unit. BUG=b:150341271 TEST=manually: 1) board laying on a table: Current data 0: 253 6 8343 2) left edge of the device toward the ground: Current data 0: 8022 448 681 3) bottom edge toward the ground: Current data 0: -103 8255 763 BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Idae526c2fbc238ea555c98f3e1747ecbf932afa7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224762 Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org>
* chip/it83xx: read GPIO level from data mirror registerRuibin Chang2020-06-022-22/+26
| | | | | | | | | | | | | | | | | | | | | In GPIO output mode, the data register is the level what we set, not the actually measured. The data mirror register shows the real level same as we measured, so we change reading the gpio level to data mirror register. BRANCH=none BUG=none TEST=on it81202 evb, GPIO setting open drain, data high, and internal pullup, manully external pulldown, verify that reads "0" in console "gpioget" Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I3afb19daf24d1eda98c503ce7de3527353e88a9e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224676 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org>
* voxel: Initial EC imageDavid Wu2020-06-029-0/+1237
| | | | | | | | | | | | | | | | | | Create the initial EC image for the voxel variant by copying the volteer reference board EC files into a new directory named for the variant. (Auto-Generated by create_initial_ec_image.sh version 1.0.2). BUG=b:157879197 BRANCH=none TEST=make BOARD=voxel Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I93a9c897df25c5700ac4f321510745b104cdb41b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224681 Reviewed-by: Keith Short <keithshort@chromium.org> Tested-by: Paul Fagerburg <pfagerburg@chromium.org>
* Waddledee: Remove 5V input limit for board rev 1Diana Z2020-06-012-5/+4
| | | | | | | | | | | | | | | Removes 5V input limit for board revision 1, while keeping it in place for revision 0 for now. BRANCH=None BUG=b:153594748 TEST=on waddledee rev 0, ensure 5V is requested when a charger is plugged in Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Id7aa6e4ce5e7746ec531725ea7ba5d2599fecdfc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2222962 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* console: add micro seconds in timestampsEric Yilun Lin2020-05-301-3/+15
| | | | | | | | | | | | | | | | | | | | | A more precise timestamp will be helpful while debugging with AP and EC uart logs. This CL adds extra 3 micro second digits in timestamps, and also uses 'yy' rather than 'YYYY' year format. BRANCH=none BUG=none TEST=sudo emerge ec-devutils; dut-control timestamp:on see cpu_uart_pty in such format: 20-05-27 15:50:36.034 Developer Console 20-05-27 15:50:36.038 20-05-27 15:50:36.038 To return to the browser, press: Change-Id: I782e6e080f38cbaaa31b0b96fac839e118619266 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2217493 Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* stm32: Disable option bytes if RO is protected on bootTom Hughes2020-05-302-5/+12
| | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:155897971 TEST=On bloonchipper after flashing flash_write_protect.bin test: * Enable HW WP: dut-control fw_wp_en:on * Reboot to RO: reboot ro * Enable flash protection: runtest 1 => PASS * Reboot to RO: reboot ro * Try to disable flash protection: runtest 2 => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie7bc4d8b518ef1387f77666072a510a8fbfb1d90 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220738 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* test: Add test for flash write protectionTom Hughes2020-05-307-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This test demonstrates the inconsistency between STM32H743 (dartmonkey) and STM32F412 (bloonchipper). BRANCH=none BUG=b:155897971 TEST=On bloonchipper after flashing flash_write_protect.bin test: * Enable HW WP: dut-control fw_wp_en:on * Reboot to RO: reboot ro * Enable flash protection: runtest 1 => PASS * Reboot to RO: reboot ro * Try to disable flash protection: runtest 2 => FAIL TEST=On dartmonkey after flashing flash_write_protect.bin test: * Enable HW WP: dut-control fw_wp_en:on * Reboot to RO: reboot ro * Enable flash protection: runtest 1 => PASS * Reboot to RO: reboot ro * Try to disable flash protection: runtest 2 => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I6eb69257f84f79a6609984efbdad7dd37803c8f6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2209419 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
View Lorry Controller Status