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* volteer: remove VSYNC sensorstabilize-lazor-13278.B-masterKeith Short2020-06-0919-102/+0
| | | | | | | | | | | | | | | Remove VSYNC sensor support from all volteer boards. BUG=b:146452722 BRANCH=none TEST=make buildall TEST=Boot Volteer, run "ectool motionsense" Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I1662f510901fb99a45999f46b854e7ceb3874f03 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2238671 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* servo_v4p1: Add TCA6416A and TCA6424A driversSam Hurst2020-06-095-1/+262
| | | | | | | | | | | | | Add TCA6416A and TCA6424A IO Expander driver. BRANCH=none BUG=b:146793000 TEST=make -j buildall Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I498496bab9f1b874b502c2a1f704d1693a7c1cf5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2223822 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* usb_pd_protocol: Invalidate last message id in SRC_SWAP_STANDBY statePatryk Duda2020-06-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In SRC_SWAP_STANDBY state when PD_CTRL_PS_RDY message is received, message id counter is cleared, but last message id remain the same. Situation where last message before power swap had message id equal to 0, and first message after power swap had message id equal to 0, was reported as message duplication and as result hard reset was triggered. From ServoV4 perspective: C1 RECV 0e6a/0 <-- Received PR_SWAP with msg_id 7 C1 CTRL[3]>1 <-- Accept it C1 st27 SRC_SWAP_SNK_DISABLE C1 st28 SRC_SWAP_SRC_DISABLE C1 st29 SRC_SWAP_STANDBY C1 CTRL[6]>1 <-- Send PS_RDY C1 RECV 0166/0 <-- Received PS_RDY with msg_id 0 due to msg_id overflow C1 st5 SNK_DISCOVERY C1 Repeat msg_id 0 <-- DUT sent capabilities with msg_id 0 C1 HARD RST RX <-- DUT sent hard reset due to timeout BUG=none BRANCH=none TEST=Flash nocturne with EC compiled with TCPMv2/PD3.0 support. Flash ServoV4 with this fix. Run firmware_PDConnect, test should pass. During test check if ServoV4 is not receiving hard reset requests. TEST=Flash nocturne with EC compiled with TCPMv2/PD3.0 support. Flash ServoV4 with this fix. Run 'fakedisconnect 100 10000' in ServoV4 console. Run 'pd 0 swap power' in DUT console. During power swap no hard reset states should be entered. Change-Id: I902d153a4f427c6a7239f8ff8b70efc9418da31a Signed-off-by: Patryk Duda <pdk@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2231365 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_pd: Cleanup: Add functions to process Disc IdentityAyushee2020-06-091-65/+73
| | | | | | | | | | | | | | | | Add separate functions process_am_discover_ident_sop() and process_am_discover_ident_sop_prime() to process the Discover Identity command. BUG=b:148528713 BRANCH=none TEST=make buildall -j Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: Id074b2fc5c9aae02b51b110c9959656cacb36ee7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2185615 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* usb_pd: Cleanup: Cable flagsAyushee2020-06-094-163/+82
| | | | | | | | | | | | | | | | | | | | | | Instead of using CABLE_FLAGS_SOP_PRIME_ENABLE and CABLE_FLAGS_SOP_PRIME_PRIME_ENABLE cable flags, add the type of message to be transmitted directly in the message header. BUG=b:148528713 BRANCH=none TEST=1. make buildall -j 2. Able to enter DP mode with Type-C dock and Type-C to DP connector. 3. Able to enter Thunderbolt-Compatible mode with thunderbolt dock with both Active and Passive cables. 4. Able to Enter USB4 mode with USB4 device with thunderbolt Gen2 cable. Change-Id: Ib0cac818200e7ab8f73cace85ffee65203019709 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2159592 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* common: Restrict gpioset console command for FPMCUYicheng Li2020-06-091-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | Generally, we don't want people to be able to modify GPIOs in production. The main EC already disables the whole console input in production. For the FPMCU, the host command version of gpioset is already restricted. This change restricts the console command version on FPMCU, without changing other boards' behavior. BRANCH=none BUG=b:154655729 TEST=make -j buildall TEST=(change bloonchipper board's USART settings to be the same as nucleo-f412zg's) make -j BOARD=bloonchipper flash the resulting firmware to a nucleo-f412zg device gpioset USER_PRES_L 0 ==> Success syslock ==> Check sysinfo, shows locked gpioset USER_PRES_L 0 ==> Access Denied Change-Id: I9ab893b5742926732148e7c363d8aa7dcd7466f2 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2172056 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* kakadu: turn off Vconn boost gpio pin when S5/G3Scott Chao2020-06-091-0/+3
| | | | | | | | | | | | | | It should be ~0V in G3, 5V in S3/S0. And this pin can solve apple HDMI dongle issue. BUG=b:156570690 BRANCH=kukui TEST=make -j BOARD=kakadu TEST=make buildall Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Change-Id: I3bd23a0534d0d63fe22bf26ed3a24b34b73fa142 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2235235 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* TCPMv2: Call into PD Vbus checkDiana Z2020-06-091-1/+1
| | | | | | | | | | | | | | | | Since not all boards detect Vbus through their TCPC, call into the PD Vbus check function when checking Vbus during a power role swap. BRANCH=None BUG=None TEST=on kindred (with PPC Vbus detection), verify power role swap completes without crashing the EC Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I9e2ae4180f18833fd71acb9661283fafbd80d25a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2236624 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* kakadu: rewrite charger CHG_CTRL1 registerScott Chao2020-06-091-0/+12
| | | | | | | | | | | | | | | We have probability that we can't recognize USB2.0 device due to charger 0x11 OTG setting is changed. So we need CL:2082291 on kakadu, too. BUG=b:158450167 BRANCH=kukui TEST=make -j BOARD=kakadu TEST=make buildall Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Change-Id: I0d5fd4183d521458f830089a23ab328aa10bb421 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2235232 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* NPCX797WC: correct image size to avoid overflowing WP_ROPeter Marheine2020-06-091-37/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The -WC chip has half as much flash as the -WB but the same amount of RAM, which causes the EC_RO section in the output FMAP to be larger than the actual read-only section of flash because code RAM is not more than twice the size of the on-chip flash, which is required because RO also contains the bootloader header. Update the definitions for this chip to generate a smaller image that still fits in Flash after the RO header is added. Because this breaks assumptions about used memory being equal to available memory, remove the RAM size checks and reorganize the chip blocks to define code and data memory in the same block to obviate any need for RAM size checks. BUG=b:158052612 TEST=Verify flash map is not broken: dump_fmap -hh build/dalboz/ec.bin, where prior to this change it complains that sections overlap: 0x00000000:0x0003f03f EC_RO 0x00000040:0x0003f03f FR_MAIN 0x00000184:0x000001a3 RO_FRID 0x0002bf40:0x0002c09d FMAP 0x00000000:0x0003ffff WP_RO 0x00040000:0x0007efff EC_RW 0x00040144:0x00040163 RW_FWID Flashing the new image to a Dalboz boots and jumps to RW correctly. BRANCH=None Change-Id: I2ac28a7f973c4ae715828687edaad5f0110a2950 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2230949 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* kukui: Disable TCPMv1 state names in ROKeith Short2020-06-091-0/+4
| | | | | | | | | | | | | | | | | | | Disable CONFIG_USB_PD_TCPMV1_DEBUG to save 900 bytes of RO flash space. This is to keep kukui buildig at ToT - do not pick this onto a release branch. BUG=b:156398243 BRANCH=none TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I7bc9d84a0cd172e20399b51eb7cd73c89119a574 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2236866 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* strago: Disable TCPMv1 state namesKeith Short2020-06-091-0/+1
| | | | | | | | | | | | | | | | | | Disable CONFIG_USB_PD_TCPMV1_DEBUG to save 900 bytes of RO and RW flash space. This is to keep strago buildig at ToT - do not pick this onto a release branch. BUG=b:157671579 BRANCH=none TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I59472523f024c51609cccefd633cd084cc138784 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2236631 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* samus_pd: Disable TCPMv1 state namesKeith Short2020-06-091-0/+1
| | | | | | | | | | | | | | | | | | Disable CONFIG_USB_PD_TCPMV1_DEBUG to save 900 bytes of RO and RW flash space. This is to keep samus_pd buildig at ToT - do not pick this onto a release branch. BUG=b:158458752 BRANCH=none TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: If2f0a7bfb8306c7744f42aa896dad67d7ec6ed27 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2236630 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* tcpmv1: Add CONFIG_USB_PD_TCPMV1_DEBUG optionKeith Short2020-06-092-5/+12
| | | | | | | | | | | | | | | | | | | | Several legacy boards are consistently running out of flash space. Add CONFIG_USB_PD_TCPMV1_DEBUG option which can be disabled on a board to save about 900 bytes of flash space in the RO and RW images. BUG=none BRANCH=none TEST=make buildall TEST=Verify Volteer board runs with CONFIG_USB_PD_TCPMV1_DEBUG disabled and the PD debug level set to 1. Also run the "pd <port> state" command and verify no side effects. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I29bb70b7d347d8c6d5797c01ed892329d90aa671 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2236629 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* EFS2: Verify and jump when system shuts down in RODaisuke Nojiri2020-06-093-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when the system shuts down in RO, EC resets with AP_OFF flag. This was for allowing the EC to jump to RW and get ready for the next normal boot after a system shuts down from the recovery mode (chromium:1045209). This behavior causes the reboot from the recovery mode to be stopped (b:154778457). This patch makes RO jump to RW instead of resetting with AP_IDLE flag. After sysjump, the AP can continue to sequence up or down. BUG=b:154778457, chromium:1045209, b:156694627, b:157077589 BRANCH=none TEST=test_that suite:faft_bios passes. TEST=Press power button in recovery screen on Zork, Puff, Volteer. System stays in S5 after sysjump. TEST=firmware_CorruptBothFwSigAB passes on Zork, Puff, Volteer. TEST=Hibernate EC on Zork, Puff, Volteer. Press power button once. System boots. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: If08f3bb7f89c2407e4c5207ade820085f65ea9ac Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213359 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power: Don't print timestamp for powerinfo commandDaisuke Nojiri2020-06-091-1/+1
| | | | | | | | | | | | | | | | This patch makes powerinfo command print the result without a timestamp like other console commands. This shouldn't break FAFT. If it does, FAFT should be fixed. BUG=none BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I90f032dc2d079d9d674489d2236b05f6051e574f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2219122 Reviewed-by: Craig Hesling <hesling@chromium.org>
* stoney: Initialize chipset state to S5 after sysjumpDaisuke Nojiri2020-06-091-14/+25
| | | | | | | | | | | | | | | | | | | | | | | | Currently, RW initializes the chipset state to G3 and forces the chipset to shut down unless the AP is already powered on. This behavior is based on the assumption that sysjump happens only upon a request from the AP. With EFS2, it's no longer the case because EC jumps while the AP is off. AP may be off, resetting (i.e. s0->s5->s0), or shutting down (s0->s5). This patch makes RW set the chipset state to S5 if the corresponding power signals are on. BUG=b:156694627, b:157077589 BRANCH=none TEST=test_that suite:faft_bios Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Id8fdd10f411f403cb42bd8429fef737e88421ae9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220547 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* x86 power: Initialize chipset state to S5 after sysjumpDaisuke Nojiri2020-06-091-14/+26
| | | | | | | | | | | | | | | | | | | | | | | | Currently, RW initializes the chipset state to G3 and forces the chipset to shut down unless the AP is already powered on. This behavior is based on the assumption that sysjump happens only upon a request from the AP. With EFS2, it's no longer the case because EC jumps while the AP is off. AP may be off, resetting (i.e. s0->s5->s0), or shutting down (s0->s5). This patch makes RW set the chipset state to S5 if the corresponding power signals are on. BUG=b:154778457 BRANCH=none TEST=Verify test_that suite:faft_bios passes. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I65cbb6c6e7f8a01e80d83a74e376ceb9628b9789 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213733 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
* tcpmv2: Set Rp selected value into RoleControl when neededDenis Brockus2020-06-082-9/+10
| | | | | | | | | | | | | | | | | | | The tcpci_tcpm_select_rp_value caches the rp value and set_cc will update the value but not all paths call set_cc and should still have a valid Rp value set BUG=b:157755939 BRANCH=none TEST=Verify Rp correctly Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I5e2cd1bd2c7fffa06f46e1d7a77868f49454c591 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2223914 Tested-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org>
* flash_ec: flashrom: Use google-servo-v2 instead of servo-v2Nicolas Boichat2020-06-081-1/+1
| | | | | | | | | | | | | | | Get rid of deprecation warning. BRANCH=master BUG=b:145175076 TEST=none Change-Id: I4fe9adc3811f8dcd6a75fe9481d7e44a29d5126e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2234042 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Commit-Queue: Edward O'Callaghan <quasisec@chromium.org> Tested-by: Edward O'Callaghan <quasisec@chromium.org>
* flash_fp_mcu: fix the volteer gpio settingZhuohao Lee2020-06-081-15/+15
| | | | | | | | | | | | | | | | | Due to the latest coreboot change, the gpiochip252 and gpiochip445 were removed and the gpiochip152 was added. Besides, the GPIO pin also changed. This patch fixes the gpio pin setting. BUG=b:156993750 BRANCH=none TEST=ran flash_fp_mcu on the Volteer Change-Id: I54082eea90e85746976d427523cfc0b53e87ddda Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2214876 Tested-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Alex Levin <levinale@chromium.org>
* asurada: enable C0/C1 USB muxEric Yilun Lin2020-06-082-0/+39
| | | | | | | | | | | | | | C0: IT5205 C1: PS8743 redriver BRANCH=master BUG=b:154559495 TEST=make build Change-Id: I103e6f5d41d6c2f2618f95753547bb8e5a190bac Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2167126 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* system: Do pending reboot when the chipset is completely offWai-Hong Tam2020-06-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pending reboot command is currently triggered in the CHIPSET_SHUTDOWN hook. The CHIPSET_SHUTDOWN hook is triggered before the power rails are removed. The hook is executed in the CHIPSET task context, meaning the chipset is still ON. Should wait for the chipset is completely off. All the power rails are turned off. So change the hook to the CHIPSET_SHUTDOWN_COMPLETE. Also make it the lowest priority. So other hooks have chances to be executed before EC reboot. BRANCH=None BUG=b:156981868 TEST=Ran "ectool reboot_ec cold at-shutdown" and "shutdown -H now". [45.061296 power state 8 = S3->S5, in 0x0005] [45.068785 Base Accel ODR: 0 - roundup 0 from config0 [AP 0]] [45.070271 Base Accel ODR: 0 - roundup 0 from config0 [AP 0]] [45.076021 Gyro ODR: 0 - roundup 0 from config 0 [AP0]] [45.078307 PD:S3->S5] [45.078877 Gyro ODR: 0 - roundup 0 from config 0 [AP0]] [45.080055 set_pmic_pwron(0)] [45.150585 set_system_power(0)] [45.161457 power shutdown complete] Reboot at shutdown: 4 Change-Id: Ic8258cbf35fccff633d0c9ccd5d09faefc594855 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228396 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* hooks: Introduce HOOK_CHIPSET_SHUTDOWN_COMPLETEWai-Hong Tam2020-06-0622-0/+71
| | | | | | | | | | | | | | | | | | | A new hook HOOK_CHIPSET_SHUTDOWN_COMPLETE is introduced, which are called from the chipset task, while the system has already shut down and all the suspend rails are already off. It will be used for executing pending EC reboot at the chipset shutdown. The EC reboot should be executed when the chipset is completely off. BRANCH=None BUG=b:156981868 TEST=Built all boards. Change-Id: I12f26957e46a1bb34ef079f127b0bddd133cd4e7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228395 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tcpc: Call default TCPC register dumpKeith Short2020-06-061-0/+2
| | | | | | | | | | | | | | | | If the TCPC chip driver doesn't provide it's own register dump routine, call the standard TCPC register dump. BUG=none BRANCH=none TEST=make buildall TEST=On volteer verify "tcpci_dump" on both ports. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I46044013ba06f805c89f38a6540a9ec938636a01 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2232833 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* strago: remove HCDEBUG command to save spaceKeith Short2020-06-061-0/+1
| | | | | | | | | | | | | | | Remove the HCDEBUG to reclaim 256 bytes of flash space. This is just keep strago building at ToT; do not pick this onto a release branch. BUG=b:157671579 BRANCH=none TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ied9043adbb9bb13b0ae7587a6f6acd6aede6a687 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2232827 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* volteer: add USB overcurrent notification to APKeith Short2020-06-056-1/+19
| | | | | | | | | | | | | | | Enable the USB C0 and USB C1 overcurrent signals to the AP. BUG=b:140561826 BRANCH=none TEST=make buildall TEST=Force overcurrent event by manually setting PPC current limit below PD contract. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I5eea4812c212496f1c483c4149697b2d53a16a37 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2222960 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* Ezkinil: modify some gpio definitionSue2020-06-0511-25/+79
| | | | | | | | | | | | | | | | | | | rename GPIO F4: DP1_HPD -> EC_DP1_HPD remove IOEX 10 HDMI_CONN_HPD_3V3_DB add GPIO 75: DP1_HPD_EC_IN move hdmi_hpd_interrupt and hdmi_hpd_handler from baseboard to board BUG=b:152512560, b:153397667, b:155797182 BRANCH=none TEST=make buildall -j Change-Id: I5cdbb42a8284c85104dbbbe7b3d557d51a11a074 Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224693 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* servo_micro: Increase USART2 queue sizeTom Hughes2020-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When servo_micro is forwarded to a remote machine with usbip (go/chromeos-wfh-tools#usbip) and the FPMCU console is on USART2, I see dropped characters: > help Known commands: chan flashwrite gpioset reboot sysinfo crash fpcapture hc history rw taskinfo flashinfo e info; HELP CMD = help on CMD. This doesn't happen when using the same setup with servo_micro's USART3, which has a larger queue size of 1024, so increase USART2 queue size to match. BRANCH=none BUG=b:147849609 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I5badc239dad866eba0571b3626961b1008979273 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2229296 Reviewed-by: Jett Rink <jettrink@chromium.org>
* zork: Move tcpc,ppc,bc12 from baseboard to boardLu Zhang2020-06-057-212/+648
| | | | | | | | | | | BUG=b:158125500 BRANCH=none TEST=Build all zork boards Signed-off-by: Lu Zhang <lu.zhang@bitland.corp-partner.google.com> Change-Id: I86a21a049f97c42d330be6c1bfbecbda10e1ebb6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2230941 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* asurada: enable lid angle calculationTing Shen2020-06-052-0/+21
| | | | | | | | | | | | | BUG=b:150341271 TEST=`accelread on`, verify the value looks reasonable BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I03bf63d95abba2c713ec6094dd3ba3e9ba6d4738 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228079 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* asurada: enable lid sensor LIS2DWLTing Shen2020-06-053-1/+40
| | | | | | | | | | | | | | | | BUG=b:150341271 TEST=1) `accelread 3` prints reasonable numbers. And the orientation is aligned with base IMU. 2) Combined with CL:2230218, `accelinfo on` to verify interrupt works. BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Idb7177ebdb819704f4fa74c02ffdbf1a0031a377 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2215758 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* volteer: Enable CONFIG_USB_PD_USB32_DRDAyushee2020-06-051-0/+3
| | | | | | | | | | | | | BUG=b:148528713 BRANCH=None TEST=On connecting Gatkex Creek with DUT as UFP, the DUT enter into USB3 mode. Change-Id: I98d83ed14d92431b9e0392ffceb4e37792dde9f1 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2225602 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* usb_pd: Move USB4 functions to common fileAyushee2020-06-055-78/+90
| | | | | | | | | | | | | | | | | Added a check for CONFIG_USB_PD_ALT_MODE_DFP in pd_send_enter_usb() and added separate configs for USB4 DRD and USB3.2 DRD BUG=b:148528713 BRANCH=none TEST=Able to enter USB4 mode with following passive cables - a. Rev 3 USB3.2 Gen 1, USB3.2 Gen 2 and USB4 Gen 3 b. Rev 2 USB3.1 Gen1/Gen2 Change-Id: I80c9b7569429bc54db08d78b5a6eee16780d6fe1 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051631 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* usb_pd: USB4: Limit the cable speedAyushee2020-06-055-39/+48
| | | | | | | | | | | | | | | | | | | | | | | Added 'get_usb4_cable_speed()' to return USB4 speed as per the port, the speed supported by DUT's port or cable speed whichever is lowest. Added configuring the cable speed in cros_ec_usb_pd_control according to the mux setting. Removed 'set_max_usb4_cable_speed()' to retain cable's actual VDO response. BUG=b:157671582 BRANCH=none TEST=1. Able to set USB4/USB3.2 Gen2 cable speed when DFP isn't gen 3 capable. 2. Able to limit cable speed according to the port, if the cable speed is higher. Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I21bba7e5a2aa8ca54f304ef8418320f319f020b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220826 Reviewed-by: Keith Short <keithshort@chromium.org>
* usb_pd: TBT: Refactor limiting the cable speedAyushee2020-06-055-45/+28
| | | | | | | | | | | | | | | | | | | | Refactored 'get_tbt_cable_speed()' to return thunderbolt-compatible speed as per the speed supported by DUT's port or cable speed whichever is lowest. Also removed 'usb_pd_limit_cable_speed()' to retain cables's actual VDO response. BUG=b:157671582 BRANCH=none TEST=Able to limit thunderbolt cable speed, if the cable speed is higher than the speed supported by DUT's port. Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I77d3efddb425daa7bd12e9ed21be7088074285bb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227088 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* Bloonchipper: USART based transport layer for host commandBhanu Prakash Maiya2020-06-0518-26/+1088
| | | | | | | | | | | | | | | | | | | | 1. USART host command layer in chip/stm32 2. Fix usart implementation in stm32 BUG=b:147849609 BRANCH=none TEST=1. make BOARD=bloonchipper -j 2. usart request and response works on dragonclaw Change-Id: Idd89d3e490f23aa528ecaf6510c13d16b405de13 Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2190531 Tested-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
* fpsensor: cleanup multiple fp spi enableBhanu Prakash Maiya2020-06-055-7/+13
| | | | | | | | | | | | | | BUG=b:147849609 BRANCH=none TEST=1. make buildall -j Change-Id: I35146070ec20a3605588792fc19595dc1c1ea3cf Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2191733 Tested-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
* berknip: add Cosmx battery configurationZick Wei2020-06-052-0/+29
| | | | | | | | | | | BUG=b:157950071 BRANCH=none TEST=make buildall Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: Icb01629d04be5f2b31a28d906d14095606e7b78d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2229899 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* servo: Add USB SPI helper functions and context statesBrian J. Nemec2020-06-052-86/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds context states to USB SPI for handling receiving and transmitting data. These context states allow us to keep track of data buffers that can not fit within a single USB packet. A context state has been added to describe the USB packets accepted by the USB SPI protocol. This structure includes union fields for easily addressing the different packet's fields and to describe the basic attributes for a USB packet including its size and how many bytes are allocated to the header. Helper functions process the USB packets and aid in the transfer of data between them and receive and transmission buffers. BUG=b:139058552 BRANCH=servo TEST=Tested with Servo Micro reading and verifying flash writes are successful in a loop. Signed-off-by: Brian Nemec <bnemec@chromium.org> Change-Id: I3e0b31f33f442719123b9e897495cad25e9e6ed4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224764 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org>
* Bobba: Fix printing when cbi_get_board_version() failedDavid Huang2020-06-051-1/+1
| | | | | | | | | | | | | | | Fix the printing when cbi_get_board_version failed. BUG=b:154772847, b:156711950 BRANCH=octopus TEST=Check usb dongle/typec adapter worked properly in any power state. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I6df4026476cd60cf1b7bb435f95800c70e9692cf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2230950 Reviewed-by: Marco Chen <marcochen@chromium.org> Commit-Queue: Marco Chen <marcochen@chromium.org> Tested-by: Marco Chen <marcochen@chromium.org>
* ISL9241: Fix slew rate controlEric Herrmann2020-06-052-0/+13
| | | | | | | | | | | | | | | | | | The slew rate control was not being configured properly, which lead to overcurrent protection being triggered on adapter insertion. This now enables slew rate control in the init sequence. BUG=b:148487130 BRANCH=none TEST=With a current probe, ensure that there is no spike when the battery begins charging due to VSYS ramp. TEST=make buildall Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: I8df02e4983acd1e11c4d395b8aabd34bf9688e06 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2229960 Tested-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* vilboz: Remove PCAL6408 entirely and enable HDMILu Zhang2020-06-059-110/+138
| | | | | | | | | | | | | BUG=b:157182792, b:158125500 BRANCH=none TEST=make BOARD=vilboz Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I71e38117309277c39ed245535643d601e8759d28 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227782 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Lu Zhang <lu.zhang@bitland.corp-partner.google.com> Commit-Queue: Lu Zhang <lu.zhang@bitland.corp-partner.google.com>
* baseboard/kukui: lower pd max voltage to 15V for jacuzziTing Shen2020-06-051-1/+2
| | | | | | | | | | | | | | | | Charging performance is better at 15V than 20V, see the analysis result in issue link below. BUG=b:157116471 TEST=make BRANCH=kukui Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I8113809372fc2e1e92be901025ee1ed4bd588a80 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2230219 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* util/flash_jlink.py: Reset after flashingCraig Hesling2020-06-041-0/+1
| | | | | | | | | | | | | | | | | | | You must reset the chip after flashing to start the new code. It is possible that the chip was resetting without this fix due to a double fault after flashing. In cases where the CPU is hung before flashing, the CPU would not reset. BRANCH=none BUG=none TEST=# Ensure that the chip is hung in on b/147520242 ./local/flash_jlink.py --ip '' # The UART console should reflect a reset and become interactive again Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I5006eff5d3a955ba9b8e6ecee4f72d7ad851f239 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226520 Commit-Queue: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* util/flash_jlink.py: Allow USB modeCraig Hesling2020-06-041-3/+8
| | | | | | | | | | | | | | | | | | | | This adds the option to specify "" for --ip, which will disable the TCP/IP mode. Thus, the JLink tool will default to USB direct. BRANCH=none BUG=none TEST=# Ensure JLinkRemoteServerCLExe is not running ./util/flash_jlink.py --ip '' # Ensure JLinkExe uses direct USB and succeeds TEST=# Ensure "JLinkRemoteServerCLExe -Port 2551 -select USB" is running ./util/flash_jlink.py # Ensure JLinkExe uses TCP/IP and succeeds Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I9da2efa8adf155673f14f12dbb354492b0827332 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226880 Commit-Queue: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* util/flash_jlink.py: Allow using PATH to find JLinkExeCraig Hesling2020-06-041-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Installing Jlink Debian package places JLinkExe in a PATH area. This allow flash_jlink to find the normal path'ed executable in addition to the hand placed binary. BRANCH=none BUG=none TEST=# Assume JLink_Linux_V670e_x86_64 dir does not exist mkdir ./JLink_Linux_V670e_x86_64 touch ./JLink_Linux_V670e_x86_64/JLinkExe chmod +x ./JLink_Linux_V670e_x86_64/JLinkExe ./util/flash_jlink.py # Should fail TEST=# Ensure the proper JLinkExe is in PATH rm -rf ./JLink_Linux_V670e_x86_64 ./util/flash_jlink.py # Should succeed Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: Ife0c2b7a47f989877f7b81a81a7dadd2b7cb5c1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226879 Commit-Queue: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* util/flash_jlink.py: Fix formatting + parsing conventionCraig Hesling2020-06-041-14/+15
| | | | | | | | | | | | | BRANCH=none BUG=none TEST=./util/flash_jlink.py --jlink JLinkExe --ip blah # Ensure that the blah parameter was passed Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: Iee38468eb38e91eb3f2b6c19de9c5070f1c0bc5a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226878 Commit-Queue: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* util/flash_jlink: Enforce python3Craig Hesling2020-06-041-1/+1
| | | | | | | | | | | | | | | | | Python 3 is required for the subprocess.run line. Enforcing python 3 helps our non-chroot devs. BRANCH=none BUG=none TEST=# Outside chroot ./util/flash_jlink.py # Ensure the error does not reference subprocess.run Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I057c1b00696a4b356f162795fd1794eba9c54bd7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226877 Commit-Queue: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* TCPMv2: Wait for Safe0V on PR Swap SNK to SRC before PS_RDYDenis Brockus2020-06-043-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were out of spec for PR Swap transitioning from SNK to SRC by sending PS_RDY before we were Safe0V. We only waited for the TC state machine to go from attached.snk to attached.src, which happened on the first state machine tick after pe_prs_src_snk_transition_to_off_entry was called and this does not guarantee Safe0V as is needed. Added an extra state to reflect what the PD spec requests and now waiting for Safe0V before indicating we are powered off. BUG=b:157755939 BRANCH=none TEST=ThinkPad Dock G2 should attach Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I93eb36acc64f273e8b30ca0a0bb76d6fa96b64ba Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2223723 Tested-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org>
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