summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* Add AP userspace scripts to tweak lightbar colorsstabilize-link-2913.278Bill Richardson2013-01-117-153/+488
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have yet another tweak for the lightbar, but we don't want to update the EC. This CL adds an init script that runs on the AP at every boot and pokes the EC to modify the lightbar settings. We have to run it at every boot because the EC will hibernate after the AP has been off (not suspended) for an hour on battery power and will lose its settings. There's a corresponding CL for the ec-utils ebuild that installs the userspace scripts into the rootfs. NOTE that in order to cherry-pick this into R23 from ToT, we have to update ectool as well, because the original R23 ectool doesn't implement the "lightbar params" command. However, the EC image that ectool talks to is built from a *different* branch that already has the ectool update, so this change DOESN'T backport any of the EC firmware changes that would otherwise be required. Instead, we just hack a little bit to make the EC firmware compile. BUG=chrome-os-partner:16827 BRANCH=link TEST=manual Build the image for Link, install, reboot. Run "ectool lightbar params". The output should match what's in /usr/share/ec/lightbar_params.txt Original-Change-Id: If50ac2ef2432f7d60cdaf4c222b68dbdee80b2ec Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/39979 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Richard Barnette <jrbarnette@chromium.org> (cherry picked from commit 3eb6f58d3e18647797ad4e3f16203c419ed4c791) Change-Id: Ied2304da58d6d27b4f186e621bb187ba9a574e6c Reviewed-on: https://gerrit.chromium.org/gerrit/41167 Commit-Queue: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org>
* temp_metrics: Set GPU min freqSameer Nanda2012-11-281-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | On systems with modems, a harmonic of the lowest GPU frequency of 350Mhz interferes with the cellular signal. Set the minimum GPU frequency for such systems to 450Mhz. BUG=chrome-os-partner:16439 TEST="cat /sys/kernel/debug/dri/0/i915_min_freq". On systems without this modem, it should read back 350. On systems with the modem, it should read back 450. BRANCH=none Original-Change-Id: I103a55af11955aed2f3e8c945904444475c63865 Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/38826 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> (cherry picked from commit 8722b5b142bb2dcbd7e0aa14c867eb17b9aeb850) Change-Id: I28cf623b974380eba95963ea4126dce532cc14e3 Reviewed-on: https://gerrit.chromium.org/gerrit/38842 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Sameer Nanda <snanda@chromium.org>
* temp_metrics: tmp006 calibration updatestabilize-linkstabilize-daisystabilizeSameer Nanda2012-10-231-4/+3
| | | | | | | | | | | | | | | | | Updated S0 calibration settings based on DVT3 systems. De-activate the PCH sensor in the thermal loop as its accuracy is poor. BUG=chrome-os-partner:9599 TEST=run "for i in {0..3}; do echo $i: && ectool tmp006cal $i; done" and make sure the S0 values are the same as those programmed by temp_metrics.conf. BRANCH=none Change-Id: I5a90575dc4f65d7ef12f2ed4ad366e1710499cc5 Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36319 Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* temp_metrics: disable ACPI thermal zone 1Sameer Nanda2012-10-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | ACPI thermal zone 0 is used for critical thermal events while thermal zone 1 is used for asserting (internal) prochot and duty cycling. Since the equivalent of thermal zone 1 functionality exists in temp_metrics, disable ACPI's thermal zone 1 in order to prevent conflicts between ACPI and temp_metrics. BUG=chrome-os-partner:9193 TEST='cat /sys/class/thermal/thermal_zone1/mode' and check that it is disabled. BRANCH=none Original-Change-Id: I689e8e5c1747c5f259f4a72a9f86396f4aa5c0b2 Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35593 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 4dd3940d19196fc3f872f08ec30d6d5a6ad8ef28) Change-Id: I363467d409abfe4b0f42b769b996944638c6bbdb Reviewed-on: https://gerrit.chromium.org/gerrit/35695 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Sameer Nanda <snanda@chromium.org>
* temp_metrics: tmp006 calibration and fan loop updatesSameer Nanda2012-10-161-22/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent changes that have gone into the EC, the TMP006 calibration data is no longer present in the EC by default. Push it down to the EC via the newly added ectool tmp006cal command. Also added couple of changes to the fan loop: - hand back fan control loop to the EC if none of the TMP006 sensors report valid temperatures. - handle S0->S3->S0 transition where the EC sets the fan to 0 RPM. BUG=chrome-os-partner:9193 TEST=run "ectool tmp006cal" command for sensors 0, 1, 2 and 3 and ensure that they return non-zero calibration values. BRANCH=none Original-Change-Id: Iaf91216a4d3353f15489b39aba9acb34055551cf Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35469 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> (cherry picked from commit dd300b5baf1d6eff7f53b8a94c8574cfece52685) Change-Id: I69549b360fb92bce5cc3326e635dbafd80ee011d Reviewed-on: https://gerrit.chromium.org/gerrit/35694 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Sameer Nanda <snanda@chromium.org>
* Add host command to get/set TMP006 calibration dataRandall Spangler2012-10-162-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for host-based thermal control and tweaking. BUG=chrome-os-partner:14955 BRANCH=link TEST=manual From a root shell, ectool tmp006cal 0 3.5e-14 -2.8e-5 -5.5e-7 4.5e-9 ectool tmp006cal 2 3.6e-14 -2.9e-5 -5.6e-7 4.6e-9 ectool tmp006cal 0 S0: 3.500000e-14 b0: -2.800000e-05 b1: -5.500000e-07 b2: 4.500000e-09 ectool tmp006cal 2 S0: 3.600000e-14 b0: -2.900000e-05 b1: -5.600000e-07 b2: 4.600000e-09 At the ec console, "t6cal" should show the settings took effect as well. Original-Change-Id: If43b11e1e827483f0a20db1a2e5644f3475fd95e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35215 (cherry picked from commit d1bebbbe66f78d2dcfb9380456a80e7c2f26a662 only the host part of the patch: ectool and ec_commands.h) Change-Id: I78f4649ded835f164c1bf2cf928874dcdbce8f48 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35584 Reviewed-by: Sameer Nanda <snanda@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* link: Added sensor-not-calibrated error for TMP006Randall Spangler2012-10-162-4/+12
| | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:15174 BRANCH=link TEST=manual, from root shell - ectool temps all -> prints all temps - ectool tmp006cal 1 0 0 0 0 - ectool temps all -> sensor 3 not calibrated Original-Change-Id: I16ee818c948fe90ac7c18b230c5d9f9a0ec83ded Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35288 Reviewed-by: Bill Richardson <wfrichar@chromium.org> (cherry picked from commit 23fe5ed867b2811a84171755137021608dda5777 only the host part of the patch: ectool and ec_commands.h) Change-Id: I7b9d6b4f9e1555e118b0591846e407c0a146d7f9 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35583 Reviewed-by: Sameer Nanda <snanda@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* temp_metrics: remove prochot and TCC modificationsSameer Nanda2012-10-111-14/+0
| | | | | | | | | | | | | | | | | | | | | External prochot input was disabled due to board issues. Re-enable it since those board issues are now fixed. Remove modification of TCC offset. Changes to TCC offset from this script are ineffective since they need to happen before the BIOS sets the BIOS_RESET_CPL bit way early in the initialization sequence. BUG=chrome-os-partner:9193 TEST=from shell run "rdmsr 0 0x1fc" and check that bit 0 is set to 1. BRANCH=link Change-Id: Ida2a090539d7e074794e13a90f251babb6c4ade9 Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35067 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> (cherry picked from commit 3af7bc4335d7f6e8e16306603c54cf4fc2f502e3) Reviewed-on: https://gerrit.chromium.org/gerrit/35270
* Fine tuning of temp_metrics thermal loopSameer Nanda2012-10-031-18/+33
| | | | | | | | | | | | | | | | | | Fine tuned temperature thresholds and added watermark concept to the thermal loop. BUG=chrome-os-partner:9193 TEST=Vary CPU and GPU load on the system. The fan speed and CPU/GPU limits should change as the skin temperature responds to changes in the load. BRANCH=link Change-Id: I43739097e699bc4e724e395c6e830c7c694704cc Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/34454 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit c98e1079318f90dc0d5b8238da0d50d46a530ead) Reviewed-on: https://gerrit.chromium.org/gerrit/34546
* Update temp_metrics to look at skin temperaturesSameer Nanda2012-10-011-30/+127
| | | | | | | | | | | | | | | | | | | | Updated temp_metrics to take the skin temperature into account instead of PECI CPU temperature for controlling fan speed as well as Ivy Bridge throttling. BUG=chrome-os-partner:9193 TEST=Vary CPU and GPU load on the system. The fan speed and CPU/GPU limits should change as the skin temperature responds to changes in the load. BRANCH=link Change-Id: Ie3d85112de1043cf5b12a78ca1fc50f5eb6c0497 Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/34221 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit bb66bec788c9447976d1be56f69a40b6c1ea36a3) Reviewed-on: https://gerrit.chromium.org/gerrit/34388
* Snow: Retry accesses to PMU before hard resetCharlie Mooney2012-09-182-31/+45
| | | | | | | | | | | | | | | | | | | | | | | Previously, after the first error when trying to reset the pmu over i2c, the ec would immediately give up and force a hard reset. Since i2c can be a little flaky from time to time, to prevent unneeded resets this allows the EC 3 attempts to configure it nicely it before it forces the whole system to reset. BUG=chrome-os-partner:14156 TEST=Boot machine successfully multiple times. Add a line in to force a failure whenever the pmu is accessed to simulate a total failure and check the EC logs, it should try 3 times on startup and on shutdown before finally resorting to a hard reset. If you add a fake failure that only triggers once, the machine should still turn out without incident. Without any fake failures, everything should work as normal. BRANCH=snow Change-Id: I1f453e9a6acc59d63e4cc80cffb58684f104ca6d Signed-off-by: Charlie Mooney <charliemooney@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/33466 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Improve handling of bursts of port 80 writesRandall Spangler2012-09-171-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Loop on FRMH bit set in the interrupt handler. This has 2 benefits: 1) FRMH is checked every LPC interrupt. So if port 80 gets stuck, any LPC activity like keyboard or host commands will unstick it. 2) Bursts of rapid writes to port 80 are captured more accurately. This also seems to prevent the port 80 channel from getting stuck. There's a small drawback that if the host spams port 80 non-stop for several seconds it can watchdog the EC, but if the host has access to write to I/O ports it could already accomplish a similar result simply by writing the 0xd1 reboot command to the host interface. BUG=chrome-os-partner:12349 BRANCH=link TEST=manual 1. From a root shell, 'ectool port80flood' repeatedly (20x or so). 2. Reboot. Port 80 codes should still be captured. Change-Id: I7a51dfe6a384a0d08cfeb91a539217fc59488637 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/33444 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Reset LPC from-host channel status on LPC resetRandall Spangler2012-09-173-2/+25
| | | | | | | | | | | | | | | | | | | | | This works around a LM4 bug where the LPC module stops triggering interrupts for a channel if bytes are written too rapidly to that channel. This should only affect port 80 because other channels use busy-status-handshaking to avoid flooding the EC. BUG=chrome-os-partner:12349 BRANCH=link TEST=manual 1. From a root shell: ectool port80flood 2. Repeat until the EC console stops showing port 80 codes coming in 3. From a root shell: reboot 4. Port 80 codes should be printed by EC as the BIOS boots Change-Id: I3b3463ce668727cad9900b576fdeb531986a415e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/33142 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* spi: Rewrite driver for new protocol, better performanceSimon Glass2012-09-174-138/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old spi driver has atrophied in various ways. It doesn't support the new protocol and does not build either. Rewrite the driver to: - Use dma for reception (rather than just reception) - This makes message reception more robust and allows us to process the new multi-byte commands - Add timeouts for rx and tx so that we don't wait forever - Increase buffer sizes to deal with new larger messages - Always send a preamble byte regardless of SPI clock speed (previously above 10MHz we sometimes miss this) - Use the NSS line to delineate transactions. When it drops, a transaction is starting. When it rises the transaction is immediately terminates regardless of state. This keeps the AP and EC in sync even in the event of timeouts, bus errors and other oddities. - Implement the new protocol which has a checksum, version byte, etc - Set up tx dma in advance and kick it when ready, thus ensuring that a message body is always attached immediately after the preamble - Use the new host_cmd_handle_args structure, which makes things much easier for us, since we don't need globals, and can use the send_response handler to know when a slow command is complete. - Handle the new type of 'slow' commands properly BUG=chrome-os-partner:10533 TEST=manual build and boot to kernel on snow Change-Id: I11767d1a6f045a86f6c9a0b4b1e943b660e4da33 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32076 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* fix signedness issue in deep sleep delayVincent Palatin2012-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | From time to time, the next timer deadline might have just expired aftering entering the idle loop, so the delay might be negative, it's a bad idea to use an unsigned variable... Now, in the uncommon case where the timer is expired, the next_delay is negative, so we use the "normal" wfi path and as the timer interrupt is pending in that case, we return directly. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:13364 TEST=On Snow, plug a servo on EC serial console, shutdown the machine, unplug AC and wait for several hours. Observe we no longer have spurious watchdog reboots. BRANCH=snow Change-Id: I40c7aa0fc7c1d6f9a5efaa1e7fc6615ed457196b Reviewed-on: https://gerrit.chromium.org/gerrit/33149 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Add capability to auto-hash correct size for EC-RO or EC-RWRandall Spangler2012-09-123-49/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise the host needs to tell the EC how big this image is (which it knows, but it's inconvenient for it to provide). BUG=chrome-os-partner:13511 BRANCH=all TEST=manual 1. ectool echash recalc ro -> prints hash of RO code (offset 0) 2. ectool echash recalc rw -> prints hash of RW code (offset non-zero) In each case, size should be an exact number and not the size of the whole RO or RW section. So for link, output should be something similar to: localhost ~ # ectool echash recalc ro Hashing EC-RO... status: done type: SHA-256 offset: 0x00000000 size: 0x00012a64 hash: 03a66c076d6dd4b4aa9ed6386713f45291f5143f9af2093003e632485899daf1 localhost ~ # ectool echash recalc rw Hashing EC-RW... status: done type: SHA-256 offset: 0x00014000 size: 0x000123d1 hash: 0d6225e70f0b1e0419e987370371e00783f945827ef25915a8fb8549159dd2a4 Signed-off-by: Randall Spangler <rspangler@chromium.org> 3. At ec console, 'hash ro' or 'hash rw' should regenerate the same hash values printed above. Change-Id: I3f6085d29927b8cdf9dabc6930f0fdc7222bd8b5 Reviewed-on: https://gerrit.chromium.org/gerrit/33123 Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Randall Spangler <rspangler@chromium.org>
* link: disable unused EEPROM modulesRandall Spangler2012-09-123-8/+10
| | | | | | | | | | | | | | | | Haven't found a use for these, so remove to reduce code size (reduces binary by 2KB) / complexity. These are still test-compiled on BDS so they'll be ready if needed. BUG=chrome-os-partner:11232 BRANCH=link TEST=build and boot firmware. 'help' should not show eeread/eewrite commands Change-Id: I0f2e41e21efcbbb0967a5b85b7c8a2ff8147460e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/33112 Reviewed-by: Simon Glass <sjg@chromium.org>
* Fix not setting in_progress flag when starting hash computationRandall Spangler2012-09-121-1/+1
| | | | | | | | | | | | | | | | | This allows recomputing hash after EC boots. BUG=chrome-os-partner:13988 BRANCH=all TEST=manual 1. hash 2048 2048 2. hash 0 2048 3. hash -> hash value should be different than in step 1 Change-Id: Id66d0655a143b5190b5d8949b0fa9a18dbbc05f4 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/33118 Reviewed-by: Simon Glass <sjg@chromium.org>
* link: remove TMP006 sensors no longer present in DVT2Randall Spangler2012-09-112-75/+23
| | | | | | | | | | | | | | | | This removes sensors U10, U13, U15, and U29 BUG=chrome-os-partner:13274 BRANCH=link TEST=temps command should show only USB, PCH, hinge, charger die/object temps and PECI should still be the 10th temp sensor Change-Id: If33266ad87ec06a8d4272009d80e382fa4003e2b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32822 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* Cleanup: move lightbar command enum into ec_commands.hRandall Spangler2012-09-113-17/+23
| | | | | | | | | | | | | | | | | | | | Previously this was in lightbar.h. ec_commands.h should not require other header files. Also make brightness local variable static, so it won't leak outside lightbar module. This is simply code cleanup; values themselves have not changed. BUG=none TEST=if it builds, it's fine BRANCH=none (not required in link branch since it's just cleanup) Change-Id: I5722fb677fcec99e0826e3dfc0b22033781b576f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32815 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
* snow: Clear state of charge calculation window on state changeRong Chang2012-09-101-4/+19
| | | | | | | | | | | | | | | | | The moving average window contains previous discharging state of charge values after state change. This change resets the index to make it calculate only new battery readings. Signed-off-by: Rong Chang <rongchang@chromium.org> BRANCH=snow BUG=chrome-os-partner:13846 TEST=none Change-Id: Ifc6c6208dea8edf262e7294972d7321501b709e2 Reviewed-on: https://gerrit.chromium.org/gerrit/32865 Commit-Ready: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* snow: Check state of charge using moving averageRong Chang2012-09-101-1/+38
| | | | | | | | | | | | | | | | Signed-off-by: Rong Chang <rongchang@chromium.org> BRANCH=snow BUG=chrome-os-partner:13846 TEST=manual Connect EC UART console and discharge snow device. The system should be turned off when average state of charge is lower than 2.5%. Change-Id: Iab9797d0aa6b159bedd8ce0d2fa72c6458cd14ac Reviewed-on: https://gerrit.chromium.org/gerrit/32693 Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Sameer Nanda <snanda@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Move pending command logic into host_commandSimon Glass2012-09-103-103/+98
| | | | | | | | | | | | | | | | | | | | | | | | This logic doesn't really belong in drivers, since to enable another driver (like SPI) we must repeat it all. This is tricky if we enable both I2C and SPI. Move the logic into host_command. BUG=chrome-os-partner:10533 BRANCH=none TEST=manual Use U-Boot to test comms status functionality on snow: SMDK5250 # mkbp write rw 40000000 SMDK5250 # mkbp erase rw SMDK5250 # mkbp erase rw Change-Id: I3f90aada80208cd0540be14525f73f980ad33292 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32075 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add Alt+VolUp+H key combo to hibernate systemRandall Spangler2012-09-101-0/+6
| | | | | | | | | | | | | | | | | This is needed for testing wake-from-hibernate. BUG=chrome-os-partner:13680 BRANCH=link (if needed for factory, else none) TEST=manual 1. Boot system. 2. alt+volup+h. System hibernates (unless you've got hardware issue 13680) 3. Press power button. System wakes. Change-Id: I66e1299a948bffe22c10863a4ffbe5c507e2c5dd Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32442 Reviewed-by: Simon Glass <sjg@chromium.org>
* Refactor runtime special key combination codeRandall Spangler2012-09-102-25/+38
| | | | | | | | | | | | | | | | | | The code for warm reboot is overly specialized, and makes it hard to add other key cominations for testing. BUG=chrome-os-partner:13763 BRANCH=link TEST=manual 1. boot system 2. hold down (in order) R+T+alt+VolUp. System does not reboot. 3. let go of T (so only R+alt+volup are pressed). System reboots. Change-Id: I14cdb7f790e8a772712085a77eaf4299487788db Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32439 Reviewed-by: Simon Glass <sjg@chromium.org>
* Remove old code to clear boot keyRandall Spangler2012-09-103-18/+1
| | | | | | | | | | | | | | | | | This has been deprecated in favor of a host event to trigger recovery mode. BUG=none BRANCH=link TEST=manual 1. Power+Esc+Refresh -> recovery mode 2. Press power -> off 3. Press power -> boots normally (NOT recovery) Change-Id: I9288785ce1c0a446867dc54d1b6ec2f556896688 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32426 Reviewed-by: Simon Glass <sjg@chromium.org>
* Add host command to dump charge state machine contextVic Yang2012-09-103-0/+50
| | | | | | | | | | | | | This is a temporary debug command and will be reverted once unnecessary. BUG=chrome-os-partner:12801 TEST=Manual BRANCH=link Change-Id: Ib1b4221db31ed2521762ee32748bd9d2e177229d Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32696 Reviewed-by: Rong Chang <rongchang@chromium.org>
* snow: Stop discharging when temperature lower than 0CRong Chang2012-09-091-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Rong Chang <rongchang@chromium.org> BRANCH=snow BUG=chrome-os-partner:13844 TEST=manual When run on battery, system will poweroff on battery temperature < 0C. Change-Id: Ib7f3a5f5149f038e83c67c7ca86f8eb22c4b1a7b Reviewed-on: https://gerrit.chromium.org/gerrit/32686 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* Check boot key combos if refresh key is held downRandall Spangler2012-09-092-22/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of how it is now, where the boot key combinations are only tested if it was a keyboard-controlled reset. This is important for testing/debugging EC software sync, which has a tendancy to blow away your RW EC as soon as you flash a test EC and it reboots. Now you can hold down refresh+downarrow while flashing. This does not affect keyboard-controlled dev switching, since that's done in the AP after the EC boots. It also does not add any new key combos, just makes it possible to trigger the existing ones without a Silego reset. BUG=chrome-os-partner:13753 BRANCH=link TEST=manual 1. Boot normally. Works. 2. Power+Refresh. Boots normally. 3. Power+Refresh+Esc. Boots to recovery. 4. Power+Refresh+Down. EC reboots, system powers down. 5. Hold down Esc and reboot from EC console. Boots normally. 6. Hold down Refresh+Esc and reboot from EC console. Boots to recovery. Change-Id: Iabe4fd13589428a40b83f591ea679cbc6f83959d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32425 Reviewed-by: Simon Glass <sjg@chromium.org>
* Switch to variable-size stacksRandall Spangler2012-09-0925-188/+260
| | | | | | | | | | | | | | | | | | | | Increase stack size slightly for vboot hash task since the vboot SHA256 function allocates ~300 bytes of stack data. Reduce stack size for watchdog, power LED, and a few other tasks with simple call trees where we can be sure an error path isn't going to blow past the reduced stack. This frees up ~1KB of RAM on STM32. BUG=chrome-os-partner:13814 BRANCH=all TEST=boot system; shmem should show more unused RAM; taskinfo should show tasks still have unused stack Change-Id: I47d6b77564a0180d15d86667cc0566a8919b776e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32608 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Allocate stacks separately from task context structsRandall Spangler2012-09-091-42/+63
| | | | | | | | | | | | | This is a precursor to supporting task-specific stack sizes. BUG=chrome-os-partner:13814 TEST=boot; taskinfo shouldn't print garbage BRANCH=all Change-Id: Iff6cee8b5f292dd026244239c99ba2252e75cf12 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32592 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Track current task directly instead of computing from stack pointerRandall Spangler2012-09-093-53/+15
| | | | | | | | | | | | | | | This is a precursor to supporting task-specific task sizes. I've benchmarked this vs. the current stack pointer method; no measurable performance difference. BUG=chrome-os-partner:13814 TEST=boot EC; taskinfo; if it boots and doesn't print garbage, it worked BRANCH=all Change-Id: Ia326c3ab499ac03cce78dbacaa52f735601a171e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32603 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* snow: make pmu charge ranges inclusiveDavid Hendricks2012-09-081-2/+2
| | | | | | | | | | | | | | | | | Since we work with integral values for battery temperature, lower limits need to be inclusive when determining when to enable/disable charging. Signed-off-by: David Hendricks <dhendrix@chromium.org> BRANCH=snow BUG=none TEST=none (yet...) Change-Id: Icfc52066ca469b56ebc411bad864111848eab197 Reviewed-on: https://gerrit.chromium.org/gerrit/32652 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>
* snow: re-configure I2C arbitration pins at AP off/on to fix leakageDavid Hendricks2012-09-071-15/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This (re-)configures the I2C arbitration lines as floating inputs when the AP powers off, and restores them strictly before the AP powers on. This is intended to prevent leakage when the AP is off and arbitration is not needed. This CL does not impact the AP on/suspend case. Signed-off-by: David Hendricks <dhendrix@chromium.org> BRANCH=snow BUG=chrome-os-partner:12573,chrome-os-partner:12381 TEST=manual (see notes below) - PA4: SPI1_NSS / AP_CLAIM, input w/ pull-up when AP on - PA6: SPI1_MISO / EC_CLAIM, output when AP is on - Both floating when AP off 8 = input with pull up/down, 4 = floating input, 1 = output AP off (before this CL): > rw 0x40010800 read 0x40010800 = 0x41484144 > gpioget SPI1_NSS 0* SPI1_NSS > gpioget SPI1_MISO 1 SPI1_MISO AP off (after this CL): > rw 0x40010800 read 0x40010800 = 0x44444144 > gpioget SPI1_NSS 0* SPI1_NSS > gpioget SPI1_MISO 0* SPI1_MISO AP on or suspended (before and after this CL): > rw 0x40010800 read 0x40010800 = 0x81484144 > gpioget SPI1_NSS 1* SPI1_NSS > gpioget SPI1_MISO 1* SPI1_MISO Additional testing: - "pmu 10000" and "cros_test i2c" in u-boot only showed the FET2 control changing (as expected). - "pmu 10000" and "while [ 1 ] ; do i2cdump -f -y -r 0-24 4 0x48 b ; done" and ran "suspend_stress_test" for a couple dozen iterations. The registers only changed as expected (FET1 and FET6 turned off when suspending). Change-Id: I72f5cb1883d01b1faad6c2db65dfa09d477e1885 Reviewed-on: https://gerrit.chromium.org/gerrit/32078 Commit-Ready: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>
* Track amount of stack used for each EC taskRandall Spangler2012-09-072-5/+31
| | | | | | | | | | | BUG=chrome-os-partner:13814 TEST=taskinfo; should show stack used per task BRANCH=all Change-Id: Ie40a70a8647c767ea6ec3d164f81c63b62b5008e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32590 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Snow: Always reset i2c when it's initiallizedCharlie Mooney2012-09-061-63/+25
| | | | | | | | | | | | | | | | | | | | Previously, the i2c init code would only preform a software reset of the i2c peripheral it is initializing when it was already BUSY. It turns out it's always BUSY and the init functions are now used in two other places where they always want the software reset as well, so this pulls out the conditional, and makes it always do it. BUG=chrome-os-partner:13388 TEST=Standard i2c stress tests. Running a loop of i2cdumps from the AP while looping i2c transactions on the EC run without any errors. Even across multiple reboots, and jumping back and forth from RO to RW on the EC via sysjump while the AP is still stressing the bus. BRANCH=snow Change-Id: I6b3aaae0042844033bb04cf5cb4171c8be041ad9 Signed-off-by: Charlie Mooney <charliemooney@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32397 Reviewed-by: Simon Glass <sjg@chromium.org>
* gaia_power: Report power on reasonSimon Glass2012-09-061-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Report the reason for a power on, to assist with debugging. BUG=chrome-os-partner:11307 BRANCH=snow TEST=manual Build and boot on snow See that power on reason is now reported > 0.003508 power on 2 [0.028674 AP running ...] ... 12.163780 ending loop 2 Shutdown complete. [batt] state discharging -> idle 17.801167 power on 4 Overriding CHARGER_INT with CHARGER_INT on EXTI4 [17.825873 AP running ...] 17.826071 XPSHOLD seen [batt] state idle -> discharg Change-Id: I2044419b330a74d19d8c4e63fa8853aa477b4df1 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32301 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* make build_info fixed-lengthDavid Hendricks2012-09-061-2/+5
| | | | | | | | | | | | | | | | | | | This makes build_info fixed-length so that it can be properly transmitted via I2C. The host buffer size will be used, which may in fact be quite a bit longer than necessary. Build info will be truncated if it's longer than the max response size. Signed-off-by: David Hendricks <dhendrix@chromium.org> BRANCH=snow BUG=chrome-os-partner:11608 TEST=Tested on Snow, logic analyzer confirmed NAK and STOP condition set properly after final byte transmitted via I2C (see BUG) Change-Id: Iccae0f3c2905d442c8eebff42aa19bf940e5f71f Reviewed-on: https://gerrit.chromium.org/gerrit/32290 Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org> Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>
* stm32: Store VbNvContext in backup registersChe-Liang Chiou2012-09-055-0/+107
| | | | | | | | | | | | | | | | | | | | | | This would improve boot speed when compared to storing in eMMC because initialing eMMC is slow. So far other platforms do not have this need because CMOS is quite efficient; thus it is left unimplemented in lm4. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> BRANCH=snow BUG=chrome-os-partner:10660,13094 TEST=On Snow, see VbNvContext is preserved across power cycles (you have to patch U-Boot to test this) Change-Id: If5072c678b87bc47a3a82a1dff2afa3896304f36 Reviewed-on: https://gerrit.chromium.org/gerrit/31832 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
* Snow:Recover from stray pulses on i2c battery lineCharlie Mooney2012-09-051-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C peripheral on the EC can get confused if there is a very specific kind of noise introduced to the line. This can be manifested by jiggling the battery jack. It gets the I2C into a state where everything seems fine outwardly, but the device refuses to even transmit START bits on the line. It appears that one of the stray pulses on the i2c bus gets the device off set from the actual bytes, leaving it misinterpreting everything and waiting forever. In this case, there is only one way to recover (as you can't directly access these aspects of the internal state) and that is to do a software reset of the i2c peripheral. Here I add some code to check for the condition where the EC was unable to even send a START bit, and do a software reset of the i2c to recover. BUG=chrome-os-partner:13161 TEST=With a faulty-battery-jack-board: Boot board, test that i2c works by running "pmu" on the EC console. Jiggle battery jack repeatedly until errors are displayed on console. Try to run pmu again. Make sure that it recovers gracefully, and do this many times. BRANCH=snow Change-Id: I91b8ef0c6f6079bc63f4a6a1bc91f67d19db9fc0 Signed-off-by: Charlie Mooney <charliemooney@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32286 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* snow: i2c: Reset i2c busses at bootup to unwedge themDavid Hendricks2012-09-051-4/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the EC got reset while some device on the bus was midway through a transaction, the bus may we wedged and all of our i2c transactions will fail. Try our best to unwedge the bus at bootup. Do this even if the bus doens't look wedeged because some device on the bus may be in a quiescent state at the moment but be waiting to pounce on the bus when it sees the clock start running. BUG=chrome-os-partner:13378 TEST=Capture scope trace in normal bootup TEST=Capture scope trace in failure bootup with an extra print statement in the code when scl/sda were not high at bootup. Forced this case by looping i2c transactions to tpschrome and rebooting midway through. BRANCH=snow Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> (Note: Credit for this patch goes to Doug, I just uploaded the initial work-in-progress version to gerrit --dhendrix) Change-Id: I8da69b5294160048f91461159c039f8f2093e971 Reviewed-on: https://gerrit.chromium.org/gerrit/32168 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
* stm32l: Add stub for gpio_set_flags()David Hendricks2012-09-051-0/+9
| | | | | | | | | | | | | | | | This is just to get around compilation failures caused in shared stm32f/l code. BRANCH=snow BUG=none TEST=compiled ec-utils for daisy Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I0f6e984ce22ae6f71d47053d801f1c62af54a45b Reviewed-on: https://gerrit.chromium.org/gerrit/32262 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
* daisy: add GPIO_I2C_* pins to board header and GPIO tableDavid Hendricks2012-09-052-1/+12
| | | | | | | | | | | | | | | | This adds the I2C pins to the listing of Daisy GPIOs. This allows us to use GPIO_I2C_* for shared Daisy/Snow code. BRANCH=snow BUG=none TEST=compile tested for Daisy and Snow Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I7413921b2dbe3f8cd79c88ab4bfc8ace0d72bd56 Reviewed-on: https://gerrit.chromium.org/gerrit/32261 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
* Change UART interrupt to priority 2Simon Glass2012-09-051-1/+1
| | | | | | | | | | | | | | | The UART probably shouldn't have such a high priority. Reduce it to below that of comms driver interrupts. BUG=none BRANCH=none TEST=manual Boot and see that UART console still functions Change-Id: If906c9c4c37617d076ad8415d126b50f52d8b09e Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32077 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Snow: Add checking for more i2c error casesCharlie Mooney2012-09-051-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a number of ways for the i2c to fail, and some are quite rare and have thus been overlooked. It's easy enough to handle these rationally, but we have to check for them. This checks that the i2c peripheral is actually in slave mode when it gets a slave event firing (stopping it from accidentally sending garbage on the tail end of another request) and makes sure a STOP bit is sent in the event that the BUSY signal isn't set at the moment we check it (if we check it at the moment that it is sending a 1, it may not be set). Finally, if the i2c can't send a STOP bit, the peripheral is reset to get it back to a sane state, specifically it needs to not be stuck in master mode forever. BUG=chrome-os-partner:13380 TEST=Boot machine normally, from AP run "while true; do ectool version; done" to start a loop of the long transaction that sends lots of spurious reads too. Then on the EC, run "pmu 10000" and then "battery 1000" to stress the bus from all sides. Once the EC is done, stop the AP's side of the stress test, and make sure the bus is still functioning. Tested the resetting, by making it reset the peripheral every 150 times, and confirmed that the following transfers work just fine. BRANCH=snow Change-Id: I265b3cddd25e1fd6ab4e8cf9c7290c875fad89f8 Signed-off-by: Charlie Mooney <charliemooney@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32188 Reviewed-by: Doug Anderson <dianders@chromium.org>
* Add host command to get panic infoRandall Spangler2012-09-052-0/+32
| | | | | | | | | | | | | | | | | | | This only adds support in the EC; it doesn't add an ectool command. We'll add that later. This also fixes a bug where the reserved byte in the panic data structure wasn't being set to 0. BUG=chrome-os-partner:7466 BRANCH=all TEST=manual 1. crash unaligned -> system crashes 2. hostcmd 0xd3 -> returns a hex string 01010100...506e6321 3. hostcmd 0xd3 -> returns a hex string 01010500...506e6321 Change-Id: I1de8e19c44c835055d893986b42d152dc704c35f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32183 Reviewed-by: Simon Glass <sjg@chromium.org>
* stm32: Squeeze fakewp backup register for VbNvContextChe-Liang Chiou2012-09-051-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We squeeze 2 bytes out of fakewp backup register so that we would have full 16 bytes for VbNvContext. As fakewp will go away real soon and it needs just 1 bits, we move it to saved reset flags register's most significant bit, which is currently unused. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> BRANCH=snow BUG=chrome-os-partner:10660,13094 TEST=manual Make sure reset flags are still preserved: 1. reset with keyboard. flags -> reset-pin 2. trigger watchdog reset. flags -> reset-pin watchdog 3. 'reboot soft preserve' flags -> reset-pin watchdog soft 4. trigger watchdog reset. flags -> reset-pin watchdog 5. 'reboot soft' flags -> reset-pin soft Make sure fakewp is still preserved: 1. 'flashinfo' -> no flags 2. 'fakewp 1' -> 'wp_gpio_asserted' 3. 'flashwp enable' -> 'wp_gpio_asserted ro_at_boot' 4. 'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now' 5. 'fakewp 0' -> 'ro_at_boot ro_now' 6. 'reboot' -> 'ro_at_boot' 7. 'fakewp 1' -> 'wp_gpio_asserted ro_at_boot' 8. 'flashwp rw' -> 'wp_gpio_asserted ro_at_boot rw_at_boot' 9. 'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now rw_at_boot rw_now' 10.'flashwp disable'-> error 7 11.'flashwp norw' -> 'wp_gpio_asserted ro_at_boot ro_now rw_now' 12.'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now' Change-Id: Ibb7dc8aa224d3226bbaac217e494565e448b5858 Reviewed-on: https://gerrit.chromium.org/gerrit/32041 Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* comm-i2c.c upgrades to protocol v2.Louis Yung-Chieh Lo2012-09-052-51/+78
| | | | | | | | | | | | | | | | | | | | | | | | Old i2c code uses protocol v1, which cannot handle veriable-length response (unknown lenght to calculate checksum). So, upgrade to procotol v2 anyway since command v1 needs protocol v2. BUG=chrome-os-partner:11608, Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> BRANCH=None TEST=on snow, and both command v0/v1 are working on protocol v2. ectool version ectool hello ectool echash ectool flashinfo ectool flashprotect ectool flashwp Change-Id: Id8532fe51359dce18839d37de8a8c8669754041c Reviewed-on: https://gerrit.chromium.org/gerrit/31838 Commit-Ready: Yung-Chieh Lo <yjlou@chromium.org> Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org> Tested-by: Yung-Chieh Lo <yjlou@chromium.org>
* Calibrate IR temperature sensors for Link DVTVincent Palatin2012-09-041-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | The TMP006 IR sensors are calibrated against the temperature measured on the *external* side on the casing using a thermocouple stick at the vertical of the sensor. The hinge sensor is sending back strange values, and the Tobject from there should not be trusted. The DC-Jack C-case sensor is not calibrated (and will be removed soon). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on Link DVT, compare EC temperature values against thermocouple readings. BRANCH=link Change-Id: I03375dd1c2f3a0aa56b0d2f343dad3b8f7581bc2 Reviewed-on: https://gerrit.chromium.org/gerrit/32156 Reviewed-by: Sameer Nanda <snanda@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Fix stack overflow in hostcmd commandRandall Spangler2012-09-041-5/+21
| | | | | | | | | | | | | | It was putting the entire parameter buffer for a host command on the stack. Now it uses shared memory. BUG=chrome-os-partner:13613 TEST='hostcmd 4' should not cause a crash several seconds later BRANCH=link (snow is also affected, but doesn't have enough shared memory to put the command buffer there either) Change-Id: I8405d88857ee92a5cee429e156df5e645d5d864d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32181 Reviewed-by: Vic Yang <victoryang@chromium.org>
View Lorry Controller Status