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* poppy: Enable usb device modeFurquan Shaikh2018-04-263-3/+9
| | | | | | | | | | | | | | | | | BUG=b:78577893 BRANCH=poppy TEST=Verified following: 1. ectool usbpd 0 dr_swap 2. ectool usbpd 0 --> Role: SNK UFP Change-Id: Ie1130eba3da4352e2a3e09eaad20886a1bea81a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029539 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* yorp: lower i2c speeds to 100kHzJett Rink2018-04-261-2/+2
| | | | | | | | | | | | | | | | | | We need to tune the i2c parameters for the nuvoton chip on our yorp board to be able to operate at 400kHz. Currently we do not need the extra speed or bandwidth, so we are reverting to a lower speed where the default timing parameters work well. BRANCH=none BUG=b:78554726,b:78225299 TEST=HDMI over TypeC works on yorp This reverts commit 2e7e6665b1e712a950eef8ae3d3f64ae0f1d2ec1. Change-Id: Ic4ba1d5ef25661bd6c7f9490450af65b4e1393ad Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1028752 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* it83xx: implement reboot wait-extNick Sanders2018-04-251-12/+13
| | | | | | | | | | | | | | This was missed on it83xx, but is helpful for servod to work reliably. Refactor save_flags to use common code. BUG=b:77830536 TEST=(not yet done) it waits 10 sec for external reboot. Change-Id: Ia2aac1879d73ac11dd7f3dfc13a1dd871905473e Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1018597 Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Nami: Control LED for AkaliDaisuke Nojiri2018-04-252-27/+69
| | | | | | | | | | | | | | | | | | | This patch adds LED control for Akali. Akali needs to show an irregular pattern in S3 (On 1 sec off 3 sec). This patch adds 'alternate' mode support. It allows an LED to extend off period. In alternate mode, an LED goes through on-off-off-off cycles. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:77827579 BRANCH=none TEST=Verify on Nami. Change-Id: Ia7541236a6c598173cb94089224ac8c0a3f63a68 Reviewed-on: https://chromium-review.googlesource.com/1024691 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Sona: Blink LED when battery is lowDaisuke Nojiri2018-04-251-1/+11
| | | | | | | | | | | | | | | | | This patch makes the battery LED on Sona blink in white when the state of charge is below 10%. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:74940319 BRANCH=none TEST=Verify battery LED blinks when soc is below 10%. Change-Id: Iee731a63787496ac15d97555564c8b02e1923256 Reviewed-on: https://chromium-review.googlesource.com/1020660 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* USB PD: Send SoftReset if in explicit contract at init.Aseda Aboagye2018-04-251-6/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, if a board supports dual role power ports, the EC will briefly apply Rp resistors on the CC lines upon initializing the PD tasks. This was put in place such that the partner port is a known state. In the case of an external PD charger, the presence of the Rp will cause the charger to stop sourcing VBUS. We only apply the pull up for reset cases where the EC did not just loose power (e.g. power on reset or brownout). This however presents a problem when booting off of AC only. If a user types 'reboot ap-off', there will be an extra reset because VBUS is dropped and the "ap-off" flag will be lost. This commit simply checks to see if there is an explicit contract in place for a port. If an explicit contract is in place and PD communications are allowed, we will not apply the Rp resistors. The PD state machine will then attempt to send a SoftReset to the port partner in order to reset the PD protocol layer. If an explicit contract is not in place, or if PD communications are not allowed, the Rp's will be asserted briefly as before. BUG=b:72838807,b:35587129,chromium:712746 BRANCH=None TEST=Flash zoombini; Remove battery and plug in just AC; Enter `reboot ap-off` and verify that AP remains off in the subsequent boot and there is no extra reset. TEST=Make zoombini locked. Have a PD contract in RW, reboot to RO and verify that VBUS is dropped from a PD charger. TEST=Repeat test on meowth. CQ-DEPEND=CL:905922 Change-Id: Ie2e3fe5b6b318e166b2a42dfa3241646369ec571 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/905390 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* pd: Properly assign data role on resetAseda Aboagye2018-04-252-30/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to PD spec: - Data role shall not be reset on soft reset. - Data role shall be reset to power-role default on hard reset. Implement the above. Even if both ports follow spec, it's still possible for a data role conflict to occur if, for example, data role swap occurs (data role mismatches power role default) followed by a hardware reset of one port (such that data role gets reset to power role default). Handle such cases by taking error recovery actions. BUG=b:71333840,chromium:805040 TEST=Connect scarlet to powered Apple accessory, verify scarlet comes up in SNK-DFP after soft reset and issuing "reboot" on EC console. After issuing a hard reset, the port comes up in SNK-UFP (which is the power-role default). BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I65139f277d59a0612f8323d711080f52425ff5e7 Reviewed-on: https://chromium-review.googlesource.com/885462 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_v4: Remove `crash` command.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | | Servo V4 is out of space, so remove the crash command to gain some back. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I9e5617de2a41f12f60d1fab246acddbbcfa3bea2 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1022964 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* samus_pd: Enable Link-Time Optimizations.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | BUG=None BRANCH=None TEST=`make -j BOARD=samus` succeeds. TEST=samus_pd is able to boot up and negotiate correctly with zinger. Change-Id: I422be2772df3436bb398ffd3e58096039efcbebe Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/998828 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Save power role in BBRAM.Aseda Aboagye2018-04-252-15/+24
| | | | | | | | | | | | | | | | | | In order to re-initialize our PD state variables properly following a reset, we need to save our current power role. This commit adds a bit in the BBRAM PD flags for the power role. BUG=b:71333840,chromium:805040 BRANCH=None TEST=Add code to save data role and restore both roles, verify that both are saved accordingly. Change-Id: I156ae8179c8e12c63322132d1f0078990bd215f8 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/979264 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kevin: Remove 'pwr_avg' command.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | | Kevin is out of space, so disable this console command to get some back. BUG=None BRANCH=None TEST=make -j buildall Change-Id: Ic24b83187067e16ca438f31250c4272580f1e34f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/922322 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* samus_pd: Remove `crash` command.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | | | | | samus_pd is out of space again (groundhogday.jpg). Remove the `crash` command. This command is needed for a FAFT test (firmware_ECSharedMem) and you cannot qualify a firmware without it. However, for samus_pd, we don't seem to run this test against samus_pd itself, but just samus. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I7e34a1a7a9fcdd36e1d97b1226b66dc3f25213f0 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/917012 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* wheatley: Enable CONFIG_COMMON_GPIO_SHORTNAMES.Aseda Aboagye2018-04-251-0/+2
| | | | | | | | | | | | | | | | | Wheatley needs more space (probably to store his book collection including works of Machiavelli). Therefore, enable CONFIG_COMMON_GPIO_SHORTNAMES to save space. BUG=None BRANCH=None TEST=make -j buildall Change-Id: Ia5dc8d36c9ae8dea6272a28677609f229a835f96 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/917011 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* USB PD: Save explicit contract state for port 2.Aseda Aboagye2018-04-252-24/+75
| | | | | | | | | | | | | | | | | | | | | | pd_get/set_saved_active() made the assumption that there were only two ports. But now, we have a board that turned that port count all the way up to 3. This commit adds in that new port BBRAM index. It also turns the byte where the port information was stored into a byte of flags, where bit 0 indicates whether there was an explicit contract in place or not. BUG=b:72838807 BRANCH=None TEST=With some code to check for explicit contract state for port 2, verify it's functional. Change-Id: I6f062f67bd3c47dd43ea7e24e844a9286fa37af9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/905923 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: Add BBRM idx for a 3rd PD port.Aseda Aboagye2018-04-253-1/+7
| | | | | | | | | | | | | | | | | | | Currently, there's only one board with 3 PD ports and it uses NPCX. Therefore, this commit just adds the index to NPCX which will be used to save the fact that there was an explicit contract in place. BUG=b:72838807 BRANCH=None TEST=make -j buildall CQ-DEPEND=CL:905390 Change-Id: Ic960f14a52f2a740adbe08bc340c45edfefbbf26 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/905922 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ectool: add a workaround for EC_CMD_FP_TEMPLATEVincent Palatin2018-04-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | When issuing a host command whose request packet length is equal to the maximum size (ie max_request_packet_size as returned by EC_CMD_GET_PROTOCOL_INFO), the command currently fails with STM32H7 over SPI host protocol. The finger template upload through the EC_CMD_FP_TEMPLATE host command fails due to the issue as it 'optimizes' the chunk length to the maximum size. For now, workaround this issue by removing a 32-bit word (aka 4 bytes) to max_request_packet_size, so we never hit this corner case. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:78544921 TEST=On Meowth, run 'ectool --name=cros_fp fptemplate finger0.bin' and see it succeeding. Change-Id: I52072ddeb12534045c37ab30df301a60c8841199 Reviewed-on: https://chromium-review.googlesource.com/1026680 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* PD: Leave Vbus ON if Vconn and Vbus Requested is set to 0 in the AMA VDOSam Hurst2018-04-251-6/+6
| | | | | | | | | | | | | | | | | | | | While troubleshooting why a generic $19.99 Multiport (USB, HDMI, Type-C) Type-C dongle didn't work on Scarlet, I noticed that Vconn Req and Vbus Req were both set to zero in the AMA VDO. For a better user experience, default to Vbus ON if both Vconn and Vbus Req are both zero. BUG=b:78286905 BRANCH=NONE TEST=manual Tested the generic dongle with USB-Keyboard, TypeC power adapter, and HP monitor. Change-Id: I170eef1372c3621334de2c457bd4533eea744cc0 Signed-off-by: Sam Hurst <shurst@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1019611 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* board/yorp: fix PMIC_EN gpioAaron Durbin2018-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | Apparently the symbol in the yorp schematic is incorrect for our part. The PMIC_EN signal on ball H6 is actually GPIO72 -- not GPIOD7. Adjust the gpio used for PMIC_EN. Note: GPIO72 needs to be put in gpio mode since it defaults to PWRGD functionality. However, gpio_pre_init() in chip/npcx/gpio.c enables gpio functionality by default. If that changes, the board options will need to change as well. BUG=b:78352179 TEST=Built. Booted. PMIC_EN goes up and down as expected. BRANCH=none Change-Id: I955f9a24e0fbecb0cda1380c237fa44c9a575e45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1026375 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* board/yorp: set the correct chip variantAaron Durbin2018-04-251-1/+1
| | | | | | | | | | | | | | | | | The yorp build is using part NPCX796FB0BX which evidently maps to npcx7m6xb. Therefore, set the correct variant to reflect reality. BUG=b:78352179 TEST=Built. Booted. BRANCH=none Change-Id: I3835b4664429c360ea946aad0a7bf3dc32f6eea1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024608 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* bip: set correct AC_PRESENT debouce delayJett Rink2018-04-241-1/+6
| | | | | | | | | | | | BRANCH=none BUG=b:75974377 TEST=none Change-Id: Ib6fcc0ac7668614a487525196ea4f3a5f399c640 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024278 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* flash_ec: fix handling ccd controlsMary Ruthven2018-04-241-11/+13
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=use ccd uut to flash meowth and ccd bitbang to flash scarlet Change-Id: I83ba0c82f66b698d4083649637d2f74a85db9bc4 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1025265 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* bip: add cbi board versionJett Rink2018-04-242-1/+4
| | | | | | | | | | | BRANCH=none BUG=b:78473271 TEST=none Change-Id: Ic7b500ed33b884c59036c41b9ce3e7925637ee69 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024962 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* bip: use ITE as TCPC driver for C1Jett Rink2018-04-242-17/+19
| | | | | | | | | | | | | | The PS8751 is only being used as mux with the option of being a TCPC is we stuff resistor on the subboard. The default resistor configuration uses ITE EC as C1 TCPC. BRANCH=NONE BUG=b:78341944 TEST=none Change-Id: I4ccad314fa7eec0d205a155e42e52109cff5811f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024487
* mux: add mode for TCPCI mux that is not the TCPCJett Rink2018-04-243-8/+32
| | | | | | | | | | | | | | We need to use the PS8751 as the USB mux without configuring it as the TCPC. Add mode that allows passing in i2c port and address instead using tcpc_config_t values. BRANCH=none BUG=b:78341944 TEST=build using bip Change-Id: I45b420ef890dfa8c5e5052864b7a2bb66d8734d6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024486
* yorp: Enable temperature sensorsDivya Sasidharan2018-04-243-3/+105
| | | | | | | | | | | | | BUG=b:77944804 BRANCH=None TEST=On yorp; test adc values, verify they are valid. Change-Id: I64191f33c594d8869391bab813902f59a63d2ea1 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1018118 Commit-Ready: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Tested-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50_rma_open: add servod supportMary Ruthven2018-04-241-3/+50
| | | | | | | | | | | | | | | | | Add support for finding the cr50 uart given a servo port or being given a servo console using -d. If servod is using ccd to run, we need to do ccd_reset after the authcode reboot. Add support for that as well. BUG=none BRANCH=none TEST=none Change-Id: I972ce60a2e67cc68b604d550579fb2e99db8ac08 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1025267 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* chip/stm32/clock: Align to second for rtc alarm host commandPhilip Chen2018-04-241-9/+20
| | | | | | | | | | | | | | | | | | | BUG=b:74256016 BRANCH=scarlet CQ-DEPEND=CL:1025118 TEST=On scarlet, run 'date; powerd_dbus_suspend --wakeup_timeout=10; date', confirm alarm works and the sleep time is ~10 secs TEST='idlestat' when scarlet is in S3, confirm scarlet enters sleep mode and wakes up without missing wake deadline TEST=Run 'power_Resume' test on scarlet for 10 times and see consistent 'seconds_system_resume' Change-Id: I4b0cbc2a6b8a85047b682358aec374e8f05a4346 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1008838 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* usb_mux: Simplify logging to reduce code sizePhilip Chen2018-04-241-5/+5
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Change-Id: Ib2d9476e4740527ad2e1f73eeecb0306140b3f38 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1025118 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ps8751: add note to revert vbus detection workaroundJett Rink2018-04-231-1/+8
| | | | | | | | | | | | | | Once the PS8751 has new firmware, it will be able to detect VBus at the appropriate time. After that, we can go back to using the cached version of Vbus detection. BRANCH=none BUG=b:77639399 TEST=none Change-Id: I691919f3bd2479a131aa58763c7906cb4f6919ff Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024531
* flash_ec: For npcx_uut, use servo to boot EC into the flashing modeWai-Hong Tam2018-04-231-0/+16
| | | | | | | | | | | | | | | | | Use servo to boot EC into the flashing mode. Use the unified control ec_boot_mode to do so. CQ-DEPEND=CL:1018206 BRANCH=none BUG=b:68707064 TEST=Ran the flash_ec script on Cheza using servo-micro TEST=Ran the flash_ec script on Meowth using CCD, with some servo overlays to drive the ccd_ec_boot_mode control Change-Id: I32dfe5baa82dd842b5237f38ea971c09e91c47d3 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1020159 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* bq25703: initial commit for bq25703 driverJett Rink2018-04-234-0/+268
| | | | | | | | | | | BRANCH=none BUG=b:76429930 TEST=building with bip Change-Id: Ibed206e1e0b578b3a4b70709509a7288284fc23b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1019606 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* hammer: Disable side-band wake using detection pinNicolas Boichat2018-04-231-24/+0
| | | | | | | | | | | | | | | | | Side-band wake was only useful when the lid would go in deep-S3, where the USB interface is disabled. Since we are using S0ix on poppy and derivatives, the side band wake is useless, and, in some rare case, may actually cause issues. BRANCH=poppy BUG=b:77828249 TEST=Flash staff, can wake soraka from suspend, or from USB autosuspend. Change-Id: I23398a792157b32a5d79505dcffc92aaffd4fec2 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1011523 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Disable ALS for Pantheontoobest542018-04-231-2/+3
| | | | | | | | | | | | | | Use OEM ID to update motion_sensor_count to disable ALS for Pantheon. BUG=b:77937854 BRANCH=none TEST=Change oem id for Pantheon then to check the ALS was disabled. Change-Id: I4cb2ad16f3413a65b6f2df84eae2d1ced37b72f6 Signed-off-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1010182 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Carter Sung <carter_sung@compal.corp-partner.google.com>
* meowth_fp: enable PCH interface in S0Vincent Palatin2018-04-222-6/+35
| | | | | | | | | | | | | | | | | | | | Enabling the SPI slave interface and the host interface depending on the detected PCH power state. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:71986991 TEST=On Meowth, check that the MCU interrupt is seen on the CPU side and we can still send host commands. TEST=On ZerbleBarn, verify that the SPI slave interface is enabled at startup. Change-Id: Ie7b22e69178bc7d34be6ab28ab24db82fefd5a02 Reviewed-on: https://chromium-review.googlesource.com/966023 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* stm32: more robust SPI slave on STM32H7Vincent Palatin2018-04-221-6/+8
| | | | | | | | | | | | | | | | | | | | | Try to ensure the SPI host protocol byte codes (aka EC_SPI_xxx) are transmitted and at the right time despite the errata and other brokenness of the SPI HW controller in the STM32H7 rev Y silicon. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:73947203 TEST=on Meowth, run: 'while true; do ectool --name=cros_fp version || break ; done' same thing with 'fpinfo', 'fptemplate', 'fpframe'. Change-Id: Ia455dc0d4b2803a150122655460ef5c11afcda6c Reviewed-on: https://chromium-review.googlesource.com/1012202 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* meowth: Only power base when AP is on.Aseda Aboagye2018-04-201-16/+46
| | | | | | | | | | | | | | | | | | | | | | | | | Previously, the base power was enabled when the base was detected by the lid. However, we should only power the base when the AP is on since it just wastes power otherwise. This commit adds a pair of chipset hooks to kick the state machine on startup and disable it on shutdown. BUG=None BRANCH=None TEST=Flash meowth, attach base with AP off, verify that base power is not enabled. TEST=Remove base and attach base, verify that base power is disabled when removed and enabled when attached. TEST=Shut AP down, verify that base power is disabled. TEST=Remove base and attach base, verify that base power remains disabled. TEST=Power on AP with base detached, verify that base power remains off. Change-Id: I4379789987dbe91c72d699c4d184b5c5cc812e5f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1020525 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* power/rk3399: Check aborted suspend for s0s3_usb_wake_power_seqPhilip Chen2018-04-201-1/+5
| | | | | | | | | | | | | BUG=b:78321971 BRANCH=scarlet TEST=build kevin and scarlet Change-Id: I9e0c842cd8f4186147fa8e6d001b1c21ddad7e89 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1022746 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org>
* flash_ec: remove redundant sudoCaveh Jalali2018-04-201-1/+1
| | | | | | | | | | | | | | | | we were invoking flashrom as "sudo sudo flashrom", so remove the gratuitous sudo. BUG=none BRANCH=none TEST=used flash_ec to flash atlas Change-Id: I420ada94c4b973c8f7efe546670dd04cfbb1b234 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020782 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: update GPIO names to match new schematicsCaveh Jalali2018-04-202-15/+15
| | | | | | | | | | | | | | | | | | the latest schematics have been updated to reflect the I2C bus numbering used in the chip datasheets. this updates the software to be consistent with the new datasheets. this is only a renaming exercise, there are no physical changes to the board. BUG=b:75070158,b:78309559 BRANCH=none TEST=it compiles Change-Id: I16e6741c2e8a1dcc32b814a50ba12739f36fd8cf Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020721 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tcpm: Check appropriate NULL pointer for src ctrlDivya Sasidharan2018-04-201-1/+1
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=On yorp; make buildall -j Change-Id: I804f82fd4d3f71080fa2a3ced02dca785a3e9891 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1020523 Commit-Ready: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Tested-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Sona: Blink LED on battery errorDaisuke Nojiri2018-04-201-13/+20
| | | | | | | | | | | | | | | | | | | | | This patch makes the battery LED blink at 0.5 sec interval in white when battery error is detected. This patch also changes the pulse interval resolution from 1 sec to 100 msec. There is no functionality change. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:74940319 BRANCH=none TEST=Verify pulsing and blinking are not affected. Verify battery LED blinks as intended on Sona. Change-Id: I0767a6004861b9f07bc846d2ba5bf0df9067a748 Reviewed-on: https://chromium-review.googlesource.com/1017305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* yorp: Fix force mode base accel configDivya Sasidharan2018-04-202-5/+7
| | | | | | | | | | | | | | | | Accel data read was (0, 0) without this change. BUG=b:74602071 BRANCH=None TEST=On yorp; on EC console test accelinfo on -> gives accel data Change-Id: I08073cccb2108b5d2189be5aa27a77adfae7677a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1015974 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* power/common: Preserve 5v enable across sysjumpJustin TerAvest2018-04-191-0/+25
| | | | | | | | | | | | | | | | | | | | | | The value of pwr_5v_en_req needs to be preserved when the EC performs a sysjump, otherwise any task calling power_5v_enable(tid, 0) will drop the 5v rail for the entire system. I've scheduled this at HOOK_PRIO_FIRST for restoring the value to ensure that no other init hooks read a stale value, but I'm not sure if that's necessary. BUG=b:78275296 BRANCH=none TEST=Booted yorp with power only connected to USB-C port 0 Change-Id: I3a9ed24a5fde02b60163ad2c5e3252759f8c1c5b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020066 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* flash_ec: Save the original servo statesWai-Hong Tam2018-04-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | When first supporting CCD, it skips saving the original servo states as some of the controls are not supported in CCD. https://chromium-review.googlesource.com/344427 But then we customized what controls will be used according to the servo board type. https://chromium-review.googlesource.com/572142 So we should save original states again. It helps to restore the original servo states if it gets interrupted in the middle. BRANCH=none BUG=none TEST=Tried running flash_ec using servo-micro. Change-Id: I5b873d871d36feed4a0e511ba858db9e093a22be Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1020158 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* grunt: Send sensor MKBP events using host eventEdward Hill2018-04-191-0/+10
| | | | | | | | | | | | | | Add CONFIG_MKBP_EVENT and CONFIG_MKBP_USE_HOST_EVENT to send sensor events to AP. BUG=b:77342604 BRANCH=none TEST=view sensors in AIDA64 Android app in ARC++ Change-Id: I3687072903d251bccb2cdf7670b0780a906dd22d Signed-off-by: Edward Hill <ecgh@chromium.org> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1012457
* stoney: Use chipset_pre_init callbackFurquan Shaikh2018-04-192-9/+7
| | | | | | | | | | | | | | | | Similar to intel_x86, move chipset stoney to using chipset_pre_init callback. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I995bbda01ec78ecd28c302f269cf15739913ecd9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018738 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK: Move chipset shutdown to chipset taskFurquan Shaikh2018-04-192-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | In order to ensure that all chipset init/shutdown operations happen within the context of chipset task for APL/GLK: 1. Update chipset_force_shutdown to only set a flag force_shutdown to indicate that chipset shutdown is requested and wake the chipset task. 2. Make chipset task (within the power state machine) call internal_chipset_shutdown. 3. Make internal_chipset_shutdown reset force_shutdown flag and make a callback to weak function chipset_do_shutdown to trigger chipset shutdown. BUG=b:78259506 BRANCH=None TEST=Verified that "apshutdown" on EC console results in chipset shutdown action being taken within chipset task. Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018737 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* intel_x86: Get rid of CHIPSET_PRE_INIT hookFurquan Shaikh2018-04-191-3/+0
| | | | | | | | | | | | | | | | | Now that all boards are moved to using chipset_pre_init_callback, get rid of hook notification for CHIPSET_PRE_INIT from x86 power state machine. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I244848b3c80e8ccd34b3c99c8aa2dee3030e0e53 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018736 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* fizz/nami: Use chipset_pre_init_callbackFurquan Shaikh2018-04-194-4/+4
| | | | | | | | | | | | | | | | This change updates fizz/nami boards to use chipset_pre_init_callback instead of hook. BUG=b:78259506 BRANCH=None TEST=make -j buildall Change-Id: Ib09c033c2f0c2c3d324c90776f7bbd8365a71f52 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018735 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK boards: Use chipset_pre_init_callbackFurquan Shaikh2018-04-198-16/+16
| | | | | | | | | | | | | | | | This change updates all APL/GLK boards to use chipset_pre_init_callback instead of hook. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I71ab0f1111e89a254db83fc58abfdfe8eacd3575 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018734 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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